include/asm-sparc/ross.h

/* */
This source file includes following definitions.
flush_i_page
flush_i_seg
flush_i_region
flush_i_ctx
flush_i_user
flush_whole_icache
get_ross_icr
put_ross_icr
   1 /* ross.h: Ross module specific definitions and defines.
   2  *
   3  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5 
   6 #ifndef _SPARC_ROSS_H
   7 #define _SPARC_ROSS_H
   8 
   9 /* Ross made Hypersparcs have a %psr 'impl' field of '0001'.  The 'vers'
  10  * field has '1111'.
  11  */
  12 
  13 /* The MMU control register fields on the HyperSparc.
  14  *
  15  * -----------------------------------------------------------------
  16  * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
  17  * -----------------------------------------------------------------
  18  *  31    24 23-22 21  20  19 18-15 14 13 12 11 10  9   8 7-2  1  0
  19  *
  20  * Phew, lots of fields there ;-)
  21  *
  22  * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
  23  * SE: Snoop Enable, turns on bus snooping for cache activity if one.
  24  * WBE: Write Buffer Enable, one turns it on.
  25  * MID: The ModuleID of the chip for MBus transactions.
  26  * BM: Boot-Mode. One indicates the MMU is in boot mode.
  27  * C: Indicates whether accesses are cachable while the MMU is
  28  *    disabled.
  29  * CS: Cache Size -- 0 = 128k, 1 = 256k
  30  * MR: Memory Reflection, one indicates that the memory bus connected
  31  *     to the MBus supports memory reflection.
  32  * CM: Cache Mode -- 0 = write-through, 1 = copy-back
  33  * CE: Cache Enable -- 0 = no caching, 1 = cache is on
  34  * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
  35  *                 1 = faults from supervisor mode do not generate traps
  36  * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
  37  */
  38 
  39 #define HYPERSPARC_CWENABLE   0x00200000
  40 #define HYPERSPARC_SBENABLE   0x00100000
  41 #define HYPERSPARC_WBENABLE   0x00080000
  42 #define HYPERSPARC_MIDMASK    0x00078000
  43 #define HYPERSPARC_BMODE      0x00004000
  44 #define HYPERSPARC_ACENABLE   0x00002000
  45 #define HYPERSPARC_CSIZE      0x00001000
  46 #define HYPERSPARC_MRFLCT     0x00000800
  47 #define HYPERSPARC_CMODE      0x00000400
  48 #define HYPERSPARC_CENABLE    0x00000100
  49 #define HYPERSPARC_NFAULT     0x00000002
  50 #define HYPERSPARC_MENABLE    0x00000001
  51 
  52 /* Flushes which clear out only the on-chip Ross HyperSparc ICACHE. */
  53 extern inline void flush_i_page(unsigned int addr)
     /*  */
  54 {
  55         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  56                              "r" (addr), "i" (ASI_M_IFLUSH_PAGE) :
  57                              "memory");
  58         return;
  59 }
  60 
  61 extern inline void flush_i_seg(unsigned int addr)
     /*  */
  62 {
  63         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  64                              "r" (addr), "i" (ASI_M_IFLUSH_SEG) :
  65                              "memory");
  66         return;
  67 }
  68 
  69 extern inline void flush_i_region(unsigned int addr)
     /*  */
  70 {
  71         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  72                              "r" (addr), "i" (ASI_M_IFLUSH_REGION) :
  73                              "memory");
  74         return;
  75 }
  76 
  77 extern inline void flush_i_ctx(unsigned int addr)
     /*  */
  78 {
  79         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  80                              "r" (addr), "i" (ASI_M_IFLUSH_CTX) :
  81                              "memory");
  82         return;
  83 }
  84 
  85 extern inline void flush_i_user(unsigned int addr)
     /*  */
  86 {
  87         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  88                              "r" (addr), "i" (ASI_M_IFLUSH_USER) :
  89                              "memory");
  90         return;
  91 }
  92 
  93 /* Finally, flush the entire ICACHE. */
  94 extern inline void flush_whole_icache(void)
     /*  */
  95 {
  96         __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
  97                              "i" (ASI_M_FLUSH_IWHOLE));
  98         return;
  99 }
 100 
 101 
 102 /* The ICCR instruction cache register on the HyperSparc.
 103  *
 104  * -----------------------------------------------
 105  * |                                 | FTD | IDC |
 106  * -----------------------------------------------
 107  *  31                                  1     0
 108  *
 109  * This register is accessed using the V8 'wrasr' and 'rdasr'
 110  * opcodes, since not all assemblers understand them and those
 111  * that do use different semantics I will just hard code the
 112  * instruction with a '.word' statement.
 113  *
 114  * FTD:  If set to one flush instructions executed during an
 115  *       instruction cache hit occurs, the corresponding line
 116  *       for said cache-hit is invalidated.  If FTD is zero,
 117  *       an unimplemented 'flush' trap will occur when any
 118  *       flush is executed by the processor.
 119  *
 120  * ICE:  If set to one, the instruction cache is enabled.  If
 121  *       zero, the cache will not be used for instruction fetches.
 122  *
 123  * All other bits are read as zeros, and writes to them have no
 124  * effect.
 125  */
 126 
 127 extern inline unsigned int get_ross_icr(void)
     /*  */
 128 {
 129         unsigned int icreg;
 130 
 131         __asm__ __volatile__(".word 0xbf402000\n\t" : /* rd %iccr, %g1 */
 132                              "=r" (icreg) : :
 133                              "g1", "memory");
 134 
 135         return icreg;
 136 }
 137 
 138 extern inline void put_ross_icr(unsigned int icreg)
     /*  */
 139 {
 140         __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
 141                              ".word 0xbf802000\n\t" /* wr %g1, 0x0, %iccr */
 142                              "nop\n\t"
 143                              "nop\n\t"
 144                              "nop\n\t" : : 
 145                              "r" (icreg) :
 146                              "g1", "memory");
 147 
 148         return;
 149 }
 150 
 151 #endif /* !(_SPARC_ROSS_H) */
/* */
root/include/asm-sparc/ross.h

INCLUDED FROM

DEFINITIONS
