drivers/net/pi2.c

/* */
This source file includes following definitions.
pi0_preprobe
random
wrtscc
rdscc
switchbuffers
hardware_send_packet
setup_rx_dma
setup_tx_dma
tdelay
free_p
a_txint
a_exint
a_rxint
b_rxint
b_txint
b_exint
hw_probe
rts
pi_header
pi_rebuild_header
scc_init
chipset_init
pi_init
valid_dma_page
pi_set_mac_address
get_dma_buffer
pi_probe
pi_open
pi_send_packet
pi_interrupt
pi_close
pi_ioctl
pi_get_stats
   1 /*
   2    pi2.c: Driver for the Ottawa Amateur Radio Club PI and PI2 interface.
   3    Copyright (c) 1994 David Perry
   4 
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License version 2, as
   7    published by the Free Software Foundation.
   8 
   9    This program is distributed in the hope that it will be useful, but
  10    WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12    General Public License for more details.
  13 
  14    You should have received a copy of the GNU General Public License
  15    along with this program; if not, write to the Free Software Foundation,
  16    Inc., 675 Mass Ave, Cambridge MA 02139, USA.
  17 
  18    The file skeleton.c by Donald Becker was used as a starting point
  19    for this driver.
  20 
  21    Revision History
  22 
  23    April 6, 1994  (dp) Created
  24                        version 0.0 ALPHA
  25    April 10, 1994 (dp) Included cleanup, suggestions from J. P. Morrison.
  26                        version 0.1 ALPHA
  27    April 13, 1994 (dp) Included address probing from JPM, autoirq
  28                        version 0.2 ALPHA
  29    April 14, 1994 (ac) Sketched in the NET3 changes.
  30    April 17, 1994 (dp) Finished the NET3 changes. Used init_etherdev()
  31                        instead of kmalloc() to ensure that DMA buffers will
  32                        reside under the 16 meg line.
  33                        version 0.4 ALPHA
  34    April 18, 1994 (dp) Now using the kernel provided sk_buff handling functions.
  35                        Fixed a nasty problem with DMA.
  36                        version 0.5 ALPHA
  37    June 6, 1994 (ac)   Fixed to match the buffer locking changes. Added a hack to
  38                        fix a funny I see (search for HACK) and fixed the calls in
  39                        init() so it doesn't migrate module based ethernet cards up
  40                        to eth2 Took out the old module ideas as they are no longer
  41                        relevant to the PI driver.
  42    July 16, 1994 (dp)  Fixed the B channel rx overrun problem ac referred to 
  43                        above. Also added a bit of a hack to improve the maximum
  44                        baud rate on the B channel (Search for STUFF2). Included
  45                        ioctl stuff from John Paul Morrison. version 0.6 ALPHA
  46    Feb 9, 1995 (dp)    Updated for 1.1.90 kernel
  47                        version 0.7 ALPHA
  48    Apr 6, 1995 (ac)    Tweaks for NET3 pre snapshot 002 AX.25
  49    April 23, 1995 (dp) Fixed ioctl so it works properly with piconfig program
  50                        when changing the baud rate or clock mode.
  51                        version 0.8 ALPHA
  52    July 17, 1995 (ac)  Finally polishing of AX25.030+ support
  53    Oct  29, 1995 (ac)  A couple of minor fixes before this, and this release changes
  54                        to the proper set_mac_address semantics which will break 
  55                        a few programs I suspect.
  56 */
  57 
  58 /* The following #define invokes a hack that will improve performance (baud)
  59    for the B port. The up side is it makes 9600 baud work ok on the B port.
  60    It may do 38400, depending on the host. The down side is it burns up
  61    CPU cycles with ints locked for up to 1 character time, at the beginning
  62    of each transmitted packet. If this causes you to lose sleep, #undefine it.
  63 */
  64 
  65 /*#define STUFF2 1*/
  66 
  67 /* The default configuration */
  68 #define PI_DMA 3
  69 
  70 #define DEF_A_SPEED 0           /* 0 means external clock */
  71 #define DEF_A_TXDELAY 15        /* 15 mS transmit delay */
  72 #define DEF_A_PERSIST 128       /* 50% persistence */
  73 #define DEF_A_SLOTIME 15        /* 15 mS slot time */
  74 #define DEF_A_SQUELDELAY 1      /* 1 mS squelch delay - allows fcs and flag */
  75 #define DEF_A_CLOCKMODE 0       /* clock mode - 0 is normal */
  76 
  77 #define DEF_B_SPEED 1200        /* 1200 baud */
  78 #define DEF_B_TXDELAY 40        /* 400 mS */
  79 #define DEF_B_PERSIST 128       /* 50% */
  80 #define DEF_B_SLOTIME 30        /* 300 mS */
  81 #define DEF_B_SQUELDELAY 3      /* 30 mS */
  82 #define DEF_B_CLOCKMODE 0       /* Normal clock mode */
  83 
  84 static const char *version =
  85 "PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n";
  86 
  87 /* The following #define is only really required for the PI card, not
  88    the PI2 - but it's safer to leave it in. */
  89 #define REALLY_SLOW_IO 1
  90 
  91 #define PI2_MODULE 0
  92 
  93 #if PI2_MODULE > 0
  94 #include <linux/module.h>
  95 #endif
  96 
  97 #include <linux/kernel.h>
  98 #include <linux/sched.h>
  99 #include <linux/types.h>
 100 #include <linux/fcntl.h>
 101 #include <linux/interrupt.h>
 102 #include <linux/ptrace.h>
 103 #include <linux/ioport.h>
 104 #include <linux/in.h>
 105 #include <linux/malloc.h>
 106 #include <linux/string.h>
 107 #include <linux/errno.h>
 108 #include <asm/system.h>
 109 #include <asm/bitops.h>
 110 #include <asm/io.h>
 111 #include <asm/dma.h>
 112 #include <asm/segment.h>
 113 #include <linux/inet.h>
 114 #include <linux/netdevice.h>
 115 #include <linux/etherdevice.h>
 116 #include <linux/skbuff.h>
 117 #include <linux/timer.h>
 118 #include <linux/if_arp.h>
 119 #include "pi2.h"
 120 #include "z8530.h"
 121 #include <net/ax25.h>
 122 
 123 
 124 struct mbuf {
 125     struct mbuf *next;
 126     int cnt;
 127     char data[0];
 128 };
 129 
 130 /*
 131  *      The actual devices we will use
 132  */
 133  
 134 /*
 135  *      PI device declarations.
 136  */
 137  
 138 static int pi0_preprobe(struct device *dev){return 0;}  /* Dummy probe function */
     /*  */
 139 static struct device pi0a = { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 140 static struct device pi0b = { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 141 
 142  
 143 /* The number of low I/O ports used by the card. */
 144 #define PI_TOTAL_SIZE   8
 145 
 146 
 147 /* Index to functions, as function prototypes. */
 148 
 149 static int pi_probe(struct device *dev, int card_type);
 150 static int pi_open(struct device *dev);
 151 static int pi_send_packet(struct sk_buff *skb, struct device *dev);
 152 static void pi_interrupt(int reg_ptr, struct pt_regs *regs);
 153 static int pi_close(struct device *dev);
 154 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
 155 static struct enet_statistics *pi_get_stats(struct device *dev);
 156 static void rts(struct pi_local *lp, int x);
 157 static void b_rxint(struct device *dev, struct pi_local *lp);
 158 static void b_txint(struct pi_local *lp);
 159 static void b_exint(struct pi_local *lp);
 160 static void a_rxint(struct device *dev, struct pi_local *lp);
 161 static void a_txint(struct pi_local *lp);
 162 static void a_exint(struct pi_local *lp);
 163 static char *get_dma_buffer(unsigned long *mem_ptr);
 164 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize);
 165 
 166 static char ax25_bcast[7] =
 167 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
 168 static char ax25_test[7] =
 169 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
 170 
 171 static int ext2_secrm_seed = 152;       /* Random generator base */
 172 
 173 static inline unsigned char random(void)
     /*  */
 174 {
 175     return (unsigned char) (ext2_secrm_seed = ext2_secrm_seed
 176                             * 69069l + 1);
 177 }
 178 
 179 static inline void wrtscc(int cbase, int ctl, int sccreg, int val)
     /*  */
 180 {
 181     /* assume caller disables interrupts! */
 182     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 183     outb_p(sccreg, ctl);        /* Select register */
 184     outb_p(val, ctl);           /* Output value */
 185     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 186 }
 187 
 188 static inline int rdscc(int cbase, int ctl, int sccreg)
     /*  */
 189 {
 190     int retval;
 191 
 192     /* assume caller disables interrupts! */
 193     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 194     outb_p(sccreg, ctl);        /* Select register */
 195     retval = inb_p(ctl);
 196     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 197     return retval;
 198 }
 199 
 200 static void switchbuffers(struct pi_local *lp)
     /*  */
 201 {
 202     if (lp->rcvbuf == lp->rxdmabuf1)
 203         lp->rcvbuf = lp->rxdmabuf2;
 204     else
 205         lp->rcvbuf = lp->rxdmabuf1;
 206 }
 207 
 208 static void hardware_send_packet(struct pi_local *lp, struct sk_buff *skb)
     /*  */
 209 {
 210     char kickflag;
 211     unsigned long flags;
 212 
 213     lp->stats.tx_packets++;
 214 
 215     save_flags(flags);
 216     cli();
 217     kickflag = (skb_peek(&lp->sndq) == NULL) && (lp->sndbuf == NULL);
 218     restore_flags(flags);
 219 
 220     skb_queue_tail(&lp->sndq, skb);
 221     if (kickflag) {
 222         /* simulate interrupt to xmit */
 223         switch (lp->base & 2) {
 224         case 2:
 225             a_txint(lp);        /* process interrupt */
 226             break;
 227         case 0:
 228             save_flags(flags);
 229             cli();
 230             if (lp->tstate == IDLE)
 231                 b_txint(lp);
 232             restore_flags(flags);
 233             break;
 234         }
 235     }
 236 }
 237 
 238 static void setup_rx_dma(struct pi_local *lp)
     /*  */
 239 {
 240     unsigned long flags;
 241     int cmd;
 242     unsigned long dma_abs;
 243     unsigned dmachan;
 244 
 245     save_flags(flags);
 246     cli();
 247 
 248     dma_abs = (unsigned long) (lp->rcvbuf->data);
 249     dmachan = lp->dmachan;
 250     cmd = lp->base + CTL;
 251 
 252     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 253         panic("PI: RX buffer violates DMA boundary!");
 254 
 255     /* Get ready for RX DMA */
 256     wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 257 
 258     disable_dma(dmachan);
 259     clear_dma_ff(dmachan);
 260 
 261     /* Set DMA mode register to single transfers, incrementing address,
 262      *  auto init, writes
 263      */
 264     set_dma_mode(dmachan, DMA_MODE_READ | 0x10);
 265     set_dma_addr(dmachan, dma_abs);
 266     set_dma_count(dmachan, lp->bufsiz);
 267     enable_dma(dmachan);
 268 
 269     /* If a packet is already coming in, this line is supposed to
 270            avoid receiving a partial packet.
 271      */
 272     wrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
 273 
 274     /* Enable RX dma */
 275     wrtscc(lp->cardbase, cmd, R1,
 276       WT_RDY_ENAB | WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 277 
 278     restore_flags(flags);
 279 }
 280 
 281 static void setup_tx_dma(struct pi_local *lp, int length)
     /*  */
 282 {
 283     unsigned long dma_abs;
 284     unsigned long flags;
 285     unsigned long dmachan;
 286 
 287     save_flags(flags);
 288     cli();
 289 
 290     dmachan = lp->dmachan;
 291     dma_abs = (unsigned long) (lp->txdmabuf);
 292 
 293     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 294         panic("PI: TX buffer violates DMA boundary!");
 295 
 296     disable_dma(dmachan);
 297     /* Set DMA mode register to single transfers, incrementing address,
 298      *  no auto init, reads
 299      */
 300     set_dma_mode(dmachan, DMA_MODE_WRITE);
 301     clear_dma_ff(dmachan);
 302     set_dma_addr(dmachan, dma_abs);
 303     /* output byte count */
 304     set_dma_count(dmachan, length);
 305 
 306     restore_flags(flags);
 307 }
 308 
 309 static void tdelay(struct pi_local *lp, int time)
     /*  */
 310 {
 311     int port;
 312     unsigned int t1;
 313     unsigned char sc;
 314 
 315     if (lp->base & 2) {         /* If A channel */
 316         sc = SC1;
 317         t1 = time;
 318         port = lp->cardbase + TMR1;
 319     } else {
 320         sc = SC2;
 321         t1 = 10 * time;         /* 10s of milliseconds for the B channel */
 322         port = lp->cardbase + TMR2;
 323         wrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
 324     }
 325 
 326     /* Setup timer sc */
 327     outb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
 328 
 329     /* times 2 to make millisecs */
 330     outb_p((t1 << 1) & 0xFF, port);
 331     outb_p((t1 >> 7) & 0xFF, port);
 332 
 333     /* Enable correct int for timeout */
 334     wrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
 335     wrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
 336 }
 337 
 338 static void free_p(struct sk_buff *skb)
     /*  */
 339 {
 340         dev_kfree_skb(skb, FREE_WRITE);
 341 }
 342 
 343 static void a_txint(struct pi_local *lp)
     /*  */
 344 {
 345     int cmd;
 346     unsigned long flags;
 347 
 348     save_flags(flags);
 349     cli();
 350 
 351     cmd = CTL + lp->base;
 352 
 353     switch (lp->tstate) {
 354     case IDLE:
 355         /* Transmitter idle. Find a frame for transmission */
 356         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 357             rts(lp, OFF);
 358             restore_flags(flags);
 359             return;
 360         }
 361         /* If a buffer to send, we drop thru here */
 362     case DEFER:
 363         /* we may have deferred prev xmit attempt */
 364         /* Check DCD - debounce it
 365          * See Intel Microcommunications Handbook, p2-308
 366          */
 367         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 368         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 369         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 370             lp->tstate = DEFER;
 371             tdelay(lp, 100);
 372             /* defer until DCD transition or timeout */
 373             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 374             restore_flags(flags);
 375             return;
 376         }
 377         if (random() > lp->persist) {
 378             lp->tstate = DEFER;
 379             tdelay(lp, lp->slotime);
 380             restore_flags(flags);
 381             return;
 382         }
 383         /* Assert RTS early minimize collision window */
 384         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 385         rts(lp, ON);            /* Transmitter on */
 386         lp->tstate = ST_TXDELAY;
 387         tdelay(lp, lp->txdelay);
 388         restore_flags(flags);
 389         return;
 390     default:
 391         break;
 392     }                           /* end switch(lp->state) */
 393 
 394     restore_flags(flags);
 395 }                               /*a_txint */
 396 
 397 static void a_exint(struct pi_local *lp)
     /*  */
 398 {
 399     unsigned long flags;
 400     int cmd;
 401     char st;
 402     int length;
 403 
 404     save_flags(flags);
 405     cli();                      /* disable interrupts */
 406 
 407     st = rdscc(lp->cardbase, lp->base + CTL, R0);       /* Fetch status */
 408 
 409     /* reset external status latch */
 410     wrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
 411     cmd = lp->base + CTL;
 412 
 413     if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT)) {
 414         setup_rx_dma(lp);
 415         lp->rstate = ACTIVE;
 416     }
 417     switch (lp->tstate) {
 418     case ACTIVE:
 419         free_p(lp->sndbuf);
 420         lp->sndbuf = NULL;
 421         lp->tstate = FLAGOUT;
 422         tdelay(lp, lp->squeldelay);
 423         break;
 424     case FLAGOUT:
 425         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 426             /* Nothing to send - return to receive mode */
 427             lp->tstate = IDLE;
 428             rts(lp, OFF);
 429             restore_flags(flags);
 430             return;
 431         }
 432         /* NOTE - fall through if more to send */
 433     case ST_TXDELAY:
 434         /* Disable DMA chan */
 435         disable_dma(lp->dmachan);
 436 
 437         /* Set up for TX dma */
 438         wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
 439 
 440 
 441         /* Get all chars */
 442         /* Strip KISS control byte */
 443         length = lp->sndbuf->len - 1;
 444         memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
 445 
 446 
 447         /* Setup DMA controller for tx */
 448         setup_tx_dma(lp, length);
 449 
 450         /* select transmit interrupts to enable */
 451         /* Allow DMA on chan */
 452         enable_dma(lp->dmachan);
 453 
 454         /* reset CRC, Txint pend*/
 455         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
 456 
 457         /* allow Underrun int only */
 458         wrtscc(lp->cardbase, cmd, R15, TxUIE);
 459 
 460         /* Enable TX DMA */
 461         wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
 462 
 463         /* Send CRC on underrun */
 464         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
 465 
 466 
 467         /* packet going out now */
 468         lp->tstate = ACTIVE;
 469         break;
 470     case DEFER:
 471         /* we have deferred prev xmit attempt
 472          * See Intel Microcommunications Handbook, p2-308
 473          */
 474         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 475         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 476         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 477             lp->tstate = DEFER;
 478             tdelay(lp, 100);
 479             /* Defer until dcd transition or 100mS timeout */
 480             wrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
 481             restore_flags(flags);
 482             return;
 483         }
 484         if (random() > lp->persist) {
 485             lp->tstate = DEFER;
 486             tdelay(lp, lp->slotime);
 487             restore_flags(flags);
 488             return;
 489         }
 490         /* Assert RTS early minimize collision window */
 491         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 492         rts(lp, ON);            /* Transmitter on */
 493         lp->tstate = ST_TXDELAY;
 494         tdelay(lp, lp->txdelay);
 495         restore_flags(flags);
 496         return;
 497     }                           /* switch(lp->tstate) */
 498 
 499     restore_flags(flags);
 500 }                               /* a_exint() */
 501 
 502 /* Receive interrupt handler for the A channel
 503  */
 504 static void a_rxint(struct device *dev, struct pi_local *lp)
     /*  */
 505 {
 506     unsigned long flags;
 507     int cmd;
 508     int bytecount;
 509     char rse;
 510     struct sk_buff *skb;
 511     int sksize, pkt_len;
 512     struct mbuf *cur_buf;
 513     unsigned char *cfix;
 514 
 515     save_flags(flags);
 516     cli();                      /* disable interrupts */
 517     cmd = lp->base + CTL;
 518 
 519     rse = rdscc(lp->cardbase, cmd, R1); /* Get special condition bits from R1 */
 520     if (rse & Rx_OVR)
 521         lp->rstate = RXERROR;
 522 
 523     if (rse & END_FR) {
 524         /* If end of frame */
 525         /* figure length of frame from 8237 */
 526         clear_dma_ff(lp->dmachan);
 527         bytecount = lp->bufsiz - get_dma_residue(lp->dmachan);
 528 
 529         if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (bytecount < 10)) {
 530             if ((bytecount >= 10) && (rse & CRC_ERR)) {
 531                 lp->stats.rx_crc_errors++;
 532             }
 533             if (lp->rstate == RXERROR) {
 534                 lp->stats.rx_errors++;
 535                 lp->stats.rx_over_errors++;
 536             }
 537             /* Reset buffer pointers */
 538             lp->rstate = ACTIVE;
 539             setup_rx_dma(lp);
 540         } else {
 541             /* Here we have a valid frame */
 542             /* Toss 2 crc bytes , add one for KISS */
 543             pkt_len = lp->rcvbuf->cnt = bytecount - 2 + 1;
 544 
 545             /* Get buffer for next frame */
 546             cur_buf = lp->rcvbuf;
 547             switchbuffers(lp);
 548             setup_rx_dma(lp);
 549 
 550 
 551             /* Malloc up new buffer. */
 552             sksize = pkt_len;
 553 
 554             skb = dev_alloc_skb(sksize);
 555             if (skb == NULL) {
 556                 printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 557                 lp->stats.rx_dropped++;
 558                 restore_flags(flags);
 559                 return;
 560             }
 561             skb->dev = dev;
 562 
 563             /* KISS kludge -  prefix with a 0 byte */
 564             cfix=skb_put(skb,pkt_len);
 565             *cfix++=0;
 566             /* 'skb->data' points to the start of sk_buff data area. */
 567             memcpy(cfix, (char *) cur_buf->data,
 568                    pkt_len - 1);
 569             skb->protocol=htons(ETH_P_AX25);
 570             skb->mac.raw=skb->data;
 571             IS_SKB(skb);
 572             netif_rx(skb);
 573             lp->stats.rx_packets++;
 574         }                       /* end good frame */
 575     }                           /* end EOF check */
 576     wrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);  /* error reset */
 577     restore_flags(flags);
 578 }
 579 
 580 static void b_rxint(struct device *dev, struct pi_local *lp)
     /*  */
 581 {
 582     unsigned long flags;
 583     int cmd;
 584     char rse;
 585     struct sk_buff *skb;
 586     int sksize;
 587     int pkt_len;
 588     unsigned char *cfix;
 589 
 590     save_flags(flags);
 591     cli();                      /* disable interrupts */
 592     cmd = CTL + lp->base;
 593 
 594     rse = rdscc(lp->cardbase, cmd, R1); /* get status byte from R1 */
 595 
 596     if ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
 597         /* there is a char to be stored
 598          * read special condition bits before reading the data char
 599          */
 600         if (rse & Rx_OVR) {
 601             /* Rx overrun - toss buffer */
 602             /* reset buffer pointers */
 603             lp->rcp = lp->rcvbuf->data;
 604             lp->rcvbuf->cnt = 0;
 605 
 606             lp->rstate = RXERROR;       /* set error flag */
 607             lp->stats.rx_errors++;
 608             lp->stats.rx_over_errors++;
 609         } else if (lp->rcvbuf->cnt >= lp->bufsiz) {
 610             /* Too large -- toss buffer */
 611             /* reset buffer pointers */
 612             lp->rcp = lp->rcvbuf->data;
 613             lp->rcvbuf->cnt = 0;
 614             lp->rstate = TOOBIG;/* when set, chars are not stored */
 615         }
 616         /* ok, we can store the received character now */
 617         if (lp->rstate == ACTIVE) {     /* If no errors... */
 618             *lp->rcp++ = rdscc(lp->cardbase, cmd, R8);  /* char to rcv buff */
 619             lp->rcvbuf->cnt++;  /* bump count */
 620         } else {
 621             /* got to empty FIFO */
 622             (void) rdscc(lp->cardbase, cmd, R8);
 623             wrtscc(lp->cardbase, cmd, R0, ERR_RES);     /* reset err latch */
 624             lp->rstate = ACTIVE;
 625         }
 626     }
 627     if (rse & END_FR) {
 628         /* END OF FRAME -- Make sure Rx was active */
 629         if (lp->rcvbuf->cnt > 0) {
 630             if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (lp->rcvbuf->cnt < 10)) {
 631                 if ((lp->rcvbuf->cnt >= 10) && (rse & CRC_ERR)) {
 632                     lp->stats.rx_crc_errors++;
 633                 }
 634                 lp->rcp = lp->rcvbuf->data;
 635                 lp->rcvbuf->cnt = 0;
 636             } else {
 637                 /* Here we have a valid frame */
 638                 pkt_len = lp->rcvbuf->cnt -= 2; /* Toss 2 crc bytes */
 639                 pkt_len += 1;   /* Make room for KISS control byte */
 640 
 641                 /* Malloc up new buffer. */
 642                 sksize = pkt_len;
 643                 skb = dev_alloc_skb(sksize);
 644                 if (skb == NULL) {
 645                     printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 646                     lp->stats.rx_dropped++;
 647                     restore_flags(flags);
 648                     return;
 649                 }
 650                 skb->dev = dev;
 651 
 652                 /* KISS kludge -  prefix with a 0 byte */
 653                 cfix=skb_put(skb,pkt_len);
 654                 *cfix++=0;
 655                 /* 'skb->data' points to the start of sk_buff data area. */
 656                 memcpy(cfix, lp->rcvbuf->data, pkt_len - 1);
 657                 skb->protocol=ntohs(ETH_P_AX25);
 658                 skb->mac.raw=skb->data;
 659                 IS_SKB(skb);
 660                 netif_rx(skb);
 661                 lp->stats.rx_packets++;
 662                 /* packet queued - initialize buffer for next frame */
 663                 lp->rcp = lp->rcvbuf->data;
 664                 lp->rcvbuf->cnt = 0;
 665 
 666             }                   /* end good frame queued */
 667         }                       /* end check for active receive upon EOF */
 668         lp->rstate = ACTIVE;    /* and clear error status */
 669     }                           /* end EOF check */
 670     restore_flags(flags);
 671 }
 672 
 673 
 674 static void b_txint(struct pi_local *lp)
     /*  */
 675 {
 676     unsigned long flags;
 677     int cmd;
 678     unsigned char c;
 679 
 680     save_flags(flags);
 681     cli();
 682     cmd = CTL + lp->base;
 683 
 684     switch (lp->tstate) {
 685     case CRCOUT:
 686         lp->tstate = FLAGOUT;
 687         tdelay(lp, lp->squeldelay);
 688         restore_flags(flags);
 689         return;
 690     case IDLE:
 691         /* Transmitter idle. Find a frame for transmission */
 692         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 693             /* Nothing to send - return to receive mode
 694              * Tx OFF now - flag should have gone
 695              */
 696             rts(lp, OFF);
 697          
 698             restore_flags(flags);
 699             return;
 700         }
 701         lp->txptr = lp->sndbuf->data;
 702         lp->txptr++;            /* Ignore KISS control byte */
 703         lp->txcnt = (int) lp->sndbuf->len - 1;
 704         /* If a buffer to send, we drop thru here */
 705     case DEFER:         /* we may have deferred prev xmit attempt */
 706         /* Check DCD - debounce it */
 707         /* See Intel Microcommunications Handbook, p2-308 */
 708         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 709         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 710         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 711             lp->tstate = DEFER;
 712             tdelay(lp, 100);
 713             /* defer until DCD transition or timeout */
 714             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 715             restore_flags(flags);
 716             return;
 717         }
 718         if (random() > lp->persist) {
 719             lp->tstate = DEFER;
 720             tdelay(lp, lp->slotime);
 721             restore_flags(flags);
 722             return;
 723         }
 724         rts(lp, ON);            /* Transmitter on */
 725         lp->tstate = ST_TXDELAY;
 726         tdelay(lp, lp->txdelay);
 727         restore_flags(flags);
 728         return;
 729 
 730     case ACTIVE:
 731         /* Here we are actively sending a frame */
 732         if (lp->txcnt--) {
 733             c = *lp->txptr++;
 734             /* next char is gone */
 735             wrtscc(lp->cardbase, cmd, R8, c);
 736             /* stuffing a char satisfies Interrupt condition */
 737         } else {
 738             /* No more to send */
 739             free_p(lp->sndbuf);
 740             lp->sndbuf = NULL;
 741             if ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
 742                 /* Did we underrun? */
 743                 /* unexpected underrun */
 744                 lp->stats.tx_errors++;
 745                 lp->stats.tx_fifo_errors++;
 746                 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 747                 lp->tstate = FLAGOUT;
 748                 tdelay(lp, lp->squeldelay);
 749                 restore_flags(flags);
 750                 return;
 751             }
 752             lp->tstate = UNDERRUN;      /* Now we expect to underrun */
 753             /* Send flags on underrun */
 754             if (lp->speed) {    /* If internally clocked */
 755                 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
 756             } else {
 757                 wrtscc(lp->cardbase, cmd, R10, CRCPS);
 758             }
 759             wrtscc(lp->cardbase, cmd, R0, RES_Tx_P);    /* reset Tx Int Pend */
 760         }
 761         restore_flags(flags);
 762         return;                 /* back to wait for interrupt */
 763     }                           /* end switch */
 764     restore_flags(flags);
 765 }
 766 
 767 /* Pi SIO External/Status interrupts (for the B channel)
 768  * This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
 769  * Receiver automatically goes to Hunt on an abort.
 770  *
 771  * If the Tx Underrun interrupt hits, change state and
 772  * issue a reset command for it, and return.
 773  */
 774 static void b_exint(struct pi_local *lp)
     /*  */
 775 {
 776     unsigned long flags;
 777     char st;
 778     int cmd;
 779     char c;
 780 
 781     cmd = CTL + lp->base;
 782     save_flags(flags);
 783     cli();                      /* disable interrupts */
 784     st = rdscc(lp->cardbase, cmd, R0);  /* Fetch status */
 785     /* reset external status latch */
 786     wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 787 
 788 
 789     switch (lp->tstate) {
 790     case ACTIVE:                /* Unexpected underrun */
 791         free_p(lp->sndbuf);
 792         lp->sndbuf = NULL;
 793         wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 794         lp->tstate = FLAGOUT;
 795         lp->stats.tx_errors++;
 796         lp->stats.tx_fifo_errors++;
 797         tdelay(lp, lp->squeldelay);
 798         restore_flags(flags);
 799         return;
 800     case UNDERRUN:
 801         lp->tstate = CRCOUT;
 802         restore_flags(flags);
 803         return;
 804     case FLAGOUT:
 805         /* Find a frame for transmission */
 806         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 807             /* Nothing to send - return to receive mode
 808              * Tx OFF now - flag should have gone
 809              */
 810             rts(lp, OFF);
 811             lp->tstate = IDLE;
 812             restore_flags(flags);
 813             return;
 814         }
 815         lp->txptr = lp->sndbuf->data;
 816         lp->txptr++;            /* Ignore KISS control byte */
 817         lp->txcnt = (int) lp->sndbuf->len - 1;
 818         /* Get first char to send */
 819         lp->txcnt--;
 820         c = *lp->txptr++;
 821         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 822 
 823         /* Send abort on underrun */
 824         if (lp->speed) {        /* If internally clocked */
 825             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 826         } else {
 827             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 828         }
 829 
 830         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 831         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 832 
 833 #ifdef STUFF2
 834         /* stuff an extra one if we can */
 835         if (lp->txcnt) {
 836             lp->txcnt--;
 837             c = *lp->txptr++;
 838             /* Wait for tx buffer empty */
 839             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 840                 ;   
 841             wrtscc(lp->cardbase, cmd, R8, c);
 842         }
 843 #endif
 844 
 845         /* select transmit interrupts to enable */
 846 
 847         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 848         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 849         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);       /* Tx/Ext ints */
 850 
 851         lp->tstate = ACTIVE;    /* char going out now */
 852         restore_flags(flags);
 853         return;
 854 
 855     case DEFER:
 856         /* Check DCD - debounce it
 857          * See Intel Microcommunications Handbook, p2-308
 858          */
 859         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 860         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 861         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 862             lp->tstate = DEFER;
 863             tdelay(lp, 100);
 864             /* defer until DCD transition or timeout */
 865             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 866             restore_flags(flags);
 867             return;
 868         }
 869         if (random() > lp->persist) {
 870             lp->tstate = DEFER;
 871             tdelay(lp, lp->slotime);
 872             restore_flags(flags);
 873             return;
 874         }
 875         rts(lp, ON);            /* Transmitter on */
 876         lp->tstate = ST_TXDELAY;
 877         tdelay(lp, lp->txdelay);
 878         restore_flags(flags);
 879         return;
 880 
 881     case ST_TXDELAY:
 882 
 883         /* Get first char to send */
 884         lp->txcnt--;
 885         c = *lp->txptr++;
 886         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 887 
 888         /* Send abort on underrun */
 889         if (lp->speed) {        /* If internally clocked */
 890             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 891         } else {
 892             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 893         }
 894 
 895         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 896         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 897 
 898 #ifdef STUFF2
 899         /* stuff an extra one if we can */
 900         if (lp->txcnt) {
 901             lp->txcnt--;
 902             c = *lp->txptr++;
 903             /* Wait for tx buffer empty */
 904             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 905                 ;   
 906             wrtscc(lp->cardbase, cmd, R8, c);
 907         }
 908 #endif
 909 
 910         /* select transmit interrupts to enable */
 911 
 912         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 913         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 914         /* Tx/Extern ints on */
 915         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
 916 
 917         lp->tstate = ACTIVE;    /* char going out now */
 918         restore_flags(flags);
 919         return;
 920     }
 921 
 922     /* Receive Mode only
 923      * This triggers when hunt mode is entered, & since an ABORT
 924      * automatically enters hunt mode, we use that to clean up
 925      * any waiting garbage
 926      */
 927     if ((lp->rstate == ACTIVE) && (st & BRK_ABRT)) {
 928         (void) rdscc(lp->cardbase, cmd, R8);
 929         (void) rdscc(lp->cardbase, cmd, R8);
 930         (void) rdscc(lp->cardbase, cmd, R8);
 931         lp->rcp = lp->rcvbuf->data;
 932         lp->rcvbuf->cnt = 0;    /* rewind on DCD transition */
 933     }
 934     restore_flags(flags);
 935 }
 936 
 937 /* Probe for a PI card. */
 938 /* This routine also initializes the timer chip */
 939 
 940 static int hw_probe(int ioaddr)
     /*  */
 941 {
 942     int time = 1000;            /* Number of milliseconds for test */
 943     unsigned long start_time, end_time;
 944 
 945     int base, tmr0, tmr1, tmrcmd;
 946     int a = 1;
 947     int b = 1;
 948 
 949     base = ioaddr & 0x3f0;
 950     tmr0 = TMR0 + base;
 951     tmr1 = TMR1 + base;
 952     tmrcmd = TMRCMD + base;
 953 
 954     /* Set up counter chip timer 0 for 500 uS period square wave */
 955     /* assuming a 3.68 mhz clock for now */
 956     outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 957     outb_p(922 & 0xFF, tmr0);
 958     outb_p(922 >> 8, tmr0);
 959 
 960     /* Setup timer control word for timer 1*/
 961     outb_p(SC1 | LSB_MSB | MODE0, tmrcmd);
 962     outb_p((time << 1) & 0xFF, tmr1);
 963     outb_p((time >> 7) & 0XFF, tmr1);
 964 
 965     /* wait until counter reg is loaded */
 966     do {
 967         /* Latch count for reading */
 968         outb_p(SC1, tmrcmd);
 969         a = inb_p(tmr1);
 970         b = inb_p(tmr1);
 971     } while (b == 0);
 972     start_time = jiffies;
 973     while (b != 0) {
 974         /* Latch count for reading */
 975         outb_p(SC1, tmrcmd);
 976         a = inb_p(tmr1);
 977         b = inb_p(tmr1);
 978         end_time = jiffies;
 979         /* Don't wait forever - there may be no card here */
 980         if ((end_time - start_time) > 200)
 981             return 0;           /* No card found */
 982     }
 983     end_time = jiffies;
 984     /* 87 jiffies, for a 3.68 mhz clock, half that for a double speed clock */
 985     if ((end_time - start_time) > 65) {
 986         return (1);             /* PI card found */
 987     } else {
 988         /* Faster crystal - tmr0 needs adjusting */
 989         /* Set up counter chip */
 990         /* 500 uS square wave */
 991         outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 992         outb_p(1844 & 0xFF, tmr0);
 993         outb_p(1844 >> 8, tmr0);
 994         return (2);             /* PI2 card found */
 995     }
 996 }
 997 
 998 static void rts(struct pi_local *lp, int x)
     /*  */
 999 {
1000     int tc;
1001     long br;
1002     int cmd;
1003     int dummy;
1004 
1005     /* assumes interrupts are off */
1006     cmd = CTL + lp->base;
1007 
1008     /* Reprogram BRG and turn on transmitter to send flags */
1009     if (x == ON) {              /* Turn Tx ON and Receive OFF */
1010         /* Exints off first to avoid abort int */
1011         wrtscc(lp->cardbase, cmd, R15, 0);
1012         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Rx off */
1013         lp->rstate = IDLE;
1014         if (cmd & 2) {          /* if channel a */
1015             /* Set up for TX dma */
1016             wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
1017         } else {
1018             wrtscc(lp->cardbase, cmd, R1, 0);   /* No interrupts */
1019         }
1020 
1021         if (!lp->clockmode) {
1022             if (lp->speed) {    /* if internally clocked */
1023                 br = lp->speed; /* get desired speed */
1024                 tc = (lp->xtal / br) - 2;       /* calc 1X BRG divisor */
1025                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1026                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1027             }
1028         }
1029         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
1030         /* Transmitter now on */
1031     } else {                    /* Tx OFF and Rx ON */
1032         lp->tstate = IDLE;
1033         wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);       /*  TX off */
1034 
1035         if (!lp->clockmode) {
1036             if (lp->speed) {    /* if internally clocked */
1037                 /* Reprogram BRG for 32x clock for receive DPLL */
1038                 /* BRG off, keep Pclk source */
1039                 wrtscc(lp->cardbase, cmd, R14, BRSRC);
1040                 br = lp->speed; /* get desired speed */
1041                 /* calc 32X BRG divisor */
1042                 tc = ((lp->xtal / 32) / br) - 2;
1043                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1044                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1045                 /* SEARCH mode, BRG source */
1046                 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
1047                 /* Enable the BRG */
1048                 wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
1049             }
1050         }
1051         /* Flush rx fifo */
1052         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Make sure rx is off */
1053         wrtscc(lp->cardbase, cmd, R0, ERR_RES); /* reset err latch */
1054         dummy = rdscc(lp->cardbase, cmd, R1);   /* get status byte from R1 */
1055         (void) rdscc(lp->cardbase, cmd, R8);
1056         (void) rdscc(lp->cardbase, cmd, R8);
1057 
1058         (void) rdscc(lp->cardbase, cmd, R8);
1059 
1060         /* Now, turn on the receiver and hunt for a flag */
1061         wrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
1062         lp->rstate = ACTIVE;    /* Normal state */
1063 
1064         if (cmd & 2) {          /* if channel a */
1065             setup_rx_dma(lp);
1066         } else {
1067             /* reset buffer pointers */
1068             lp->rcp = lp->rcvbuf->data;
1069             lp->rcvbuf->cnt = 0;
1070             wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1071         }
1072         wrtscc(lp->cardbase, cmd, R15, BRKIE);  /* allow ABORT int */
1073     }
1074 }
1075 
1076 /* Fill in the MAC-level header. */
1077 static int pi_header(struct sk_buff *skb, struct device *dev, unsigned short type,
     /*  */
1078              void *daddr, void *saddr, unsigned len)
1079 {
1080     return ax25_encapsulate(skb, dev, type, daddr, saddr, len);
1081 }
1082 
1083 /* Rebuild the MAC-level header. */
1084 static int pi_rebuild_header(void *buff, struct device *dev, unsigned long raddr,
     /*  */
1085                              struct sk_buff *skb)
1086 {
1087     return ax25_rebuild_header(buff, dev, raddr, skb);
1088 }
1089 
1090 static void scc_init(struct device *dev)
     /*  */
1091 {
1092     unsigned long flags;
1093     struct pi_local *lp = (struct pi_local *) dev->priv;
1094 
1095     int tc;
1096     long br;
1097     register int cmd;
1098 
1099     /* Initialize 8530 channel for SDLC operation */
1100 
1101     cmd = CTL + lp->base;
1102     save_flags(flags);
1103     cli();
1104 
1105     switch (cmd & CHANA) {
1106     case CHANA:
1107         wrtscc(lp->cardbase, cmd, R9, CHRA);    /* Reset channel A */
1108         wrtscc(lp->cardbase, cmd, R2, 0xff);    /* Initialize interrupt vector */
1109         break;
1110     default:
1111         wrtscc(lp->cardbase, cmd, R9, CHRB);    /* Reset channel B */
1112         break;
1113     }
1114 
1115     /* Deselect all Rx and Tx interrupts */
1116     wrtscc(lp->cardbase, cmd, R1, 0);
1117 
1118     /* Turn off external interrupts (like CTS/CD) */
1119     wrtscc(lp->cardbase, cmd, R15, 0);
1120 
1121     /* X1 clock, SDLC mode */
1122     wrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
1123 
1124     /* Tx/Rx parameters */
1125     if (lp->speed) {            /* Use internal clocking */
1126         wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
1127         if (!lp->clockmode)
1128             /* Tx Clk from BRG. Rcv Clk from DPLL, TRxC pin outputs DPLL */
1129             wrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
1130         else
1131             /* Tx Clk from DPLL, Rcv Clk from DPLL, TRxC Outputs BRG */
1132             wrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
1133     } else {                    /* Use external clocking */
1134         wrtscc(lp->cardbase, cmd, R10, CRCPS);
1135         /* Tx Clk from Trxcl. Rcv Clk from Rtxcl, TRxC pin is input */
1136         wrtscc(lp->cardbase, cmd, R11, TCTRxCP);
1137     }
1138 
1139     /* Null out SDLC start address */
1140     wrtscc(lp->cardbase, cmd, R6, 0);
1141 
1142     /* SDLC flag */
1143     wrtscc(lp->cardbase, cmd, R7, FLAG);
1144 
1145     /* Set up the Transmitter but don't enable it
1146      *  DTR, 8 bit TX chars only
1147      */
1148     wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
1149 
1150     /* Receiver initial setup */
1151     wrtscc(lp->cardbase, cmd, R3, Rx8); /* 8 bits/char */
1152 
1153     /* Setting up BRG now - turn it off first */
1154     wrtscc(lp->cardbase, cmd, R14, BRSRC);      /* BRG off, keep Pclk source */
1155 
1156     /* set the 32x time constant for the BRG in Receive mode */
1157 
1158     if (lp->speed) {
1159         br = lp->speed;         /* get desired speed */
1160         tc = ((lp->xtal / 32) / br) - 2;        /* calc 32X BRG divisor */
1161     } else {
1162         tc = 14;
1163     }
1164 
1165     wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
1166     wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);   /* upper byte */
1167 
1168     /* Following subroutine sets up and ENABLES the receiver */
1169     rts(lp, OFF);               /* TX OFF and RX ON */
1170 
1171     if (lp->speed) {
1172         /* DPLL frm BRG, BRG src PCLK */
1173         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
1174     } else {
1175         /* DPLL frm rtxc,BRG src PCLK */
1176         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
1177     }
1178     wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);     /* SEARCH mode, keep BRG src */
1179     wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);    /* Enable the BRG */
1180 
1181     if (!(cmd & 2))             /* if channel b */
1182         wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1183 
1184     wrtscc(lp->cardbase, cmd, R15, BRKIE);      /* ABORT int */
1185 
1186     /* Now, turn on the receiver and hunt for a flag */
1187     wrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
1188 
1189     restore_flags(flags);
1190 }
1191 
1192 static void chipset_init(struct device *dev)
     /*  */
1193 {
1194     int cardbase;
1195     unsigned long flags;
1196 
1197     cardbase = dev->base_addr & 0x3f0;
1198 
1199     save_flags(flags);
1200     cli();
1201     wrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES); /* Hardware reset */
1202     /* Disable interrupts with master interrupt ctrl reg */
1203     wrtscc(cardbase, dev->base_addr + CTL, R9, 0);
1204     restore_flags(flags);
1205 
1206 }
1207 
1208 
1209 int pi_init(void)
     /*  */
1210 {
1211     int *port;
1212     int ioaddr = 0;
1213     int card_type = 0;
1214     int ports[] =
1215     {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1216 
1217     printk(version);
1218 
1219     /* Only one card supported for now */
1220     for (port = &ports[0]; *port && !card_type; port++) {
1221         ioaddr = *port;
1222 
1223         if (check_region(ioaddr, PI_TOTAL_SIZE) == 0) {
1224             printk("PI: Probing for card at address %#3x\n",ioaddr);
1225             card_type = hw_probe(ioaddr);
1226         }
1227     }
1228 
1229     switch (card_type) {
1230     case 1:
1231         printk("PI: Found a PI card at address %#3x\n", ioaddr);
1232         break;
1233     case 2:
1234         printk("PI: Found a PI2 card at address %#3x\n", ioaddr);
1235         break;
1236     default:
1237         printk("PI: ERROR: No card found\n");
1238         return -EIO;
1239     }
1240 
1241     /* Link a couple of device structures into the chain */
1242     /* For the A port */
1243     /* Allocate space for 4 buffers even though we only need 3,
1244        because one of them may cross a DMA page boundary and
1245        be rejected by get_dma_buffer().
1246     */
1247     register_netdev(&pi0a);
1248     
1249     pi0a.priv = kmalloc(sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4, GFP_KERNEL | GFP_DMA);
1250                         
1251     pi0a.dma = PI_DMA;
1252     pi0a.base_addr = ioaddr + 2;
1253     pi0a.irq = 0;
1254 
1255     /* And the B port */
1256     register_netdev(&pi0b);
1257     pi0b.base_addr = ioaddr;
1258     pi0b.irq = 0;
1259     pi0b.priv = kmalloc(sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4, GFP_KERNEL | GFP_DMA);
1260 
1261     /* Now initialize them */
1262     pi_probe(&pi0a, card_type);
1263     pi_probe(&pi0b, card_type);
1264 
1265     pi0b.irq = pi0a.irq;        /* IRQ is shared */
1266     
1267     return 0;
1268 }
1269 
1270 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize)
     /*  */
1271 {
1272     if (((addr & 0xffff) + dev_buffsize) <= 0x10000)
1273         return 1;
1274     else
1275         return 0;
1276 }
1277 
1278 static int pi_set_mac_address(struct device *dev, struct sockaddr *sa)
     /*  */
1279 {
1280     memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);  /* addr is an AX.25 shifted ASCII */
1281     return 0;                                           /* mac address */
1282 }
1283 
1284 /* Allocate a buffer which does not cross a DMA page boundary */
1285 static char *
1286 get_dma_buffer(unsigned long *mem_ptr)
     /*  */
1287 {
1288     char *ret;
1289 
1290     ret = (char *)*mem_ptr;
1291 
1292     if(!valid_dma_page(*mem_ptr, DMA_BUFF_SIZE + sizeof(struct mbuf))){
1293         *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1294         ret = (char *)*mem_ptr;
1295     }
1296     *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1297     return (ret);
1298 }
1299 
1300 static int pi_probe(struct device *dev, int card_type)
     /*  */
1301 {
1302     short ioaddr;
1303     struct pi_local *lp;
1304     int i;
1305     unsigned long flags;
1306     unsigned long mem_ptr;
1307 
1308     ioaddr = dev->base_addr;
1309 
1310     /* Initialize the device structure. */
1311     /* Must be done before chipset_init */
1312     /* Make certain the data structures used by the PI2 are aligned. */
1313     dev->priv = (void *) (((int) dev->priv + 7) & ~7);
1314     lp = (struct pi_local *) dev->priv;
1315 
1316     memset(dev->priv, 0, sizeof(struct pi_local));
1317 
1318     /* Allocate some buffers which do not cross DMA page boundaries */
1319     mem_ptr = (unsigned long) dev->priv + sizeof(struct pi_local);
1320     lp->txdmabuf = get_dma_buffer(&mem_ptr);
1321     lp->rxdmabuf1 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1322     lp->rxdmabuf2 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1323 
1324     /* Initialize rx buffer */
1325     lp->rcvbuf = lp->rxdmabuf1;
1326     lp->rcp = lp->rcvbuf->data;
1327     lp->rcvbuf->cnt = 0;
1328 
1329     /* Initialize the transmit queue head structure */
1330     skb_queue_head_init(&lp->sndq);
1331 
1332     /* These need to be initialized before scc_init is called. */
1333     if (card_type == 1)
1334         lp->xtal = (unsigned long) SINGLE / 2;
1335     else
1336         lp->xtal = (unsigned long) DOUBLE / 2;
1337     lp->base = dev->base_addr;
1338     lp->cardbase = dev->base_addr & 0x3f0;
1339     if (dev->base_addr & CHANA) {
1340         lp->speed = DEF_A_SPEED;
1341         /* default channel access Params */
1342         lp->txdelay = DEF_A_TXDELAY;
1343         lp->persist = DEF_A_PERSIST;
1344         lp->slotime = DEF_A_SLOTIME;
1345         lp->squeldelay = DEF_A_SQUELDELAY;
1346         lp->clockmode = DEF_A_CLOCKMODE;
1347 
1348     } else {
1349         lp->speed = DEF_B_SPEED;
1350         /* default channel access Params */
1351         lp->txdelay = DEF_B_TXDELAY;
1352         lp->persist = DEF_B_PERSIST;
1353         lp->slotime = DEF_B_SLOTIME;
1354         lp->squeldelay = DEF_B_SQUELDELAY;
1355         lp->clockmode = DEF_B_CLOCKMODE;
1356     }
1357     lp->bufsiz = DMA_BUFF_SIZE;
1358     lp->tstate = IDLE;
1359 
1360     chipset_init(dev);
1361 
1362     if (dev->base_addr & CHANA) {       /* Do these things only for the A port */
1363         /* Note that a single IRQ services 2 devices (A and B channels) */
1364 
1365         lp->dmachan = dev->dma;
1366         if (lp->dmachan < 1 || lp->dmachan > 3)
1367             printk("PI: DMA channel %d out of range\n", lp->dmachan);
1368 
1369         /* chipset_init() was already called */
1370 
1371         if (dev->irq < 2) {
1372             autoirq_setup(0);
1373             save_flags(flags);
1374             cli();
1375             wrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
1376             /* enable PI card interrupts */
1377             wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1378             restore_flags(flags);
1379             /* request a timer interrupt for 1 mS hence */
1380             tdelay(lp, 1);
1381             /* 20 "jiffies" should be plenty of time... */
1382             dev->irq = autoirq_report(20);
1383             if (!dev->irq) {
1384                 printk(". Failed to detect IRQ line.\n");
1385             }
1386             save_flags(flags);
1387             cli();
1388             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);     /* Hardware reset */
1389             /* Disable interrupts with master interrupt ctrl reg */
1390             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
1391             restore_flags(flags);
1392         }
1393 
1394         printk("PI: Autodetected IRQ %d, assuming DMA %d.\n",
1395                dev->irq, dev->dma);
1396 
1397         /* This board has jumpered interrupts. Snarf the interrupt vector
1398                    now.  There is no point in waiting since no other device can use
1399                    the interrupt, and this marks the 'irqaction' as busy. */
1400         {
1401             int irqval = request_irq(dev->irq, &pi_interrupt,0, "pi2");
1402             if (irqval) {
1403                 printk("PI: unable to get IRQ %d (irqval=%d).\n",
1404                        dev->irq, irqval);
1405                 return EAGAIN;
1406             }
1407         }
1408 
1409         /* Grab the region */
1410         snarf_region(ioaddr & 0x3f0, PI_TOTAL_SIZE);
1411 
1412 
1413     }                           /* Only for A port */
1414     dev->open = pi_open;
1415     dev->stop = pi_close;
1416     dev->do_ioctl = pi_ioctl;
1417     dev->hard_start_xmit = pi_send_packet;
1418     dev->get_stats = pi_get_stats;
1419 
1420     /* Fill in the fields of the device structure */
1421     for (i = 0; i < DEV_NUMBUFFS; i++)
1422         skb_queue_head_init(&dev->buffs[i]);
1423 
1424 
1425     dev->hard_header = pi_header;
1426     dev->rebuild_header = pi_rebuild_header;
1427     dev->set_mac_address = pi_set_mac_address;
1428 
1429     dev->type = ARPHRD_AX25;                    /* AF_AX25 device */
1430     dev->hard_header_len = 73;                  /* We do digipeaters now */
1431     dev->mtu = 1500;                            /* eth_mtu is the default */
1432     dev->addr_len = 7;                          /* sizeof an ax.25 address */
1433     memcpy(dev->broadcast, ax25_bcast, 7);
1434     memcpy(dev->dev_addr, ax25_test, 7);
1435 
1436     /* New-style flags. */
1437     dev->flags = 0;
1438     dev->family = AF_INET;
1439     dev->pa_addr = 0;
1440     dev->pa_brdaddr = 0;
1441     dev->pa_mask = 0;
1442     dev->pa_alen = 4;
1443 
1444     return 0;
1445 }
1446 
1447 /* Open/initialize the board.  This is called (in the current kernel)
1448    sometime after booting when the 'ifconfig' program is run.
1449 
1450    This routine should set everything up anew at each open, even
1451    registers that "should" only need to be set once at boot, so that
1452    there is non-reboot way to recover if something goes wrong.
1453    */
1454 static int pi_open(struct device *dev)
     /*  */
1455 {
1456     unsigned long flags;
1457     static first_time = 1;
1458 
1459     struct pi_local *lp = (struct pi_local *) dev->priv;
1460 
1461     if (dev->base_addr & 2) {   /* if A channel */
1462         if (first_time) {
1463             if (request_dma(dev->dma,"pi2")) {
1464                 free_irq(dev->irq);
1465                 return -EAGAIN;
1466             }
1467             irq2dev_map[dev->irq] = dev;
1468         }
1469         /* Reset the hardware here. */
1470         chipset_init(dev);
1471     }
1472     lp->tstate = IDLE;
1473 
1474     if (dev->base_addr & 2) {   /* if A channel */
1475         scc_init(dev);          /* Called once for each channel */
1476         scc_init(dev->next);
1477     }
1478     /* master interrupt enable */
1479     save_flags(flags);
1480     cli();
1481     wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1482     restore_flags(flags);
1483 
1484     lp->open_time = jiffies;
1485 
1486     dev->tbusy = 0;
1487     dev->interrupt = 0;
1488     dev->start = 1;
1489     first_time = 0;
1490     return 0;
1491 }
1492 
1493 static int pi_send_packet(struct sk_buff *skb, struct device *dev)
     /*  */
1494 {
1495     struct pi_local *lp = (struct pi_local *) dev->priv;
1496 
1497     /* If some higher layer thinks we've missed an tx-done interrupt
1498            we are passed NULL. Caution: dev_tint() handles the cli()/sti()
1499            itself. */
1500     if (skb == NULL) {
1501         dev_tint(dev);
1502         return 0;
1503     }
1504     hardware_send_packet(lp, skb);
1505     dev->trans_start = jiffies;
1506 
1507     return 0;
1508 }
1509 
1510 /* The typical workload of the driver:
1511    Handle the network interface interrupts. */
1512 static void pi_interrupt(int reg_ptr, struct pt_regs *regs)
     /*  */
1513 {
1514 /*    int irq = -(((struct pt_regs *) reg_ptr)->orig_eax + 2);*/
1515     struct pi_local *lp;
1516     int st;
1517     unsigned long flags;
1518 
1519 /*    dev_b = dev_a->next;       Relies on the order defined in Space.c */
1520 
1521 #if 0
1522     if (dev_a == NULL) {
1523         printk("PI: pi_interrupt(): irq %d for unknown device.\n", irq);
1524         return;
1525     }
1526 #endif    
1527     /* Read interrupt status register (only valid from channel A)
1528      * Process all pending interrupts in while loop
1529      */
1530     lp = (struct pi_local *) pi0a.priv; /* Assume channel A */
1531     while ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
1532         if (st & CHBTxIP) {
1533             /* Channel B Transmit Int Pending */
1534             lp = (struct pi_local *) pi0b.priv;
1535             b_txint(lp);
1536         } else if (st & CHARxIP) {
1537             /* Channel A Rcv Interrupt Pending */
1538             lp = (struct pi_local *) pi0a.priv;
1539             a_rxint(&pi0a, lp);
1540         } else if (st & CHATxIP) {
1541             /* Channel A Transmit Int Pending */
1542             lp = (struct pi_local *) pi0a.priv;
1543             a_txint(lp);
1544         } else if (st & CHAEXT) {
1545             /* Channel A External Status Int */
1546             lp = (struct pi_local *) pi0a.priv;
1547             a_exint(lp);
1548         } else if (st & CHBRxIP) {
1549             /* Channel B Rcv Interrupt Pending */
1550             lp = (struct pi_local *) pi0b.priv;
1551             b_rxint(&pi0b, lp);
1552         } else if (st & CHBEXT) {
1553             /* Channel B External Status Int */
1554             lp = (struct pi_local *) pi0b.priv;
1555             b_exint(lp);
1556         }
1557         /* Reset highest interrupt under service */
1558         save_flags(flags);
1559         cli();
1560         wrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
1561         restore_flags(flags);
1562     }                           /* End of while loop on int processing */
1563     return;
1564 }
1565 
1566 /* The inverse routine to pi_open(). */
1567 static int pi_close(struct device *dev)
     /*  */
1568 {
1569     unsigned long flags;
1570     struct pi_local *lp;
1571     struct sk_buff *ptr;
1572 
1573     save_flags(flags);
1574     cli();
1575 
1576     lp = (struct pi_local *) dev->priv;
1577     ptr = NULL;
1578 
1579     chipset_init(dev);          /* reset the scc */
1580     disable_dma(lp->dmachan);
1581 
1582     lp->open_time = 0;
1583 
1584     dev->tbusy = 1;
1585     dev->start = 0;
1586 
1587     /* Free any buffers left in the hardware transmit queue */
1588     while ((ptr = skb_dequeue(&lp->sndq)) != NULL)
1589         free_p(ptr);
1590 
1591     restore_flags(flags);
1592     return 0;
1593 }
1594 
1595 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
     /*  */
1596 {
1597     unsigned long flags;
1598     struct pi_req rq;
1599     struct pi_local *lp = (struct pi_local *) dev->priv;
1600 
1601     int ret = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct pi_req));
1602     if (ret)
1603         return ret;
1604         
1605     if(cmd!=SIOCDEVPRIVATE)
1606         return -EINVAL;
1607 
1608     memcpy_fromfs(&rq, ifr->ifr_data, sizeof(struct pi_req));
1609 
1610     switch (rq.cmd) {
1611     case SIOCSPIPARAM:
1612 
1613         if (!suser())
1614             return -EPERM;
1615         save_flags(flags);
1616         cli();
1617         lp->txdelay = rq.txdelay;
1618         lp->persist = rq.persist;
1619         lp->slotime = rq.slotime;
1620         lp->squeldelay = rq.squeldelay;
1621         lp->clockmode = rq.clockmode;
1622         lp->speed = rq.speed;
1623         pi_open(&pi0a); /* both channels get reset %%% */
1624         restore_flags(flags);
1625         ret = 0;
1626         break;
1627 
1628     case SIOCSPIDMA:
1629 
1630         if (!suser())
1631             return -EPERM;
1632         ret = 0;
1633         if (dev->base_addr & 2) {   /* if A channel */
1634            if (rq.dmachan < 1 || rq.dmachan > 3)
1635                 return -EINVAL;
1636            save_flags(flags);
1637            cli();
1638            pi_close(dev);
1639            free_dma(lp->dmachan);
1640            dev->dma = lp->dmachan = rq.dmachan;
1641            if (request_dma(lp->dmachan,"pi2")) 
1642                 ret = -EAGAIN;
1643            pi_open(dev);
1644            restore_flags(flags);
1645         }
1646         break;
1647 
1648     case SIOCSPIIRQ:
1649         ret = -EINVAL;      /* add this later */
1650         break;
1651 
1652     case SIOCGPIPARAM:
1653     case SIOCGPIDMA:
1654     case SIOCGPIIRQ:
1655 
1656         rq.speed = lp->speed;
1657         rq.txdelay = lp->txdelay;
1658         rq.persist = lp->persist;
1659         rq.slotime = lp->slotime;
1660         rq.squeldelay = lp->squeldelay;
1661         rq.clockmode = lp->clockmode;
1662         rq.dmachan = lp->dmachan;
1663         rq.irq = dev->irq;
1664         memcpy_tofs(ifr->ifr_data, &rq, sizeof(struct pi_req));
1665         ret = 0;
1666         break;
1667 
1668     default:
1669         ret = -EINVAL;
1670     }
1671     return ret;
1672 }
1673 
1674 /* Get the current statistics.  This may be called with the card open or
1675    closed. */
1676 static struct netstats *
1677  pi_get_stats(struct device *dev)
     /*  */
1678 {
1679     struct pi_local *lp = (struct pi_local *) dev->priv;
1680 
1681     return &lp->stats;
1682 }
1683 
1684 
1685 /*
1686  * Local variables:
1687  *  compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1688  *  version-control: t
1689  *  kept-new-versions: 5
1690  *  tab-width: 4
1691  * End:
1692  */
/* */
root/drivers/net/pi2.c

DEFINITIONS
