drivers/sound/ad1848.c

/* */
This source file includes following definitions.
ad_read
ad_write
wait_for_calibration
ad_mute
ad_unmute
ad_enter_MCE
ad_leave_MCE
ad1848_set_recmask
change_bits
ad1848_mixer_get
ad1848_mixer_set
ad1848_mixer_reset
ad1848_mixer_ioctl
ad1848_open
ad1848_close
set_speed
set_channels
set_format
ad1848_ioctl
ad1848_output_block
ad1848_start_input
ad1848_prepare_for_IO
ad1848_reset
ad1848_halt
ad1848_halt_input
ad1848_halt_output
ad1848_trigger
ad1848_detect
ad1848_init
ad1848_unload
ad1848_interrupt
probe_ms_sound
attach_ms_sound
unload_ms_sound
probe_pnp_ad1848
attach_pnp_ad1848
unload_pnp_ad1848
ad1848_tmr_start
ad1848_tmr_reprogram
ad1848_tmr_disable
ad1848_tmr_restart
ad1848_tmr_install
   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  *
  16  * Copyright by Hannu Savolainen 1994, 1995
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: 1. Redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer. 2.
  22  * Redistributions in binary form must reproduce the above copyright notice,
  23  * this list of conditions and the following disclaimer in the documentation
  24  * and/or other materials provided with the distribution.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  27  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  30  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  33  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  * Modified:
  39  *  Riccardo Facchetti  24 Mar 1995
  40  *  - Added the Audio Excel DSP 16 initialization routine.
  41  */
  42 
  43 #define DEB(x)
  44 #define DEB1(x)
  45 #include "sound_config.h"
  46 
  47 #if defined(CONFIGURE_SOUNDCARD) && !defined(EXCLUDE_AD1848)
  48 
  49 #include "ad1848_mixer.h"
  50 
  51 typedef struct
  52   {
  53     int             base;
  54     int             irq;
  55     int             dual_dma;   /* 1, when two DMA channels allocated */
  56     unsigned char   MCE_bit;
  57     unsigned char   saved_regs[16];
  58 
  59     int             speed;
  60     unsigned char   speed_bits;
  61     int             channels;
  62     int             audio_format;
  63     unsigned char   format_bits;
  64 
  65     int             xfer_count;
  66     int             irq_mode;
  67     int             intr_active;
  68     int             opened;
  69     char           *chip_name;
  70     int             mode;
  71 #define MD_1848         1
  72 #define MD_4231         2
  73 #define MD_4231A        3
  74 #define MD_1845         4
  75 
  76     /* Mixer parameters */
  77     int             recmask;
  78     int             supported_devices;
  79     int             supported_rec_devices;
  80     unsigned short  levels[32];
  81     int             dev_no;
  82     volatile unsigned long timer_ticks;
  83     int             timer_running;
  84     int             irq_ok;
  85     sound_os_info  *osp;
  86   }
  87 
  88 ad1848_info;
  89 
  90 static int      nr_ad1848_devs = 0;
  91 static volatile char irq2dev[17] =
  92 {-1, -1, -1, -1, -1, -1, -1, -1,
  93  -1, -1, -1, -1, -1, -1, -1, -1, -1};
  94 
  95 static int      timer_installed = -1;
  96 
  97 static char     mixer2codec[MAX_MIXER_DEV] =
  98 {0};
  99 
 100 static int      ad_format_mask[5 /*devc->mode */ ] =
 101 {
 102   0,
 103   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 104   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 105   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 106   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW      /* AD1845 */
 107 };
 108 
 109 static ad1848_info dev_info[MAX_AUDIO_DEV];
 110 
 111 #define io_Index_Addr(d)        ((d)->base)
 112 #define io_Indexed_Data(d)      ((d)->base+1)
 113 #define io_Status(d)            ((d)->base+2)
 114 #define io_Polled_IO(d)         ((d)->base+3)
 115 
 116 static int      ad1848_open (int dev, int mode);
 117 static void     ad1848_close (int dev);
 118 static int      ad1848_ioctl (int dev, unsigned int cmd, ioctl_arg arg, int local);
 119 static void     ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 120 static void     ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 121 static int      ad1848_prepare_for_IO (int dev, int bsize, int bcount);
 122 static void     ad1848_reset (int dev);
 123 static void     ad1848_halt (int dev);
 124 static void     ad1848_halt_input (int dev);
 125 static void     ad1848_halt_output (int dev);
 126 static void     ad1848_trigger (int dev, int bits);
 127 static int      ad1848_tmr_install (int dev);
 128 static void     ad1848_tmr_reprogram (int dev);
 129 
 130 static int
 131 ad_read (ad1848_info * devc, int reg)
     /*  */
 132 {
 133   unsigned long   flags;
 134   int             x;
 135   int             timeout = 900000;
 136 
 137   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 138     timeout--;
 139 
 140   save_flags (flags);
 141   cli ();
 142   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 143   x = inb (io_Indexed_Data (devc));
 144   /*  printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
 145   restore_flags (flags);
 146 
 147   return x;
 148 }
 149 
 150 static void
 151 ad_write (ad1848_info * devc, int reg, int data)
     /*  */
 152 {
 153   unsigned long   flags;
 154   int             timeout = 90000;
 155 
 156   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 157     timeout--;
 158 
 159   save_flags (flags);
 160   cli ();
 161   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 162   outb ((unsigned char) (data & 0xff), io_Indexed_Data (devc));
 163   /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
 164   restore_flags (flags);
 165 }
 166 
 167 static void
 168 wait_for_calibration (ad1848_info * devc)
     /*  */
 169 {
 170   int             timeout = 0;
 171 
 172   /*
 173      * Wait until the auto calibration process has finished.
 174      *
 175      * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 176      * 2)       Wait until the ACI bit of I11 gets on and then off.
 177    */
 178 
 179   timeout = 100000;
 180   while (timeout > 0 && inb (devc->base) & 0x80)
 181     timeout--;
 182   if (inb (devc->base) & 0x80)
 183     printk ("ad1848: Auto calibration timed out(1).\n");
 184 
 185   timeout = 100;
 186   while (timeout > 0 && !(ad_read (devc, 11) & 0x20))
 187     timeout--;
 188   if (!(ad_read (devc, 11) & 0x20))
 189     return;
 190 
 191   timeout = 20000;
 192   while (timeout > 0 && ad_read (devc, 11) & 0x20)
 193     timeout--;
 194   if (ad_read (devc, 11) & 0x20)
 195     printk ("ad1848: Auto calibration timed out(3).\n");
 196 }
 197 
 198 static void
 199 ad_mute (ad1848_info * devc)
     /*  */
 200 {
 201   int             i;
 202   unsigned char   prev;
 203 
 204   /*
 205      * Save old register settings and mute output channels
 206    */
 207   for (i = 6; i < 8; i++)
 208     {
 209       prev = devc->saved_regs[i] = ad_read (devc, i);
 210       ad_write (devc, i, prev | 0x80);
 211     }
 212 }
 213 
 214 static void
 215 ad_unmute (ad1848_info * devc)
     /*  */
 216 {
 217   int             i;
 218 
 219   /*
 220      * Restore back old volume registers (unmute)
 221    */
 222   for (i = 6; i < 8; i++)
 223     {
 224       ad_write (devc, i, devc->saved_regs[i] & ~0x80);
 225     }
 226 }
 227 
 228 static void
 229 ad_enter_MCE (ad1848_info * devc)
     /*  */
 230 {
 231   unsigned long   flags;
 232   int             timeout = 1000;
 233   unsigned short  prev;
 234 
 235   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 236     timeout--;
 237 
 238   save_flags (flags);
 239   cli ();
 240 
 241   devc->MCE_bit = 0x40;
 242   prev = inb (io_Index_Addr (devc));
 243   if (prev & 0x40)
 244     {
 245       restore_flags (flags);
 246       return;
 247     }
 248 
 249   outb (devc->MCE_bit, io_Index_Addr (devc));
 250   restore_flags (flags);
 251 }
 252 
 253 static void
 254 ad_leave_MCE (ad1848_info * devc)
     /*  */
 255 {
 256   unsigned long   flags;
 257   unsigned char   prev;
 258   int             timeout = 1000;
 259 
 260   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 261     timeout--;
 262 
 263   save_flags (flags);
 264   cli ();
 265 
 266   devc->MCE_bit = 0x00;
 267   prev = inb (io_Index_Addr (devc));
 268   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 269 
 270   if ((prev & 0x40) == 0)       /* Not in MCE mode */
 271     {
 272       restore_flags (flags);
 273       return;
 274     }
 275 
 276   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 277   wait_for_calibration (devc);
 278   restore_flags (flags);
 279 }
 280 
 281 
 282 static int
 283 ad1848_set_recmask (ad1848_info * devc, int mask)
     /*  */
 284 {
 285   unsigned char   recdev;
 286   int             i, n;
 287 
 288   mask &= devc->supported_rec_devices;
 289 
 290   n = 0;
 291   for (i = 0; i < 32; i++)      /* Count selected device bits */
 292     if (mask & (1 << i))
 293       n++;
 294 
 295   if (n == 0)
 296     mask = SOUND_MASK_MIC;
 297   else if (n != 1)              /* Too many devices selected */
 298     {
 299       mask &= ~devc->recmask;   /* Filter out active settings */
 300 
 301       n = 0;
 302       for (i = 0; i < 32; i++)  /* Count selected device bits */
 303         if (mask & (1 << i))
 304           n++;
 305 
 306       if (n != 1)
 307         mask = SOUND_MASK_MIC;
 308     }
 309 
 310   switch (mask)
 311     {
 312     case SOUND_MASK_MIC:
 313       recdev = 2;
 314       break;
 315 
 316     case SOUND_MASK_LINE:
 317     case SOUND_MASK_LINE3:
 318       recdev = 0;
 319       break;
 320 
 321     case SOUND_MASK_CD:
 322     case SOUND_MASK_LINE1:
 323       recdev = 1;
 324       break;
 325 
 326     case SOUND_MASK_IMIX:
 327       recdev = 3;
 328       break;
 329 
 330     default:
 331       mask = SOUND_MASK_MIC;
 332       recdev = 2;
 333     }
 334 
 335   recdev <<= 6;
 336   ad_write (devc, 0, (ad_read (devc, 0) & 0x3f) | recdev);
 337   ad_write (devc, 1, (ad_read (devc, 1) & 0x3f) | recdev);
 338 
 339   devc->recmask = mask;
 340   return mask;
 341 }
 342 
 343 static void
 344 change_bits (unsigned char *regval, int dev, int chn, int newval)
     /*  */
 345 {
 346   unsigned char   mask;
 347   int             shift;
 348 
 349   if (mix_devices[dev][chn].polarity == 1)      /* Reverse */
 350     newval = 100 - newval;
 351 
 352   mask = (1 << mix_devices[dev][chn].nbits) - 1;
 353   shift = mix_devices[dev][chn].bitpos;
 354   newval = (int) ((newval * mask) + 50) / 100;  /* Scale it */
 355 
 356   *regval &= ~(mask << shift);  /* Clear bits */
 357   *regval |= (newval & mask) << shift;  /* Set new value */
 358 }
 359 
 360 static int
 361 ad1848_mixer_get (ad1848_info * devc, int dev)
     /*  */
 362 {
 363   if (!((1 << dev) & devc->supported_devices))
 364     return -EINVAL;
 365 
 366   return devc->levels[dev];
 367 }
 368 
 369 static int
 370 ad1848_mixer_set (ad1848_info * devc, int dev, int value)
     /*  */
 371 {
 372   int             left = value & 0x000000ff;
 373   int             right = (value & 0x0000ff00) >> 8;
 374   int             retvol;
 375 
 376   int             regoffs;
 377   unsigned char   val;
 378 
 379   if (left > 100)
 380     left = 100;
 381   if (right > 100)
 382     right = 100;
 383 
 384   if (mix_devices[dev][RIGHT_CHN].nbits == 0)   /* Mono control */
 385     right = left;
 386 
 387   retvol = left | (left << 8);
 388 
 389   /* Scale volumes */
 390   left = mix_cvt[left];
 391   right = mix_cvt[right];
 392 
 393   /* Scale it again */
 394   left = mix_cvt[left];
 395   right = mix_cvt[right];
 396 
 397   if (dev > 31)
 398     return -EINVAL;
 399 
 400   if (!(devc->supported_devices & (1 << dev)))
 401     return -EINVAL;
 402 
 403   if (mix_devices[dev][LEFT_CHN].nbits == 0)
 404     return -EINVAL;
 405 
 406   devc->levels[dev] = retvol;
 407 
 408   /*
 409      * Set the left channel
 410    */
 411 
 412   regoffs = mix_devices[dev][LEFT_CHN].regno;
 413   val = ad_read (devc, regoffs);
 414   change_bits (&val, dev, LEFT_CHN, left);
 415   ad_write (devc, regoffs, val);
 416   devc->saved_regs[regoffs] = val;
 417 
 418   /*
 419      * Set the right channel
 420    */
 421 
 422   if (mix_devices[dev][RIGHT_CHN].nbits == 0)
 423     return retvol;              /* Was just a mono channel */
 424 
 425   regoffs = mix_devices[dev][RIGHT_CHN].regno;
 426   val = ad_read (devc, regoffs);
 427   change_bits (&val, dev, RIGHT_CHN, right);
 428   ad_write (devc, regoffs, val);
 429   devc->saved_regs[regoffs] = val;
 430 
 431   return retvol;
 432 }
 433 
 434 static void
 435 ad1848_mixer_reset (ad1848_info * devc)
     /*  */
 436 {
 437   int             i;
 438 
 439   devc->recmask = 0;
 440   if (devc->mode != MD_1848)
 441     devc->supported_devices = MODE2_MIXER_DEVICES;
 442   else
 443     devc->supported_devices = MODE1_MIXER_DEVICES;
 444 
 445   devc->supported_rec_devices = MODE1_REC_DEVICES;
 446 
 447   for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 448     if (devc->supported_devices & (1 << i))
 449       ad1848_mixer_set (devc, i, default_mixer_levels[i]);
 450   ad1848_set_recmask (devc, SOUND_MASK_MIC);
 451 }
 452 
 453 static int
 454 ad1848_mixer_ioctl (int dev, unsigned int cmd, ioctl_arg arg)
     /*  */
 455 {
 456   ad1848_info    *devc;
 457 
 458   int             codec_dev = mixer2codec[dev];
 459 
 460   if (!codec_dev)
 461     return -ENXIO;
 462 
 463   codec_dev--;
 464 
 465   devc = (ad1848_info *) audio_devs[codec_dev]->devc;
 466 
 467   if (((cmd >> 8) & 0xff) == 'M')
 468     {
 469       if (cmd & IOC_IN)
 470         switch (cmd & 0xff)
 471           {
 472           case SOUND_MIXER_RECSRC:
 473             return snd_ioctl_return ((int *) arg, ad1848_set_recmask (devc, get_fs_long ((long *) arg)));
 474             break;
 475 
 476           default:
 477             return snd_ioctl_return ((int *) arg, ad1848_mixer_set (devc, cmd & 0xff, get_fs_long ((long *) arg)));
 478           }
 479       else
 480         switch (cmd & 0xff)     /*
 481                                  * Return parameters
 482                                  */
 483           {
 484 
 485           case SOUND_MIXER_RECSRC:
 486             return snd_ioctl_return ((int *) arg, devc->recmask);
 487             break;
 488 
 489           case SOUND_MIXER_DEVMASK:
 490             return snd_ioctl_return ((int *) arg, devc->supported_devices);
 491             break;
 492 
 493           case SOUND_MIXER_STEREODEVS:
 494             return snd_ioctl_return ((int *) arg, devc->supported_devices & ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX));
 495             break;
 496 
 497           case SOUND_MIXER_RECMASK:
 498             return snd_ioctl_return ((int *) arg, devc->supported_rec_devices);
 499             break;
 500 
 501           case SOUND_MIXER_CAPS:
 502             return snd_ioctl_return ((int *) arg, SOUND_CAP_EXCL_INPUT);
 503             break;
 504 
 505           default:
 506             return snd_ioctl_return ((int *) arg, ad1848_mixer_get (devc, cmd & 0xff));
 507           }
 508     }
 509   else
 510     return -EINVAL;
 511 }
 512 
 513 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
 514 {
 515   {
 516     "Generic AD1848 codec",
 517     DMA_AUTOMODE,
 518     AFMT_U8,                    /* Will be set later */
 519     NULL,
 520     ad1848_open,
 521     ad1848_close,
 522     ad1848_output_block,
 523     ad1848_start_input,
 524     ad1848_ioctl,
 525     ad1848_prepare_for_IO,
 526     ad1848_prepare_for_IO,
 527     ad1848_reset,
 528     ad1848_halt,
 529     NULL,
 530     NULL,
 531     ad1848_halt_input,
 532     ad1848_halt_output,
 533     ad1848_trigger
 534   }};
 535 
 536 static struct mixer_operations ad1848_mixer_operations =
 537 {
 538   "AD1848/CS4248/CS4231",
 539   ad1848_mixer_ioctl
 540 };
 541 
 542 static int
 543 ad1848_open (int dev, int mode)
     /*  */
 544 {
 545   ad1848_info    *devc = NULL;
 546   unsigned long   flags;
 547 
 548   if (dev < 0 || dev >= num_audiodevs)
 549     return -ENXIO;
 550 
 551   devc = (ad1848_info *) audio_devs[dev]->devc;
 552 
 553   save_flags (flags);
 554   cli ();
 555   if (devc->opened)
 556     {
 557       restore_flags (flags);
 558       printk ("ad1848: Already opened\n");
 559       return -EBUSY;
 560     }
 561 
 562 
 563   devc->dual_dma = 0;
 564 
 565   if (audio_devs[dev]->flags & DMA_DUPLEX)
 566     {
 567       devc->dual_dma = 1;
 568     }
 569 
 570   devc->intr_active = 0;
 571   devc->opened = 1;
 572   devc->irq_mode = 0;
 573   restore_flags (flags);
 574 /*
 575  * Mute output until the playback really starts. This decreases clicking.
 576  */
 577   ad_mute (devc);
 578 
 579   return 0;
 580 }
 581 
 582 static void
 583 ad1848_close (int dev)
     /*  */
 584 {
 585   unsigned long   flags;
 586   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 587 
 588   DEB (printk ("ad1848_close(void)\n"));
 589 
 590   save_flags (flags);
 591   cli ();
 592 
 593   devc->intr_active = 0;
 594   ad1848_reset (dev);
 595 
 596 
 597   devc->opened = 0;
 598   devc->irq_mode = 0;
 599 
 600   ad_unmute (devc);
 601   restore_flags (flags);
 602 }
 603 
 604 static int
 605 set_speed (ad1848_info * devc, int arg)
     /*  */
 606 {
 607   /*
 608      * The sampling speed is encoded in the least significant nible of I8. The
 609      * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
 610      * three bits select the divisor (indirectly):
 611      *
 612      * The available speeds are in the following table. Keep the speeds in
 613      * the increasing order.
 614    */
 615   typedef struct
 616   {
 617     int             speed;
 618     unsigned char   bits;
 619   }
 620   speed_struct;
 621 
 622   static speed_struct speed_table[] =
 623   {
 624     {5510, (0 << 1) | 1},
 625     {5510, (0 << 1) | 1},
 626     {6620, (7 << 1) | 1},
 627     {8000, (0 << 1) | 0},
 628     {9600, (7 << 1) | 0},
 629     {11025, (1 << 1) | 1},
 630     {16000, (1 << 1) | 0},
 631     {18900, (2 << 1) | 1},
 632     {22050, (3 << 1) | 1},
 633     {27420, (2 << 1) | 0},
 634     {32000, (3 << 1) | 0},
 635     {33075, (6 << 1) | 1},
 636     {37800, (4 << 1) | 1},
 637     {44100, (5 << 1) | 1},
 638     {48000, (6 << 1) | 0}
 639   };
 640 
 641   int             i, n, selected = -1;
 642 
 643   n = sizeof (speed_table) / sizeof (speed_struct);
 644 
 645   if (devc->mode == MD_1845)    /* AD1845 has different timer than others */
 646     {
 647       if (arg < 4000)
 648         arg = 4000;
 649       if (arg > 50000)
 650         arg = 50000;
 651 
 652       devc->speed = arg;
 653       devc->speed_bits = speed_table[selected].bits;
 654       return devc->speed;
 655     }
 656 
 657   if (arg < speed_table[0].speed)
 658     selected = 0;
 659   if (arg > speed_table[n - 1].speed)
 660     selected = n - 1;
 661 
 662   for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 663     if (speed_table[i].speed == arg)
 664       selected = i;
 665     else if (speed_table[i].speed > arg)
 666       {
 667         int             diff1, diff2;
 668 
 669         diff1 = arg - speed_table[i - 1].speed;
 670         diff2 = speed_table[i].speed - arg;
 671 
 672         if (diff1 < diff2)
 673           selected = i - 1;
 674         else
 675           selected = i;
 676       }
 677 
 678   if (selected == -1)
 679     {
 680       printk ("ad1848: Can't find speed???\n");
 681       selected = 3;
 682     }
 683 
 684   devc->speed = speed_table[selected].speed;
 685   devc->speed_bits = speed_table[selected].bits;
 686   return devc->speed;
 687 }
 688 
 689 static int
 690 set_channels (ad1848_info * devc, int arg)
     /*  */
 691 {
 692   if (arg != 1 && arg != 2)
 693     return devc->channels;
 694 
 695   devc->channels = arg;
 696   return arg;
 697 }
 698 
 699 static int
 700 set_format (ad1848_info * devc, int arg)
     /*  */
 701 {
 702 
 703   static struct format_tbl
 704   {
 705     int             format;
 706     unsigned char   bits;
 707   }
 708   format2bits[] =
 709   {
 710     {
 711       0, 0
 712     }
 713     ,
 714     {
 715       AFMT_MU_LAW, 1
 716     }
 717     ,
 718     {
 719       AFMT_A_LAW, 3
 720     }
 721     ,
 722     {
 723       AFMT_IMA_ADPCM, 5
 724     }
 725     ,
 726     {
 727       AFMT_U8, 0
 728     }
 729     ,
 730     {
 731       AFMT_S16_LE, 2
 732     }
 733     ,
 734     {
 735       AFMT_S16_BE, 6
 736     }
 737     ,
 738     {
 739       AFMT_S8, 0
 740     }
 741     ,
 742     {
 743       AFMT_U16_LE, 0
 744     }
 745     ,
 746     {
 747       AFMT_U16_BE, 0
 748     }
 749   };
 750   int             i, n = sizeof (format2bits) / sizeof (struct format_tbl);
 751 
 752   if (!(arg & ad_format_mask[devc->mode]))
 753     arg = AFMT_U8;
 754 
 755   devc->audio_format = arg;
 756 
 757   for (i = 0; i < n; i++)
 758     if (format2bits[i].format == arg)
 759       {
 760         if ((devc->format_bits = format2bits[i].bits) == 0)
 761           return devc->audio_format = AFMT_U8;  /* Was not supported */
 762 
 763         return arg;
 764       }
 765 
 766   /* Still hanging here. Something must be terribly wrong */
 767   devc->format_bits = 0;
 768   return devc->audio_format = AFMT_U8;
 769 }
 770 
 771 static int
 772 ad1848_ioctl (int dev, unsigned int cmd, ioctl_arg arg, int local)
     /*  */
 773 {
 774   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 775 
 776   switch (cmd)
 777     {
 778     case SOUND_PCM_WRITE_RATE:
 779       if (local)
 780         return set_speed (devc, (int) arg);
 781       return snd_ioctl_return ((int *) arg, set_speed (devc, get_fs_long ((long *) arg)));
 782 
 783     case SOUND_PCM_READ_RATE:
 784       if (local)
 785         return devc->speed;
 786       return snd_ioctl_return ((int *) arg, devc->speed);
 787 
 788     case SNDCTL_DSP_STEREO:
 789       if (local)
 790         return set_channels (devc, (int) arg + 1) - 1;
 791       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg) + 1) - 1);
 792 
 793     case SOUND_PCM_WRITE_CHANNELS:
 794       if (local)
 795         return set_channels (devc, (int) arg);
 796       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg)));
 797 
 798     case SOUND_PCM_READ_CHANNELS:
 799       if (local)
 800         return devc->channels;
 801       return snd_ioctl_return ((int *) arg, devc->channels);
 802 
 803     case SNDCTL_DSP_SAMPLESIZE:
 804       if (local)
 805         return set_format (devc, (int) arg);
 806       return snd_ioctl_return ((int *) arg, set_format (devc, get_fs_long ((long *) arg)));
 807 
 808     case SOUND_PCM_READ_BITS:
 809       if (local)
 810         return devc->audio_format;
 811       return snd_ioctl_return ((int *) arg, devc->audio_format);
 812 
 813     default:;
 814     }
 815   return -EINVAL;
 816 }
 817 
 818 static void
 819 ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 820 {
 821   unsigned long   flags, cnt;
 822   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 823 
 824   cnt = count;
 825 
 826   if (devc->audio_format == AFMT_IMA_ADPCM)
 827     {
 828       cnt /= 4;
 829     }
 830   else
 831     {
 832       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 833         cnt >>= 1;
 834     }
 835   if (devc->channels > 1)
 836     cnt >>= 1;
 837   cnt--;
 838 
 839   if (devc->irq_mode & PCM_ENABLE_OUTPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 840       intrflag &&
 841       cnt == devc->xfer_count)
 842     {
 843       devc->irq_mode |= PCM_ENABLE_OUTPUT;
 844       devc->intr_active = 1;
 845       return;                   /*
 846                                  * Auto DMA mode on. No need to react
 847                                  */
 848     }
 849   save_flags (flags);
 850   cli ();
 851 
 852   if (dma_restart)
 853     {
 854       /* ad1848_halt (dev); */
 855       DMAbuf_start_dma (dev, buf, count, DMA_MODE_WRITE);
 856     }
 857 
 858   ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 859   ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 860 
 861   /* ad_write (devc, 9, ad_read (devc, 9) | 0x01); *//* Playback enable */
 862   ad_unmute (devc);
 863 
 864   devc->xfer_count = cnt;
 865   devc->irq_mode |= PCM_ENABLE_OUTPUT;
 866   devc->intr_active = 1;
 867   restore_flags (flags);
 868 }
 869 
 870 static void
 871 ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 872 {
 873   unsigned long   flags, cnt;
 874   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 875 
 876   cnt = count;
 877   if (devc->audio_format == AFMT_IMA_ADPCM)
 878     {
 879       cnt /= 4;
 880     }
 881   else
 882     {
 883       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 884         cnt >>= 1;
 885     }
 886   if (devc->channels > 1)
 887     cnt >>= 1;
 888   cnt--;
 889 
 890   if (devc->irq_mode & PCM_ENABLE_INPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 891       intrflag &&
 892       cnt == devc->xfer_count)
 893     {
 894       devc->irq_mode |= PCM_ENABLE_INPUT;
 895       devc->intr_active = 1;
 896       return;                   /*
 897                                  * Auto DMA mode on. No need to react
 898                                  */
 899     }
 900   save_flags (flags);
 901   cli ();
 902 
 903   if (dma_restart)
 904     {
 905       /* ad1848_halt (dev); */
 906       DMAbuf_start_dma (dev, buf, count, DMA_MODE_READ);
 907     }
 908 
 909   if (devc->mode == MD_1848 || !devc->dual_dma)         /* Single DMA channel mode */
 910     {
 911       ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 912       ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 913     }
 914   else
 915     /* Dual DMA channel mode */
 916     {
 917       ad_write (devc, 31, (unsigned char) (cnt & 0xff));
 918       ad_write (devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
 919     }
 920 
 921   /*  ad_write (devc, 9, ad_read (devc, 9) | 0x02); *//* Capture enable */
 922   ad_unmute (devc);
 923 
 924   devc->xfer_count = cnt;
 925   devc->irq_mode |= PCM_ENABLE_INPUT;
 926   devc->intr_active = 1;
 927   restore_flags (flags);
 928 }
 929 
 930 static int
 931 ad1848_prepare_for_IO (int dev, int bsize, int bcount)
     /*  */
 932 {
 933   int             timeout;
 934   unsigned char   fs, old_fs;
 935   unsigned long   flags;
 936   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 937 
 938   if (devc->irq_mode)
 939     return 0;
 940 
 941   save_flags (flags);
 942   cli ();
 943   fs = devc->speed_bits | (devc->format_bits << 5);
 944 
 945   if (devc->channels > 1)
 946     fs |= 0x10;
 947 
 948   if (devc->mode == MD_1845)    /* Use alternate speed select registers */
 949     {
 950       fs &= 0xf0;               /* Mask off the rate select bits */
 951 
 952       ad_write (devc, 22, (devc->speed >> 8) & 0xff);   /* Speed MSB */
 953       ad_write (devc, 23, devc->speed & 0xff);  /* Speed LSB */
 954     }
 955 
 956   if (fs == (old_fs = ad_read (devc, 8)))       /* No change */
 957     {
 958       restore_flags (flags);
 959       devc->xfer_count = 0;
 960       return 0;
 961     }
 962 
 963   ad_enter_MCE (devc);          /* Enables changes to the format select reg */
 964   ad_write (devc, 8, fs);
 965   /*
 966    * Write to I8 starts resyncronization. Wait until it completes.
 967    */
 968   timeout = 10000;
 969   while (timeout > 0 && inb (devc->base) == 0x80)
 970     timeout--;
 971 
 972   /*
 973      * If mode == 2 (CS4231), set I28 also. It's the capture format register.
 974    */
 975   if (devc->mode != MD_1848)
 976     {
 977       ad_write (devc, 28, fs);
 978 
 979       /*
 980          * Write to I28 starts resyncronization. Wait until it completes.
 981        */
 982       timeout = 10000;
 983       while (timeout > 0 && inb (devc->base) == 0x80)
 984         timeout--;
 985 
 986     }
 987 
 988   ad_leave_MCE (devc);          /*
 989                                  * Starts the calibration process.
 990                                  */
 991   restore_flags (flags);
 992   devc->xfer_count = 0;
 993 
 994 #ifndef EXCLUDE_SEQUENCER
 995   if (dev == timer_installed && devc->timer_running)
 996     if ((fs & 0x01) != (old_fs & 0x01))
 997       {
 998         ad1848_tmr_reprogram (dev);
 999       }
1000 #endif
1001   return 0;
1002 }
1003 
1004 static void
1005 ad1848_reset (int dev)
     /*  */
1006 {
1007   ad1848_halt (dev);
1008 }
1009 
1010 static void
1011 ad1848_halt (int dev)
     /*  */
1012 {
1013   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1014   unsigned long   flags;
1015 
1016   save_flags (flags);
1017   cli ();
1018 
1019   ad_mute (devc);
1020   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1021 
1022   ad_write (devc, 15, 0);       /* Clear DMA counter */
1023   ad_write (devc, 14, 0);       /* Clear DMA counter */
1024 
1025   if (devc->mode != MD_1848)
1026     {
1027       ad_write (devc, 30, 0);   /* Clear DMA counter */
1028       ad_write (devc, 31, 0);   /* Clear DMA counter */
1029     }
1030 
1031   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1032 
1033   outb (0, io_Status (devc));   /* Clear interrupt status */
1034   outb (0, io_Status (devc));   /* Clear interrupt status */
1035   devc->irq_mode = 0;
1036 
1037   /* DMAbuf_reset_dma (dev); */
1038   restore_flags (flags);
1039 }
1040 
1041 static void
1042 ad1848_halt_input (int dev)
     /*  */
1043 {
1044   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1045   unsigned long   flags;
1046 
1047   if (devc->mode == MD_1848)
1048     {
1049       ad1848_halt (dev);
1050       return;
1051     }
1052 
1053   save_flags (flags);
1054   cli ();
1055 
1056   ad_mute (devc);
1057   ad_write (devc, 9, ad_read (devc, 9) & ~0x02);        /* Stop capture */
1058 
1059 
1060   devc->irq_mode &= ~PCM_ENABLE_INPUT;
1061 
1062   restore_flags (flags);
1063 }
1064 
1065 static void
1066 ad1848_halt_output (int dev)
     /*  */
1067 {
1068   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1069   unsigned long   flags;
1070 
1071   if (devc->mode == MD_1848)
1072     {
1073       ad1848_halt (dev);
1074       return;
1075     }
1076 
1077   save_flags (flags);
1078   cli ();
1079 
1080   ad_mute (devc);
1081   ad_write (devc, 9, ad_read (devc, 9) & ~0x01);        /* Stop playback */
1082 
1083 
1084   devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1085 
1086   restore_flags (flags);
1087 }
1088 
1089 static void
1090 ad1848_trigger (int dev, int state)
     /*  */
1091 {
1092   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1093   unsigned long   flags;
1094   unsigned char   tmp;
1095 
1096   save_flags (flags);
1097   cli ();
1098   state &= devc->irq_mode;
1099 
1100   tmp = ad_read (devc, 9) & ~0x03;
1101   if (state & PCM_ENABLE_INPUT)
1102     tmp |= 0x02;
1103   if (state & PCM_ENABLE_OUTPUT)
1104     tmp |= 0x01;
1105   ad_write (devc, 9, tmp);
1106 
1107   restore_flags (flags);
1108 }
1109 
1110 int
1111 ad1848_detect (int io_base, int *ad_flags, sound_os_info * osp)
     /*  */
1112 {
1113 
1114   unsigned char   tmp;
1115   int             i;
1116   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1117   unsigned char   tmp1 = 0xff, tmp2 = 0xff;
1118 
1119   if (ad_flags)
1120     *ad_flags = 0;
1121 
1122   if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1123     {
1124       DDB (printk ("ad1848 detect error - step 0\n"));
1125       return 0;
1126     }
1127   if (check_region (io_base, 4))
1128     {
1129       printk ("\n\nad1848.c: Port %x not free.\n\n", io_base);
1130       return 0;
1131     }
1132 
1133   devc->base = io_base;
1134   devc->irq_ok = 0;
1135   devc->timer_running = 0;
1136   devc->MCE_bit = 0x40;
1137   devc->irq = 0;
1138   devc->opened = 0;
1139   devc->chip_name = "AD1848";
1140   devc->mode = MD_1848;         /* AD1848 or CS4248 */
1141   devc->osp = osp;
1142 
1143   /*
1144      * Check that the I/O address is in use.
1145      *
1146      * The bit 0x80 of the base I/O port is known to be 0 after the
1147      * chip has performed it's power on initialization. Just assume
1148      * this has happened before the OS is starting.
1149      *
1150      * If the I/O address is unused, it typically returns 0xff.
1151    */
1152   if ((inb (devc->base) & 0x80) != 0x00)        /* Not a AD1848 */
1153     {
1154       DDB (printk ("ad1848 detect error - step A (%02x)\n",
1155                    inb (devc->base)));
1156       return 0;
1157     }
1158 
1159   /*
1160      * Test if it's possible to change contents of the indirect registers.
1161      * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1162      * so try to avoid using it.
1163    */
1164 
1165   ad_write (devc, 0, 0xaa);
1166   ad_write (devc, 1, 0x45);     /* 0x55 with bit 0x10 clear */
1167 
1168   if ((tmp1 = ad_read (devc, 0)) != 0xaa || (tmp2 = ad_read (devc, 1)) != 0x45)
1169     {
1170       DDB (printk ("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1171       return 0;
1172     }
1173 
1174   ad_write (devc, 0, 0x45);
1175   ad_write (devc, 1, 0xaa);
1176 
1177   if ((tmp1 = ad_read (devc, 0)) != 0x45 || (tmp2 = ad_read (devc, 1)) != 0xaa)
1178     {
1179       DDB (printk ("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1180       return 0;
1181     }
1182 
1183   /*
1184      * The indirect register I12 has some read only bits. Lets
1185      * try to change them.
1186    */
1187 
1188   tmp = ad_read (devc, 12);
1189   ad_write (devc, 12, (~tmp) & 0x0f);
1190 
1191   if ((tmp & 0x0f) != ((tmp1 = ad_read (devc, 12)) & 0x0f))
1192     {
1193       DDB (printk ("ad1848 detect error - step D (%x)\n", tmp1));
1194       return 0;
1195     }
1196 
1197   /*
1198      * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1199      *   0x01=RevB and 0x0A=RevC.
1200    */
1201 
1202   /*
1203      * The original AD1848/CS4248 has just 15 indirect registers. This means
1204      * that I0 and I16 should return the same value (etc.).
1205      * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1206      * with CS4231.
1207    */
1208 
1209   ad_write (devc, 12, 0);       /* Mode2=disabled */
1210 
1211   for (i = 0; i < 16; i++)
1212     if ((tmp1 = ad_read (devc, i)) != (tmp2 = ad_read (devc, i + 16)))
1213       {
1214         DDB (printk ("ad1848 detect error - step F(%d/%x/%x)\n", i, tmp1, tmp2));
1215         return 0;
1216       }
1217 
1218   /*
1219      * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1220      * The bit 0x80 is always 1 in CS4248 and CS4231.
1221    */
1222 
1223   ad_write (devc, 12, 0x40);    /* Set mode2, clear 0x80 */
1224 
1225   tmp1 = ad_read (devc, 12);
1226   if (tmp1 & 0x80)
1227     {
1228       if (ad_flags)
1229         *ad_flags |= AD_F_CS4248;
1230 
1231       devc->chip_name = "CS4248";       /* Our best knowledge just now */
1232     }
1233 
1234   if ((tmp1 & 0xc0) == (0x80 | 0x40))
1235     {
1236       /*
1237          *      CS4231 detected - is it?
1238          *
1239          *      Verify that setting I0 doesn't change I16.
1240        */
1241       ad_write (devc, 16, 0);   /* Set I16 to known value */
1242 
1243       ad_write (devc, 0, 0x45);
1244       if ((tmp1 = ad_read (devc, 16)) != 0x45)  /* No change -> CS4231? */
1245         {
1246 
1247           ad_write (devc, 0, 0xaa);
1248           if ((tmp1 = ad_read (devc, 16)) == 0xaa)      /* Rotten bits? */
1249             {
1250               DDB (printk ("ad1848 detect error - step H(%x)\n", tmp1));
1251               return 0;
1252             }
1253 
1254           /*
1255              * Verify that some bits of I25 are read only.
1256            */
1257 
1258           tmp1 = ad_read (devc, 25);    /* Original bits */
1259           ad_write (devc, 25, ~tmp1);   /* Invert all bits */
1260           if ((ad_read (devc, 25) & 0xe7) == (tmp1 & 0xe7))
1261             {
1262               int             id;
1263 
1264               /*
1265                *      It's at least CS4231
1266                */
1267               devc->chip_name = "CS4231";
1268 
1269 #ifdef MOZART_PORT
1270               if (devc->base != MOZART_PORT + 4)
1271 #endif
1272                 devc->mode = MD_4231;
1273 
1274               /*
1275                * It could be an AD1845 or CS4231A as well.
1276                * CS4231 and AD1845 report the same revision info in I25
1277                * while the CS4231A reports different.
1278                */
1279 
1280               id = ad_read (devc, 25) & 0xe7;
1281 
1282               switch (id)
1283                 {
1284 
1285                 case 0xa0:
1286                   devc->chip_name = "CS4231A";
1287                   devc->mode = MD_4231A;
1288                   break;
1289 
1290                 case 0xa2:
1291                   devc->chip_name = "CS4232";
1292                   devc->mode = MD_4231A;
1293                   break;
1294 
1295                 case 0xb2:
1296                   devc->chip_name = "CS4232A";
1297                   devc->mode = MD_4231A;
1298                   break;
1299 
1300                 case 0x80:
1301                   {
1302                     /* 
1303                      * It must be a CS4231 or AD1845. The register I23 of
1304                      * CS4231 is undefined and it appears to be read only.
1305                      * AD1845 uses I23 for setting sample rate. Assume
1306                      * the chip is AD1845 if I23 is changeable.
1307                      */
1308 
1309                     unsigned char   tmp = ad_read (devc, 23);
1310 
1311                     ad_write (devc, 23, ~tmp);
1312                     if (ad_read (devc, 23) != tmp)      /* AD1845 ? */
1313                       {
1314                         devc->chip_name = "AD1845";
1315                         devc->mode = MD_1845;
1316                       }
1317 
1318                     ad_write (devc, 23, tmp);   /* Restore */
1319                   }
1320                   break;
1321 
1322                 default:        /* Assume CS4231 */
1323                   devc->mode = MD_4231;
1324 
1325                 }
1326             }
1327           ad_write (devc, 25, tmp1);    /* Restore bits */
1328 
1329         }
1330     }
1331 
1332   if (ad_flags)
1333     {
1334       if (devc->mode != MD_1848)
1335         *ad_flags |= AD_F_CS4231;
1336     }
1337 
1338   return 1;
1339 }
1340 
1341 void
1342 ad1848_init (char *name, int io_base, int irq, int dma_playback, int dma_capture, int share_dma, sound_os_info * osp)
     /*  */
1343 {
1344   /*
1345      * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1346      *   so that this driver doesn't need to allocate/deallocate it.
1347      *   The actually used IRQ is ABS(irq).
1348    */
1349 
1350   /*
1351      * Initial values for the indirect registers of CS4248/AD1848.
1352    */
1353   static int      init_values[] =
1354   {
1355     0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x80, 0x80,
1356     0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1357 
1358   /* Positions 16 to 31 just for CS4231 */
1359     0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1360     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1361   };
1362   int             i, my_dev;
1363   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1364 
1365   if (!ad1848_detect (io_base, NULL, osp))
1366     return;
1367 
1368   request_region (devc->base, 4, devc->chip_name);
1369 
1370   devc->irq = (irq > 0) ? irq : 0;
1371   devc->opened = 0;
1372   devc->timer_ticks = 0;
1373   devc->osp = osp;
1374 
1375   if (nr_ad1848_devs != 0)
1376     {
1377       memcpy ((char *) &ad1848_pcm_operations[nr_ad1848_devs],
1378               (char *) &ad1848_pcm_operations[0],
1379               sizeof (struct audio_operations));
1380     }
1381 
1382   for (i = 0; i < 16; i++)
1383     ad_write (devc, i, init_values[i]);
1384 
1385   ad_mute (devc);               /* Initialize some variables */
1386   ad_unmute (devc);             /* Leave it unmuted now */
1387 
1388   if (devc->mode > MD_1848)
1389     {
1390       if (dma_capture == dma_playback || dma_capture == -1 || dma_playback == -1)
1391         {
1392           ad_write (devc, 9, ad_read (devc, 9) | 0x04);         /* Single DMA mode */
1393           ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1394         }
1395       else
1396         {
1397           ad_write (devc, 9, ad_read (devc, 9) & ~0x04);        /* Dual DMA mode */
1398           ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_DUPLEX;
1399         }
1400 
1401       ad_write (devc, 12, ad_read (devc, 12) | 0x40);   /* Mode2 = enabled */
1402       for (i = 16; i < 32; i++)
1403         ad_write (devc, i, init_values[i]);
1404 
1405       if (devc->mode == MD_4231A)
1406         ad_write (devc, 9, init_values[9] | 0x18);      /* Enable full calibration */
1407 
1408       if (devc->mode == MD_1845)
1409         ad_write (devc, 27, init_values[27] | 0x08);    /* Alternate freq select enabled */
1410     }
1411   else
1412     ad_write (devc, 9, ad_read (devc, 9) | 0x04);       /* Single DMA mode */
1413 
1414   outb (0, io_Status (devc));   /* Clear pending interrupts */
1415 
1416   if (name != NULL && name[0] != 0)
1417     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1418              "%s (%s)", name, devc->chip_name);
1419   else
1420     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1421              "Generic audio codec (%s)", devc->chip_name);
1422 
1423   printk (" <%s>", ad1848_pcm_operations[nr_ad1848_devs].name);
1424 
1425   if (num_audiodevs < MAX_AUDIO_DEV)
1426     {
1427       audio_devs[my_dev = num_audiodevs++] = &ad1848_pcm_operations[nr_ad1848_devs];
1428       if (irq > 0)
1429         {
1430           audio_devs[my_dev]->devc = devc;
1431           irq2dev[irq] = my_dev;
1432           if (snd_set_irq_handler (devc->irq, ad1848_interrupt,
1433                                    audio_devs[my_dev]->name,
1434                                    devc->osp) < 0)
1435             {
1436               printk ("ad1848: IRQ in use\n");
1437             }
1438 
1439 #ifdef NO_IRQ_TEST
1440           if (devc->mode != MD_1848)
1441             {
1442               int             x;
1443               unsigned char   tmp = ad_read (devc, 16);
1444 
1445               devc->timer_ticks = 0;
1446 
1447               ad_write (devc, 21, 0x00);        /* Timer msb */
1448               ad_write (devc, 20, 0x10);        /* Timer lsb */
1449 
1450               ad_write (devc, 16, tmp | 0x40);  /* Enable timer */
1451               for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1452               ad_write (devc, 16, tmp & ~0x40);         /* Disable timer */
1453 
1454               if (devc->timer_ticks == 0)
1455                 printk ("[IRQ conflict???]");
1456               else
1457                 devc->irq_ok = 1;
1458 
1459             }
1460           else
1461             devc->irq_ok = 1;   /* Couldn't test. assume it's OK */
1462 #else
1463           devc->irq_ok = 1;
1464 #endif
1465         }
1466       else if (irq < 0)
1467         irq2dev[-irq] = devc->dev_no = my_dev;
1468 
1469       audio_devs[my_dev]->dmachan1 = dma_playback;
1470       audio_devs[my_dev]->dmachan2 = dma_capture;
1471       audio_devs[my_dev]->buffsize = DSP_BUFFSIZE;
1472       audio_devs[my_dev]->devc = devc;
1473       audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1474       nr_ad1848_devs++;
1475 
1476 #ifndef EXCLUDE_SEQUENCER
1477       if (devc->mode != MD_1848 && devc->irq_ok)
1478         ad1848_tmr_install (my_dev);
1479 #endif
1480 
1481       if (!share_dma)
1482         {
1483           if (sound_alloc_dma (dma_playback, "Sound System"))
1484             printk ("ad1848.c: Can't allocate DMA%d\n", dma_playback);
1485 
1486           if (dma_capture != dma_playback)
1487             if (sound_alloc_dma (dma_capture, "Sound System (capture)"))
1488               printk ("ad1848.c: Can't allocate DMA%d\n", dma_capture);
1489         }
1490 
1491       /*
1492          * Toggle the MCE bit. It completes the initialization phase.
1493        */
1494 
1495       ad_enter_MCE (devc);      /* In case the bit was off */
1496       ad_leave_MCE (devc);
1497 
1498       if (num_mixers < MAX_MIXER_DEV)
1499         {
1500           mixer2codec[num_mixers] = my_dev + 1;
1501           audio_devs[my_dev]->mixer_dev = num_mixers;
1502           mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1503           ad1848_mixer_reset (devc);
1504         }
1505     }
1506   else
1507     printk ("AD1848: Too many PCM devices available\n");
1508 }
1509 
1510 void
1511 ad1848_unload (int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
     /*  */
1512 {
1513   int             i, dev = 0;
1514   ad1848_info    *devc = NULL;
1515 
1516   for (i = 0; devc == NULL && nr_ad1848_devs; i++)
1517     if (dev_info[i].base == io_base)
1518       {
1519         devc = &dev_info[i];
1520         dev = devc->dev_no;
1521       }
1522 
1523   if (devc != NULL)
1524     {
1525       release_region (devc->base, 4);
1526 
1527       if (!share_dma)
1528         {
1529           if (irq > 0)
1530             snd_release_irq (devc->irq);
1531 
1532           sound_free_dma (audio_devs[dev]->dmachan1);
1533 
1534           if (audio_devs[dev]->dmachan2 != audio_devs[dev]->dmachan1)
1535             sound_free_dma (audio_devs[dev]->dmachan2);
1536         }
1537     }
1538   else
1539     printk ("ad1848: Can't find device to be undoaded. Base=%x\n",
1540             io_base);
1541 }
1542 
1543 void
1544 ad1848_interrupt (int irq, struct pt_regs *dummy)
     /*  */
1545 {
1546   unsigned char   status;
1547   ad1848_info    *devc;
1548   int             dev;
1549 
1550   if (irq < 0 || irq > 15)
1551     {
1552       dev = -1;
1553     }
1554   else
1555     dev = irq2dev[irq];
1556 
1557   if (dev < 0 || dev >= num_audiodevs)
1558     {
1559       for (irq = 0; irq < 17; irq++)
1560         if (irq2dev[irq] != -1)
1561           break;
1562 
1563       if (irq > 15)
1564         {
1565           printk ("ad1848.c: Bogus interrupt %d\n", irq);
1566           return;
1567         }
1568 
1569       dev = irq2dev[irq];
1570       devc = (ad1848_info *) audio_devs[dev]->devc;
1571     }
1572   else
1573     devc = (ad1848_info *) audio_devs[dev]->devc;
1574 
1575   status = inb (io_Status (devc));
1576 
1577   if (status == 0x80)
1578     printk ("ad1848_interrupt: Why?\n");
1579 
1580   if (status & 0x01)
1581     {
1582       int             alt_stat;
1583 
1584       if (devc->mode != MD_1848)
1585         {
1586           alt_stat = ad_read (devc, 24);
1587           if (alt_stat & 0x40)  /* Timer interrupt */
1588             {
1589               devc->timer_ticks++;
1590 #ifndef EXCLUDE_SEQUENCER
1591               if (timer_installed == dev && devc->timer_running)
1592                 sound_timer_interrupt ();
1593 #endif
1594             }
1595         }
1596       else
1597         alt_stat = 0xff;
1598 
1599       if (devc->opened && devc->irq_mode & PCM_ENABLE_INPUT && alt_stat & 0x20)
1600         {
1601           DMAbuf_inputintr (dev);
1602         }
1603 
1604       if (devc->opened && devc->irq_mode & PCM_ENABLE_OUTPUT && alt_stat & 0x10)
1605         {
1606           DMAbuf_outputintr (dev, 1);
1607         }
1608     }
1609 
1610   outb (0, io_Status (devc));   /* Clear interrupt status */
1611 
1612 }
1613 
1614 /*
1615  * Some extra code for the MS Sound System
1616  */
1617 
1618 int
1619 probe_ms_sound (struct address_info *hw_config)
     /*  */
1620 {
1621   unsigned char   tmp;
1622 
1623   if (check_region (hw_config->io_base, 8))
1624     {
1625       printk ("MSS: I/O port conflict\n");
1626       return 0;
1627     }
1628 
1629 #if !defined(EXCLUDE_AEDSP16) && defined(AEDSP16_MSS)
1630   /*
1631      * Initialize Audio Excel DSP 16 to MSS: before any operation
1632      * we must enable MSS I/O ports.
1633    */
1634 
1635   InitAEDSP16_MSS (hw_config);
1636 #endif
1637 
1638   if (hw_config->card_subtype == 1)     /* Has IRQ/DMA registers */
1639     return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1640 
1641   /*
1642      * Check if the IO port returns valid signature. The original MS Sound
1643      * system returns 0x04 while some cards (AudioTriX Pro for example)
1644      * return 0x00 or 0x0f.
1645    */
1646 
1647   if ((tmp = inb (hw_config->io_base + 3)) == 0xff)     /* Bus float */
1648     return 0;
1649   if ((tmp & 0x3f) != 0x04 &&
1650       (tmp & 0x3f) != 0x0f &&
1651       (tmp & 0x3f) != 0x00)
1652     {
1653       DDB (printk ("No MSS signature detected on port 0x%x (0x%x)\n",
1654                    hw_config->io_base, inb (hw_config->io_base + 3)));
1655       return 0;
1656     }
1657 
1658   if (hw_config->irq > 11)
1659     {
1660       printk ("MSS: Bad IRQ %d\n", hw_config->irq);
1661       return 0;
1662     }
1663 
1664   if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
1665     {
1666       printk ("MSS: Bad DMA %d\n", hw_config->dma);
1667       return 0;
1668     }
1669 
1670   /*
1671      * Check that DMA0 is not in use with a 8 bit board.
1672    */
1673 
1674   if (hw_config->dma == 0 && inb (hw_config->io_base + 3) & 0x80)
1675     {
1676       printk ("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1677       return 0;
1678     }
1679 
1680   if (hw_config->irq > 7 && hw_config->irq != 9 && inb (hw_config->io_base + 3) & 0x80)
1681     {
1682       printk ("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1683       return 0;
1684     }
1685 
1686   return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1687 }
1688 
1689 long
1690 attach_ms_sound (long mem_start, struct address_info *hw_config)
     /*  */
1691 {
1692   static char     interrupt_bits[12] =
1693   {
1694     -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1695   };
1696   char            bits;
1697 
1698   static char     dma_bits[4] =
1699   {
1700     1, 2, 0, 3
1701   };
1702 
1703   int             config_port = hw_config->io_base + 0, version_port = hw_config->io_base + 3;
1704 
1705   if (!ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp))
1706     return mem_start;
1707 
1708   /*
1709      * Set the IRQ and DMA addresses.
1710    */
1711 
1712   bits = interrupt_bits[hw_config->irq];
1713   if (bits == -1)
1714     return mem_start;
1715 
1716   outb (bits | 0x40, config_port);
1717   if ((inb (version_port) & 0x40) == 0)
1718     printk ("[IRQ Conflict?]");
1719 
1720   outb (bits | dma_bits[hw_config->dma], config_port);  /* Write IRQ+DMA setup */
1721 
1722   ad1848_init ("MS Sound System", hw_config->io_base + 4,
1723                hw_config->irq,
1724                hw_config->dma,
1725                hw_config->dma, 0, hw_config->osp);
1726   request_region (hw_config->io_base, 4, "WSS config");
1727   return mem_start;
1728 }
1729 
1730 void
1731 unload_ms_sound (struct address_info *hw_config)
     /*  */
1732 {
1733   ad1848_unload (hw_config->io_base + 4,
1734                  hw_config->irq,
1735                  hw_config->dma,
1736                  hw_config->dma, 0);
1737   release_region (hw_config->io_base, 4);
1738 }
1739 
1740 /*
1741  * WSS compatible PnP codec support
1742  */
1743 
1744 int
1745 probe_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1746 {
1747   return ad1848_detect (hw_config->io_base, NULL, hw_config->osp);
1748 }
1749 
1750 long
1751 attach_pnp_ad1848 (long mem_start, struct address_info *hw_config)
     /*  */
1752 {
1753 
1754   ad1848_init (hw_config->name, hw_config->io_base,
1755                hw_config->irq,
1756                hw_config->dma,
1757                hw_config->dma2, 0, hw_config->osp);
1758   return mem_start;
1759 }
1760 
1761 void
1762 unload_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1763 {
1764   ad1848_unload (hw_config->io_base,
1765                  hw_config->irq,
1766                  hw_config->dma,
1767                  hw_config->dma2, 0);
1768   release_region (hw_config->io_base, 4);
1769 }
1770 
1771 #ifndef EXCLUDE_SEQUENCER
1772 /*
1773  * Timer stuff (for /dev/music).
1774  */
1775 
1776 static unsigned int current_interval = 0;
1777 
1778 static unsigned int
1779 ad1848_tmr_start (int dev, unsigned int usecs)
     /*  */
1780 {
1781   unsigned long   flags;
1782   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1783   unsigned long   xtal_nsecs;   /* nanoseconds per xtal oscillaror tick */
1784   unsigned long   divider;
1785 
1786   save_flags (flags);
1787   cli ();
1788 
1789 /*
1790  * Length of the timer interval (in nanoseconds) depends on the
1791  * selected crystal oscillator. Check this from bit 0x01 of I8.
1792  *
1793  * AD1845 has just one oscillator which has cycle time of 10.050 us
1794  * (when a 24.576 MHz xtal oscillator is used).
1795  *
1796  * Convert requested interval to nanoseconds before computing
1797  * the timer divider.
1798  */
1799 
1800   if (devc->mode == MD_1845)
1801     xtal_nsecs = 10050;
1802   else if (ad_read (devc, 8) & 0x01)
1803     xtal_nsecs = 9920;
1804   else
1805     xtal_nsecs = 9969;
1806 
1807   divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
1808 
1809   if (divider < 100)            /* Don't allow shorter intervals than about 1ms */
1810     divider = 100;
1811 
1812   if (divider > 65535)          /* Overflow check */
1813     divider = 65535;
1814 
1815   ad_write (devc, 21, (divider >> 8) & 0xff);   /* Set upper bits */
1816   ad_write (devc, 20, divider & 0xff);  /* Set lower bits */
1817   ad_write (devc, 16, ad_read (devc, 16) | 0x40);       /* Start the timer */
1818   devc->timer_running = 1;
1819   restore_flags (flags);
1820 
1821   return current_interval = (divider * xtal_nsecs + 500) / 1000;
1822 }
1823 
1824 static void
1825 ad1848_tmr_reprogram (int dev)
     /*  */
1826 {
1827 /*
1828  *    Audio driver has changed sampling rate so that a different xtal
1829  *      oscillator was selected. We have to reprogram the timer rate.
1830  */
1831 
1832   ad1848_tmr_start (dev, current_interval);
1833   sound_timer_syncinterval (current_interval);
1834 }
1835 
1836 static void
1837 ad1848_tmr_disable (int dev)
     /*  */
1838 {
1839   unsigned long   flags;
1840   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1841 
1842   save_flags (flags);
1843   cli ();
1844   ad_write (devc, 16, ad_read (devc, 16) & ~0x40);
1845   devc->timer_running = 0;
1846   restore_flags (flags);
1847 }
1848 
1849 static void
1850 ad1848_tmr_restart (int dev)
     /*  */
1851 {
1852   unsigned long   flags;
1853   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1854 
1855   if (current_interval == 0)
1856     return;
1857 
1858   save_flags (flags);
1859   cli ();
1860   ad_write (devc, 16, ad_read (devc, 16) | 0x40);
1861   devc->timer_running = 1;
1862   restore_flags (flags);
1863 }
1864 
1865 static struct sound_lowlev_timer ad1848_tmr =
1866 {
1867   0,
1868   ad1848_tmr_start,
1869   ad1848_tmr_disable,
1870   ad1848_tmr_restart
1871 };
1872 
1873 static int
1874 ad1848_tmr_install (int dev)
     /*  */
1875 {
1876 
1877   if (timer_installed != -1)
1878     return 0;                   /* Don't install another timer */
1879 
1880   timer_installed = ad1848_tmr.dev = dev;
1881   sound_timer_init (&ad1848_tmr, audio_devs[dev]->name);
1882 
1883   return 1;
1884 }
1885 #endif
1886 #endif
/* */
root/drivers/sound/ad1848.c

DEFINITIONS
