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1 /* $Id: scc.h,v 1.11 1995/08/24 21:06:24 jreuter Exp jreuter $ */
2
3 #ifndef _SCC_H
4 #define _SCC_H
5
6 /* selection of hardware types */
7
8 #define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */
9 #define EAGLE 0x01 /* hardware type for EAGLE card */
10 #define PC100 0x02 /* hardware type for PC100 card */
11 #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */
12 #define DRSI 0x08 /* hardware type for DRSI PC*Packet card */
13 #define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */
14
15 /* Constants */
16
17 #define MAXSCC 4 /* number of max. supported chips */
18 #define MAX_IBUFS 200 /* change this if you run out of memory */
19 #define BUFSIZE 128 /* must not exceed 4096 */
20 #define TPS 25 /* scc_timer(): Ticks Per Second */
21
22 #define SCC_TIMER 3
23
24 #define SCC_PARANOIA_CHECK /* tell the user if something is going wrong */
25
26 /* ioctl() commands */
27
28 /* !!! NEW VALUES !!! */
29
30 #define TIOCSCCINI 0x5470 /* init driver */
31 #define TIOCCHANINI 0x5471 /* init channel */
32
33 #define TIOCGKISS 0x5472 /* get kiss parameter */
34 #define TIOCSKISS 0x5473 /* set kiss parameter */
35
36 #define TIOCSCCSTAT 0x5474 /* get scc status */
37
38
39 /* magic number */
40
41 #define SCC_MAGIC 0x8530 /* ;-) */
42
43 /* KISS protocol flags */
44 #define FEND 192
45 #define FESC 219
46 #define TFEND 220
47 #define TFESC 221
48
49 /* KISS state machine */
50
51 #define KISS_IDLE 0
52 #define KISS_DATA 1
53 #define KISS_ESCAPE 2
54 #define KISS_RXFRAME 3
55
56 /* Device parameter control (from WAMPES) */
57
58 #define PARAM_TXDELAY 1
59 #define PARAM_PERSIST 2
60 #define PARAM_SLOTTIME 3
61 #define PARAM_TXTAIL 4
62 #define PARAM_FULLDUP 5
63 #define PARAM_SOFTDCD 6 /* was: PARAM_HW */
64 #define PARAM_MUTE 7 /* ??? */
65 #define PARAM_DTR 8
66 #define PARAM_RTS 9
67 #define PARAM_SPEED 10
68 #define PARAM_ENDDELAY 11 /* ??? */
69 #define PARAM_GROUP 12
70 #define PARAM_IDLE 13
71 #define PARAM_MIN 14
72 #define PARAM_MAXKEY 15
73 #define PARAM_WAIT 16
74 #define PARAM_MAXDEFER 17
75 #define PARAM_TX 18
76 #define PARAM_SLIP 19
77 #define PARAM_RETURN 255 /* reset kiss mode */
78
79 #define TIMER_OFF 65535U /* to switch off timers */
80 #define NO_SUCH_PARAM 65534U /* param not implemented */
81
82 /* channel grouping */
83
84 #define RXGROUP 0x100 /* if set, only tx when all channels clear */
85 #define TXGROUP 0x200 /* if set, don't transmit simultaneously */
86
87 /* Tx/Rx clock sources */
88
89 #define CLK_DPLL 0 /* normal halfduplex operation */
90 #define CLK_EXTERNAL 1 /* external clocking (G3RUH/DF9IC modems) */
91 #define CLK_DIVIDER 2 /* Rx = DPLL, Tx = divider (fullduplex with */
92 /* modems without clock regeneration */
93
94 /* Tx state */
95
96 #define TXS_IDLE 0 /* Transmitter off, no data pending */
97 #define TXS_BUSY 1 /* waiting for permission to send / tailtime */
98 #define TXS_ACTIVE 2 /* Transmitter on, sending data */
99 #define TXS_NEWFRAME 3 /* reset CRC and send (next) frame */
100
101 #define TX_ON 1 /* command for scc_key_trx() */
102 #define TX_OFF 0 /* dto */
103
104 /* Buffer management */
105
106 #define BT_RECEIVE 1 /* buffer allocated by receive */
107 #define BT_TRANSMIT 2 /* buffer allocated by transmit */
108
109 #define QUEUE_THRES MAX_IBUFS/20 /* maximum amount of packets being queued */
110 #define QUEUE_HYST 3 /* leave QUEUE_HYST packets untouched */
111
112 #define NULLBUF (struct mbuf *)0
113 #define NULLBUFP (struct mbuf **)0
114
115
116 typedef unsigned short io_port; /* type definition for an 'io port address' */
117 typedef unsigned short ioaddr; /* old def */
118
119 #ifdef SCC_DELAY
120 #define Inb(port) inb_p(port)
121 #define Outb(port, val) outb_p(val, port)
122 #else
123 #define Inb(port) inb(port)
124 #define Outb(port, val) outb(val, port)
125 #endif
126
127 /* some nasty macros (esp. Expired) */
128
129 #define TIMER_STOPPED 65535U
130 #define Running(k) (scc->k != TIMER_STOPPED)
131 #define Expired(k) (scc->k != TIMER_STOPPED) && (!(scc->k) || (--(scc->k) == 0))
132 #define Stop_Timer(k) scc->k = TIMER_STOPPED
133
134
135 /* Basic message buffer structure */
136
137 /* looks familiar? Hmm, yes... */
138
139 struct mbuf {
140 struct mbuf *next; /* Links mbufs belonging to single packets */
141 struct mbuf *anext; /* Links packets on queues */
142
143 char type; /* who allocated this buffer? */
144 int time_out; /* unimplemented yet */
145
146 int size; /* Size of associated data buffer */
147 int refcnt; /* Reference count */
148 struct mbuf *dup; /* Pointer to duplicated mbuf */
149 char data[BUFSIZE]; /* Active working pointers */
150 int cnt;
151 int in_use;
152 };
153
154
155 struct sccbuf {
156 struct mbuf *bp;
157 int inuse;
158 };
159
160
161 /* SCC channel control structure for KISS */
162
163 struct scc_kiss {
164 unsigned char txdelay; /* Transmit Delay 10 ms/cnt */
165 unsigned char persist; /* Persistence (0-255) as a % */
166 unsigned char slottime; /* Delay to wait on persistence hit */
167 unsigned char tailtime; /* Delay after XMTR OFF */
168 unsigned char fulldup; /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */
169 unsigned char waittime; /* Waittime before any transmit attempt */
170 unsigned int maxkeyup; /* Maximum time to transmit (seconds) */
171 unsigned char mintime; /* Minimal offtime after MAXKEYUP timeout */
172 unsigned int idletime; /* Maximum idle time in ALWAYS KEYED mode (seconds) */
173 unsigned int maxdefer; /* Timer for CSMA channel busy limit */
174 unsigned char tx_inhibit; /* Transmit is not allowed when set */
175 unsigned char group; /* group ID for AX.25 TX interlocking */
176 unsigned char not_slip; /* set to zero: use SLIP instead of KISS */
177 unsigned char softdcd; /* use DPLL instead of DCD pin for carrier detect */
178 };
179
180
181 /* SCC statistical information */
182
183 struct scc_stat {
184 long rxints; /* Receiver interrupts */
185 long txints; /* Transmitter interrupts */
186 long exints; /* External/status interrupts */
187 long spints; /* Special receiver interrupts */
188
189 long txframes; /* Packets sent */
190 long rxframes; /* Number of Frames Actally Received */
191 long rxerrs; /* CRC Errors */
192 long txerrs; /* KISS errors */
193
194 unsigned int nospace; /* "Out of buffers" */
195 unsigned int rx_over; /* Receiver Overruns */
196 unsigned int tx_under; /* Transmitter Underruns */
197
198 unsigned int tx_state; /* Transmitter state */
199
200 char tx_kiss_state; /* state of the kiss interpreter */
201 char rx_kiss_state; /* state of the kiss encoder */
202
203 int tx_queued; /* tx frames enqueued */
204 int rx_queued; /* rx frames enqueued */
205
206 unsigned int rx_alloc; /* allocated rx_buffers */
207 unsigned int tx_alloc; /* allocated tx_buffers */
208 unsigned int used_buf; /* used buffers (should be rx_alloc+tx_alloc) */
209 };
210
211
212 struct scc_modem{
213 long speed; /* Line speed, bps */
214 char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */
215 char nrz; /* NRZ instead of NRZI */
216 };
217
218 struct ioctl_command {
219 int command; /* one of the KISS-Commands devined above */
220 unsigned param; /* KISS-Param */
221 };
222
223 /* SCC channel structure */
224
225 struct scc_channel {
226 int magic; /* magic word */
227
228 int init; /* channel exists? */
229 struct tty_struct *tty; /* link to tty control structure */
230 unsigned char tty_opened;
231
232 io_port ctrl; /* I/O address of CONTROL register */
233 io_port data; /* I/O address of DATA register */
234 char enhanced; /* Enhanced SCC support */
235
236 unsigned char wreg[16]; /* Copy of last written value in WRx */
237 unsigned char status; /* Copy of R0 at last external interrupt */
238
239 struct scc_kiss kiss; /* control structure for KISS params */
240 struct scc_stat stat; /* statistical information */
241 struct scc_modem modem; /* modem information */
242
243 struct mbuf *rbp; /* rx: Head of mbuf chain being filled */
244 struct mbuf *rbp1; /* rx: Pointer to mbuf currently being written */
245 struct mbuf *rcvq; /* Pointer to mbuf packets currently received */
246
247 struct mbuf *sndq; /* tx: Packets awaiting transmission */
248 struct mbuf *tbp; /* tx: Transmit mbuf being sent */
249
250 struct mbuf *sndq1; /* Pointer to mbuf currently under construction */
251 struct mbuf *sndq2; /* Pointer to mbuf currently under construction */
252
253
254 /* Timer */
255
256 unsigned int t_dwait; /* wait time (DWAIT) */
257 unsigned int t_slot; /* channel sample frequency */
258 unsigned int t_txdel; /* TX delay */
259 unsigned int t_tail; /* tail time */
260 unsigned int t_maxk; /* max. key up */
261 unsigned int t_min; /* minimal key up */
262 unsigned int t_idle; /* */
263 unsigned int t_mbusy; /* time until defer if channel busy */
264 };
265
266 /* some variables for scc_rx_timer() bound together in a struct */
267
268 struct rx_timer_CB {
269 char lock;
270 unsigned long expires;
271 struct scc_channel *scc;
272 };
273
274
275 /* 8530 Serial Communications Controller Register definitions */
276 #define FLAG 0x7e
277
278 /* Write Register 0 */
279 #define R0 0 /* Register selects */
280 #define R1 1
281 #define R2 2
282 #define R3 3
283 #define R4 4
284 #define R5 5
285 #define R6 6
286 #define R7 7
287 #define R8 8
288 #define R9 9
289 #define R10 10
290 #define R11 11
291 #define R12 12
292 #define R13 13
293 #define R14 14
294 #define R15 15
295
296 #define NULLCODE 0 /* Null Code */
297 #define POINT_HIGH 0x8 /* Select upper half of registers */
298 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
299 #define SEND_ABORT 0x18 /* HDLC Abort */
300 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
301 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
302 #define ERR_RES 0x30 /* Error Reset */
303 #define RES_H_IUS 0x38 /* Reset highest IUS */
304
305 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
306 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
307 #define RES_EOM_L 0xC0 /* Reset EOM latch */
308
309 /* Write Register 1 */
310
311 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
312 #define TxINT_ENAB 0x2 /* Tx Int Enable */
313 #define PAR_SPEC 0x4 /* Parity is special condition */
314
315 #define RxINT_DISAB 0 /* Rx Int Disable */
316 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
317 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
318 #define INT_ERR_Rx 0x18 /* Int on error only */
319
320 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
321 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
322 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
323
324 /* Write Register 2 (Interrupt Vector) */
325
326 /* Write Register 3 */
327
328 #define RxENABLE 0x1 /* Rx Enable */
329 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
330 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
331 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
332 #define ENT_HM 0x10 /* Enter Hunt Mode */
333 #define AUTO_ENAB 0x20 /* Auto Enables */
334 #define Rx5 0x0 /* Rx 5 Bits/Character */
335 #define Rx7 0x40 /* Rx 7 Bits/Character */
336 #define Rx6 0x80 /* Rx 6 Bits/Character */
337 #define Rx8 0xc0 /* Rx 8 Bits/Character */
338
339 /* Write Register 4 */
340
341 #define PAR_ENA 0x1 /* Parity Enable */
342 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
343
344 #define SYNC_ENAB 0 /* Sync Modes Enable */
345 #define SB1 0x4 /* 1 stop bit/char */
346 #define SB15 0x8 /* 1.5 stop bits/char */
347 #define SB2 0xc /* 2 stop bits/char */
348
349 #define MONSYNC 0 /* 8 Bit Sync character */
350 #define BISYNC 0x10 /* 16 bit sync character */
351 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
352 #define EXTSYNC 0x30 /* External Sync Mode */
353
354 #define X1CLK 0x0 /* x1 clock mode */
355 #define X16CLK 0x40 /* x16 clock mode */
356 #define X32CLK 0x80 /* x32 clock mode */
357 #define X64CLK 0xC0 /* x64 clock mode */
358
359 /* Write Register 5 */
360
361 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
362 #define RTS 0x2 /* RTS */
363 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
364 #define TxENAB 0x8 /* Tx Enable */
365 #define SND_BRK 0x10 /* Send Break */
366 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
367 #define Tx7 0x20 /* Tx 7 bits/character */
368 #define Tx6 0x40 /* Tx 6 bits/character */
369 #define Tx8 0x60 /* Tx 8 bits/character */
370 #define DTR 0x80 /* DTR */
371
372 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
373
374 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
375
376 /* Write Register 8 (transmit buffer) */
377
378 /* Write Register 9 (Master interrupt control) */
379 #define VIS 1 /* Vector Includes Status */
380 #define NV 2 /* No Vector */
381 #define DLC 4 /* Disable Lower Chain */
382 #define MIE 8 /* Master Interrupt Enable */
383 #define STATHI 0x10 /* Status high */
384 #define NORESET 0 /* No reset on write to R9 */
385 #define CHRB 0x40 /* Reset channel B */
386 #define CHRA 0x80 /* Reset channel A */
387 #define FHWRES 0xc0 /* Force hardware reset */
388
389 /* Write Register 10 (misc control bits) */
390 #define BIT6 1 /* 6 bit/8bit sync */
391 #define LOOPMODE 2 /* SDLC Loop mode */
392 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
393 #define MARKIDLE 8 /* Mark/flag on idle */
394 #define GAOP 0x10 /* Go active on poll */
395 #define NRZ 0 /* NRZ mode */
396 #define NRZI 0x20 /* NRZI mode */
397 #define FM1 0x40 /* FM1 (transition = 1) */
398 #define FM0 0x60 /* FM0 (transition = 0) */
399 #define CRCPS 0x80 /* CRC Preset I/O */
400
401 /* Write Register 11 (Clock Mode control) */
402 #define TRxCXT 0 /* TRxC = Xtal output */
403 #define TRxCTC 1 /* TRxC = Transmit clock */
404 #define TRxCBR 2 /* TRxC = BR Generator Output */
405 #define TRxCDP 3 /* TRxC = DPLL output */
406 #define TRxCOI 4 /* TRxC O/I */
407 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
408 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
409 #define TCBR 0x10 /* Transmit clock = BR Generator output */
410 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
411 #define RCRTxCP 0 /* Receive clock = RTxC pin */
412 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
413 #define RCBR 0x40 /* Receive clock = BR Generator output */
414 #define RCDPLL 0x60 /* Receive clock = DPLL output */
415 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
416
417 /* Write Register 12 (lower byte of baud rate generator time constant) */
418
419 /* Write Register 13 (upper byte of baud rate generator time constant) */
420
421 /* Write Register 14 (Misc control bits) */
422 #define BRENABL 1 /* Baud rate generator enable */
423 #define BRSRC 2 /* Baud rate generator source */
424 #define DTRREQ 4 /* DTR/Request function */
425 #define AUTOECHO 8 /* Auto Echo */
426 #define LOOPBAK 0x10 /* Local loopback */
427 #define SEARCH 0x20 /* Enter search mode */
428 #define RMC 0x40 /* Reset missing clock */
429 #define DISDPLL 0x60 /* Disable DPLL */
430 #define SSBR 0x80 /* Set DPLL source = BR generator */
431 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
432 #define SFMM 0xc0 /* Set FM mode */
433 #define SNRZI 0xe0 /* Set NRZI mode */
434
435 /* Write Register 15 (external/status interrupt control) */
436 #define ZCIE 2 /* Zero count IE */
437 #define DCDIE 8 /* DCD IE */
438 #define SYNCIE 0x10 /* Sync/hunt IE */
439 #define CTSIE 0x20 /* CTS IE */
440 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
441 #define BRKIE 0x80 /* Break/Abort IE */
442
443
444 /* Read Register 0 */
445 #define Rx_CH_AV 0x1 /* Rx Character Available */
446 #define ZCOUNT 0x2 /* Zero count */
447 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
448 #define DCD 0x8 /* DCD */
449 #define SYNC_HUNT 0x10 /* Sync/hunt */
450 #define CTS 0x20 /* CTS */
451 #define TxEOM 0x40 /* Tx underrun */
452 #define BRK_ABRT 0x80 /* Break/Abort */
453
454 /* Read Register 1 */
455 #define ALL_SNT 0x1 /* All sent */
456 /* Residue Data for 8 Rx bits/char programmed */
457 #define RES3 0x8 /* 0/3 */
458 #define RES4 0x4 /* 0/4 */
459 #define RES5 0xc /* 0/5 */
460 #define RES6 0x2 /* 0/6 */
461 #define RES7 0xa /* 0/7 */
462 #define RES8 0x6 /* 0/8 */
463 #define RES18 0xe /* 1/8 */
464 #define RES28 0x0 /* 2/8 */
465 /* Special Rx Condition Interrupts */
466 #define PAR_ERR 0x10 /* Parity error */
467 #define Rx_OVR 0x20 /* Rx Overrun Error */
468 #define CRC_ERR 0x40 /* CRC/Framing Error */
469 #define END_FR 0x80 /* End of Frame (SDLC) */
470
471 /* Read Register 2 (channel B only) - Interrupt vector */
472
473 #define VECTOR_MASK 0x06
474
475 #define TXINT 0x00
476 #define EXINT 0x02
477 #define RXINT 0x04
478 #define SPINT 0x06
479
480
481 /* Read Register 3 (interrupt pending register) ch a only */
482 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
483 #define CHBTxIP 0x2 /* Channel B Tx IP */
484 #define CHBRxIP 0x4 /* Channel B Rx IP */
485 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
486 #define CHATxIP 0x10 /* Channel A Tx IP */
487 #define CHARxIP 0x20 /* Channel A Rx IP */
488
489 /* Read Register 8 (receive data register) */
490
491 /* Read Register 10 (misc status bits) */
492 #define ONLOOP 2 /* On loop */
493 #define LOOPSEND 0x10 /* Loop sending */
494 #define CLK2MIS 0x40 /* Two clocks missing */
495 #define CLK1MIS 0x80 /* One clock missing */
496
497 /* Read Register 12 (lower byte of baud rate generator constant) */
498
499 /* Read Register 13 (upper byte of baud rate generator constant) */
500
501 /* Read Register 15 (value of WR 15) */
502
503
504 /* 8536 register definitions */
505
506 #define CIO_MICR 0x00 /* Master interrupt control register */
507 #define CIO_MCCR 0x01 /* Master configuration control register */
508 #define CIO_CTMS1 0x1c /* Counter/timer mode specification #1 */
509 #define CIO_CTMS2 0x1d /* Counter/timer mode specification #2 */
510 #define CIO_CTMS3 0x1e /* Counter/timer mode specification #3 */
511 #define CIO_IVR 0x04 /* Interrupt vector register */
512
513 #define CIO_CSR1 0x0a /* Command and status register CTC #1 */
514 #define CIO_CSR2 0x0b /* Command and status register CTC #2 */
515 #define CIO_CSR3 0x0c /* Command and status register CTC #3 */
516
517 #define CIO_CT1MSB 0x16 /* CTC #1 Timer constant - MSB */
518 #define CIO_CT1LSB 0x17 /* CTC #1 Timer constant - LSB */
519 #define CIO_CT2MSB 0x18 /* CTC #2 Timer constant - MSB */
520 #define CIO_CT2LSB 0x19 /* CTC #2 Timer constant - LSB */
521 #define CIO_CT3MSB 0x1a /* CTC #3 Timer constant - MSB */
522 #define CIO_CT3LSB 0x1b /* CTC #3 Timer constant - LSB */
523 #define CIO_PDCA 0x23 /* Port A data direction control */
524 #define CIO_PDCB 0x2b /* Port B data direction control */
525
526 #define CIO_GCB 0x04 /* CTC Gate command bit */
527 #define CIO_TCB 0x02 /* CTC Trigger command bit */
528 #define CIO_IE 0xc0 /* CTC Interrupt enable (set) */
529 #define CIO_CIP 0x20 /* CTC Clear interrupt pending */
530 #define CIO_IP 0x20 /* CTC Interrupt pending */
531
532
533 /* 8580/85180/85280 Enhanced SCC register definitions */
534
535 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
536 #define AUTOTXF 0x01 /* Auto Tx Flag */
537 #define AUTOEOM 0x02 /* Auto EOM Latch Reset */
538 #define AUTORTS 0x04 /* Auto RTS */
539 #define TXDNRZI 0x08 /* TxD Pulled High in SDLC NRZI mode */
540 #define FASTDTR 0x10 /* Fast DTR/REQ Mode */
541 #define CRCCBCR 0x20 /* CRC Check Bytes Completely Received */
542 #define EXTRDEN 0x40 /* Extended Read Enabled */
543
544 /* Write Register 15 (external/status interrupt control) */
545 #define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */
546 #define FIFOE 4 /* FIFO Enable */
547
548 /* Read Register 6 (frame status FIFO) */
549 #define BCLSB 0xff /* LSB of 14 bits count */
550
551 /* Read Register 7 (frame status FIFO) */
552 #define BCMSB 0x3f /* MSB of 14 bits count */
553 #define FDA 0x40 /* FIFO Data Available Status */
554 #define FOY 0x80 /* FIFO Overflow Status */
555
556 #endif /* _SCC_H */
557
558 /* global functions */
559
560 extern int scc_init(void);
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*/