include/asm-ppc/processor.h

/* */
This source file includes following definitions.
start_thread
thread_saved_pc
   1 #ifndef __ASM_PPC_PROCESSOR_H
   2 #define __ASM_PPC_PROCESSOR_H
   3 
   4 /*
   5  * PowerPC machine specifics
   6  */
   7 
   8 #ifndef _PPC_MACHINE_H_
   9 #define _PPC_MACHINE_H_ 
  10 
  11 /* Bit encodings for Machine State Register (MSR) */
  12 #define MSR_POW         (1<<18)         /* Enable Power Management */
  13 #define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
  14 #define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
  15 #define MSR_EE          (1<<15)         /* External Interrupt enable */
  16 #define MSR_PR          (1<<14)         /* Supervisor/User privelege */
  17 #define MSR_FP          (1<<13)         /* Floating Point enable */
  18 #define MSR_ME          (1<<12)         /* Machine Check enable */
  19 #define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
  20 #define MSR_SE          (1<<10)         /* Single Step */
  21 #define MSR_BE          (1<<9)          /* Branch Trace */
  22 #define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
  23 #define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
  24 #define MSR_IR          (1<<5)          /* Instruction MMU enable */
  25 #define MSR_DR          (1<<4)          /* Data MMU enable */
  26 #define MSR_RI          (1<<1)          /* Recoverable Exception */
  27 #define MSR_LE          (1<<0)          /* Little-Endian enable */
  28 
  29 #define MSR_            MSR_FP|MSR_FE0|MSR_FE1|MSR_ME
  30 #define MSR_USER        MSR_|MSR_PR|MSR_EE|MSR_IR|MSR_DR
  31 
  32 /* Bit encodings for Hardware Implementation Register (HID0) */
  33 #define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
  34 #define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
  35 #define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
  36 #define HID0_SBCLK      (1<<27)
  37 #define HID0_EICE       (1<<26)
  38 #define HID0_ECLK       (1<<25)
  39 #define HID0_PAR        (1<<24)
  40 #define HID0_DOZE       (1<<23)
  41 #define HID0_NAP        (1<<22)
  42 #define HID0_SLEEP      (1<<21)
  43 #define HID0_DPM        (1<<20)
  44 #define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
  45 #define HID0_DCE        (1<<14)         /* Data Cache Enable */
  46 #define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
  47 #define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
  48 #define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
  49 #define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
  50  
  51 #endif
  52 
  53 static inline void start_thread(struct pt_regs * regs, unsigned long eip, unsigned long esp)
     /*  */
  54 {
  55   regs->nip = eip;
  56   regs->gpr[1] = esp;
  57   regs->msr = MSR_USER;
  58 }
  59 
  60 
  61 /*
  62  * Bus types
  63  */
  64 #define EISA_bus 0
  65 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
  66 #define MCA_bus 0
  67 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
  68 
  69 /*
  70  * Write Protection works right in supervisor mode on the PowerPC
  71  */
  72 
  73 #define wp_works_ok 1
  74 #define wp_works_ok__is_a_macro /* for versions in ksyms.c */
  75 
  76 /*
  77  * User space process size: 2GB. This is hardcoded into a few places,
  78  * so don't change it unless you know what you are doing.
  79  *
  80  * "this is gonna have to change to 1gig for the sparc" - David S. Miller
  81  */
  82 #define TASK_SIZE       (0x80000000UL)
  83 
  84 struct thread_struct 
  85    {
  86         unsigned long   ksp;            /* Kernel stack pointer */
  87         unsigned long   *pg_tables;     /* MMU information */
  88         unsigned long   segs[16];       /* MMU Segment registers */
  89         unsigned long   last_pc;        /* PC when last entered system */
  90         double          fpr[32];        /* Complete floating point set */
  91    };
  92 
  93 #define INIT_TSS  { \
  94         0, 0, 0, \
  95         0, 0, 0, \
  96         0, 0, 0, \
  97 }
  98 
  99 #define INIT_MMAP { &init_mm, 0, 0x40000000, \
 100                       PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC }
 101 
 102 
 103 
 104 
 105 /*
 106  * Return saved PC of a blocked thread.  This assumes the frame pointer
 107  * is the 6th saved long on the kernel stack and that the saved return
 108  * address is the first long in the frame.  This all holds provided the
 109  * thread blocked through a call to schedule().
 110  */
 111 static inline unsigned long thread_saved_pc(struct thread_struct *t)
     /*  */
 112 {
 113         unsigned long fp;
 114 
 115         fp = ((unsigned long*)t->ksp)[6];
 116         return *(unsigned long*)fp;
 117 }
 118 
 119 #endif
 120
/* */
root/include/asm-ppc/processor.h

INCLUDED FROM

DEFINITIONS
