arch/mips/kernel/gdb-low.S

/* */
   1 /*
   2  * arch/mips/kernel/gdb-low.S
   3  *
   4  * gdb-low.S contains the low-level trap handler for the GDB stub.
   5  *
   6  * Copyright (C) 1995 Andreas Busse
   7  */
   8 
   9 #include <linux/sys.h>
  10 
  11 #include <asm/asm.h>
  12 #include <asm/segment.h>
  13 #include <asm/mipsregs.h>
  14 #include <asm/mipsconfig.h>
  15 #include <asm/stackframe.h>
  16 #include <asm/gdb-stub.h>
  17 
  18 /*
  19  * The low level trap handler
  20  */
  21                 .align  5
  22                 NESTED(trap_low, GDB_FR_SIZE, sp)
  23                 .set    noat
  24                 .set    noreorder
  25 
  26                 mfc0    k0,CP0_STATUS
  27                 sll     k0,3                    /* extract cu0 bit */
  28                 bltz    k0,1f
  29                 move    k1,sp
  30 
  31                 /*
  32                  * Called from user mode, new stack
  33                  */
  34                 lui     k1,%hi(kernelsp)
  35                 lw      k1,%lo(kernelsp)(k1)
  36 1:              move    k0,sp
  37                 subu    sp,k1,GDB_FR_SIZE
  38                 sw      k0,GDB_FR_REG29(sp)
  39                 sw      v0,GDB_FR_REG2(sp)
  40 
  41 /*
  42  * first save the CP0 and special registers
  43  */
  44 
  45                 mfc0    v0,CP0_STATUS
  46                 sw      v0,GDB_FR_STATUS(sp)
  47                 mfc0    v0,CP0_CAUSE
  48                 sw      v0,GDB_FR_CAUSE(sp)
  49                 mfc0    v0,CP0_EPC
  50                 sw      v0,GDB_FR_EPC(sp)
  51                 mfc0    v0,CP0_BADVADDR
  52                 sw      v0,GDB_FR_BADVADDR(sp)
  53                 mfhi    v0
  54                 sw      v0,GDB_FR_HI(sp)
  55                 mflo    v0
  56                 sw      v0,GDB_FR_LO(sp)
  57 
  58 /*
  59  * Now the integer registers
  60  */
  61 
  62                 sw      zero,GDB_FR_REG0(sp)            /* I know... */
  63                 sw      $1,GDB_FR_REG1(sp)
  64                 /* v0 already saved */
  65                 sw      v1,GDB_FR_REG3(sp)
  66                 sw      a0,GDB_FR_REG4(sp)
  67                 sw      a1,GDB_FR_REG5(sp)
  68                 sw      a2,GDB_FR_REG6(sp)
  69                 sw      a3,GDB_FR_REG7(sp)
  70                 sw      t0,GDB_FR_REG8(sp)
  71                 sw      t1,GDB_FR_REG9(sp)
  72                 sw      t2,GDB_FR_REG10(sp)
  73                 sw      t3,GDB_FR_REG11(sp)
  74                 sw      t4,GDB_FR_REG12(sp)
  75                 sw      t5,GDB_FR_REG13(sp)
  76                 sw      t6,GDB_FR_REG14(sp)
  77                 sw      t7,GDB_FR_REG15(sp)
  78                 sw      s0,GDB_FR_REG16(sp)
  79                 sw      s1,GDB_FR_REG17(sp)
  80                 sw      s2,GDB_FR_REG18(sp)
  81                 sw      s3,GDB_FR_REG19(sp)
  82                 sw      s4,GDB_FR_REG20(sp)
  83                 sw      s5,GDB_FR_REG21(sp)
  84                 sw      s6,GDB_FR_REG22(sp)
  85                 sw      s7,GDB_FR_REG23(sp)
  86                 sw      t8,GDB_FR_REG24(sp)
  87                 sw      t9,GDB_FR_REG25(sp)
  88                 sw      k0,GDB_FR_REG26(sp)
  89                 sw      k1,GDB_FR_REG27(sp)
  90                 sw      gp,GDB_FR_REG28(sp)
  91                 /* sp already saved */
  92                 sw      fp,GDB_FR_REG30(sp)
  93                 sw      ra,GDB_FR_REG31(sp)
  94 
  95                 STI                             /* disable interrupts */
  96                 
  97 /*
  98  * Followed by the floating point registers
  99  */
 100                 mfc0    v0,CP0_STATUS           /* check if the FPU is enabled */
 101                 srl     v0,v0,16
 102                 andi    v0,v0,(ST0_CU1 >> 16)
 103                 beqz    v0,2f                   /* disabled, skip */
 104                 nop
 105 
 106                 swc1    $0,GDB_FR_FPR0(sp)
 107                 swc1    $1,GDB_FR_FPR1(sp)
 108                 swc1    $2,GDB_FR_FPR2(sp)
 109                 swc1    $3,GDB_FR_FPR3(sp)
 110                 swc1    $4,GDB_FR_FPR4(sp)
 111                 swc1    $5,GDB_FR_FPR5(sp)
 112                 swc1    $6,GDB_FR_FPR6(sp)
 113                 swc1    $7,GDB_FR_FPR7(sp)
 114                 swc1    $8,GDB_FR_FPR8(sp)
 115                 swc1    $9,GDB_FR_FPR9(sp)
 116                 swc1    $10,GDB_FR_FPR10(sp)
 117                 swc1    $11,GDB_FR_FPR11(sp)
 118                 swc1    $12,GDB_FR_FPR12(sp)
 119                 swc1    $13,GDB_FR_FPR13(sp)
 120                 swc1    $14,GDB_FR_FPR14(sp)
 121                 swc1    $15,GDB_FR_FPR15(sp)
 122                 swc1    $16,GDB_FR_FPR16(sp)
 123                 swc1    $17,GDB_FR_FPR17(sp)
 124                 swc1    $18,GDB_FR_FPR18(sp)
 125                 swc1    $19,GDB_FR_FPR19(sp)
 126                 swc1    $20,GDB_FR_FPR20(sp)
 127                 swc1    $21,GDB_FR_FPR21(sp)
 128                 swc1    $22,GDB_FR_FPR22(sp)
 129                 swc1    $23,GDB_FR_FPR23(sp)
 130                 swc1    $24,GDB_FR_FPR24(sp)
 131                 swc1    $25,GDB_FR_FPR25(sp)
 132                 swc1    $26,GDB_FR_FPR26(sp)
 133                 swc1    $27,GDB_FR_FPR27(sp)
 134                 swc1    $28,GDB_FR_FPR28(sp)
 135                 swc1    $29,GDB_FR_FPR29(sp)
 136                 swc1    $30,GDB_FR_FPR30(sp)
 137                 swc1    $31,GDB_FR_FPR31(sp)
 138 
 139 /*
 140  * FPU control registers
 141  */
 142 
 143                 mfc1    v0,CP1_STATUS
 144                 sw      v0,GDB_FR_FSR(sp)
 145                 mfc1    v0,CP1_REVISION
 146                 sw      v0,GDB_FR_FIR(sp)
 147 
 148 /*
 149  * current stack frame ptr
 150  */
 151 
 152 2:              sw      sp,GDB_FR_FRP(sp)
 153 
 154 /*
 155  * CP0 registers (R4000/R4400 unused registers skipped)
 156  */
 157 
 158                 mfc0    v0,CP0_INDEX
 159                 sw      v0,GDB_FR_CP0_INDEX(sp)
 160                 mfc0    v0,CP0_RANDOM
 161                 sw      v0,GDB_FR_CP0_RANDOM(sp)
 162                 mfc0    v0,CP0_ENTRYLO0
 163                 sw      v0,GDB_FR_CP0_ENTRYLO0(sp)
 164                 mfc0    v0,CP0_ENTRYLO1
 165                 sw      v0,GDB_FR_CP0_ENTRYLO1(sp)
 166                 mfc0    v0,CP0_PAGEMASK
 167                 sw      v0,GDB_FR_CP0_PAGEMASK(sp)
 168                 mfc0    v0,CP0_WIRED
 169                 sw      v0,GDB_FR_CP0_WIRED(sp)
 170                 mfc0    v0,CP0_ENTRYHI
 171                 sw      v0,GDB_FR_CP0_ENTRYHI(sp)
 172                 mfc0    v0,CP0_PRID
 173                 sw      v0,GDB_FR_CP0_PRID(sp)
 174 
 175                 .set    at
 176 
 177 /*
 178  * continue with the higher level handler
 179  */
 180 
 181                 move    a0,sp
 182                 jal     handle_exception
 183                 nop
 184 
 185 /*
 186  * restore all writable registers, in reverse order
 187  */
 188 
 189                 .set    noat
 190 
 191                 lw      v0,GDB_FR_CP0_ENTRYHI(sp)
 192                 lw      v1,GDB_FR_CP0_WIRED(sp)
 193                 mtc0    v0,CP0_ENTRYHI
 194                 mtc0    v1,CP0_WIRED
 195                 lw      v0,GDB_FR_CP0_PAGEMASK(sp)
 196                 lw      v1,GDB_FR_CP0_ENTRYLO1(sp)
 197                 mtc0    v0,CP0_PAGEMASK
 198                 mtc0    v1,CP0_ENTRYLO1
 199                 lw      v0,GDB_FR_CP0_ENTRYLO0(sp)
 200                 lw      v1,GDB_FR_CP0_INDEX(sp)
 201                 mtc0    v0,CP0_ENTRYLO0
 202                 mtc0    v1,CP0_INDEX
 203 
 204 /*
 205  * Next, the floating point registers
 206  */
 207                 mfc0    v0,CP0_STATUS           /* check if the FPU is enabled */
 208                 srl     v0,v0,16
 209                 andi    v0,v0,(ST0_CU1 >> 16)
 210                 beqz    v0,3f                   /* disabled, skip */
 211                 nop
 212 
 213                 lwc1    $31,GDB_FR_FPR31(sp)
 214                 lwc1    $30,GDB_FR_FPR30(sp)
 215                 lwc1    $29,GDB_FR_FPR29(sp)
 216                 lwc1    $28,GDB_FR_FPR28(sp)
 217                 lwc1    $27,GDB_FR_FPR27(sp)
 218                 lwc1    $26,GDB_FR_FPR26(sp)
 219                 lwc1    $25,GDB_FR_FPR25(sp)
 220                 lwc1    $24,GDB_FR_FPR24(sp)
 221                 lwc1    $23,GDB_FR_FPR23(sp)
 222                 lwc1    $22,GDB_FR_FPR22(sp)
 223                 lwc1    $21,GDB_FR_FPR21(sp)
 224                 lwc1    $20,GDB_FR_FPR20(sp)
 225                 lwc1    $19,GDB_FR_FPR19(sp)
 226                 lwc1    $18,GDB_FR_FPR18(sp)
 227                 lwc1    $17,GDB_FR_FPR17(sp)
 228                 lwc1    $16,GDB_FR_FPR16(sp)
 229                 lwc1    $15,GDB_FR_FPR15(sp)
 230                 lwc1    $14,GDB_FR_FPR14(sp)
 231                 lwc1    $13,GDB_FR_FPR13(sp)
 232                 lwc1    $12,GDB_FR_FPR12(sp)
 233                 lwc1    $11,GDB_FR_FPR11(sp)
 234                 lwc1    $10,GDB_FR_FPR10(sp)
 235                 lwc1    $9,GDB_FR_FPR9(sp)
 236                 lwc1    $8,GDB_FR_FPR8(sp)
 237                 lwc1    $7,GDB_FR_FPR7(sp)
 238                 lwc1    $6,GDB_FR_FPR6(sp)
 239                 lwc1    $5,GDB_FR_FPR5(sp)
 240                 lwc1    $4,GDB_FR_FPR4(sp)
 241                 lwc1    $3,GDB_FR_FPR3(sp)
 242                 lwc1    $2,GDB_FR_FPR2(sp)
 243                 lwc1    $1,GDB_FR_FPR1(sp)
 244                 lwc1    $0,GDB_FR_FPR0(sp)
 245 
 246 /*
 247  * Now the CP0 and integer registers
 248  */
 249 
 250 3:              mfc0    t0,CP0_STATUS
 251                 ori     t0,0x1f
 252                 xori    t0,0x1f
 253                 mtc0    t0,CP0_STATUS
 254 
 255                 lw      v0,GDB_FR_STATUS(sp)
 256                 lw      v1,GDB_FR_EPC(sp)
 257                 mtc0    v0,CP0_STATUS
 258                 mtc0    v1,CP0_EPC
 259                 lw      v0,GDB_FR_HI(sp)
 260                 lw      v1,GDB_FR_LO(sp)
 261                 mthi    v0
 262                 mtlo    v0
 263                 lw      ra,GDB_FR_REG31(sp)
 264                 lw      fp,GDB_FR_REG30(sp)
 265                 lw      gp,GDB_FR_REG28(sp)
 266                 lw      k1,GDB_FR_REG27(sp)
 267                 lw      k0,GDB_FR_REG26(sp)
 268                 lw      t9,GDB_FR_REG25(sp)
 269                 lw      t8,GDB_FR_REG24(sp)
 270                 lw      s7,GDB_FR_REG23(sp)
 271                 lw      s6,GDB_FR_REG22(sp)
 272                 lw      s5,GDB_FR_REG21(sp)
 273                 lw      s4,GDB_FR_REG20(sp)
 274                 lw      s3,GDB_FR_REG19(sp)
 275                 lw      s2,GDB_FR_REG18(sp)
 276                 lw      s1,GDB_FR_REG17(sp)
 277                 lw      s0,GDB_FR_REG16(sp)
 278                 lw      t7,GDB_FR_REG15(sp)
 279                 lw      t6,GDB_FR_REG14(sp)
 280                 lw      t5,GDB_FR_REG13(sp)
 281                 lw      t4,GDB_FR_REG12(sp)
 282                 lw      t3,GDB_FR_REG11(sp)
 283                 lw      t2,GDB_FR_REG10(sp)
 284                 lw      t1,GDB_FR_REG9(sp)
 285                 lw      t0,GDB_FR_REG8(sp)
 286                 lw      a3,GDB_FR_REG7(sp)
 287                 lw      a2,GDB_FR_REG6(sp)
 288                 lw      a1,GDB_FR_REG5(sp)
 289                 lw      a0,GDB_FR_REG4(sp)
 290                 lw      v1,GDB_FR_REG3(sp)
 291                 lw      v0,GDB_FR_REG2(sp)
 292                 lw      $1,GDB_FR_REG1(sp)
 293                 lw      sp,GDB_FR_REG29(sp)             /* Deallocate stack */
 294 
 295                 ERET
 296                 .set    at
 297                 .set    reorder
 298                 END(trap_low)
 299 
 300 /* end of file gdb-low.S */
/* */
root/arch/mips/kernel/gdb-low.S
