include/asm-mips/stackframe.h

/* */
   1 /*
   2  *  include/asm-mips/stackframe.h
   3  *
   4  *  Copyright (C) 1994, 1995 Waldorf Electronics
   5  *  written by Ralf Baechle
   6  */
   7 
   8 #ifndef __ASM_MIPS_STACKFRAME_H
   9 #define __ASM_MIPS_STACKFRAME_H
  10 
  11 /*
  12  * Stack layout for all exceptions:
  13  *
  14  * ptrace needs to have all regs on the stack. If the order here is changed,
  15  * it needs to be updated in include/asm-mips/ptrace.h
  16  *
  17  * The first PTRSIZE*5 bytes are argument save space for C subroutines.
  18  */
  19 #define FR_REG1         (PTRSIZE*5)
  20 #define FR_REG2         ((FR_REG1) + 4)
  21 #define FR_REG3         ((FR_REG2) + 4)
  22 #define FR_REG4         ((FR_REG3) + 4)
  23 #define FR_REG5         ((FR_REG4) + 4)
  24 #define FR_REG6         ((FR_REG5) + 4)
  25 #define FR_REG7         ((FR_REG6) + 4)
  26 #define FR_REG8         ((FR_REG7) + 4)
  27 #define FR_REG9         ((FR_REG8) + 4)
  28 #define FR_REG10        ((FR_REG9) + 4)
  29 #define FR_REG11        ((FR_REG10) + 4)
  30 #define FR_REG12        ((FR_REG11) + 4)
  31 #define FR_REG13        ((FR_REG12) + 4)
  32 #define FR_REG14        ((FR_REG13) + 4)
  33 #define FR_REG15        ((FR_REG14) + 4)
  34 #define FR_REG16        ((FR_REG15) + 4)
  35 #define FR_REG17        ((FR_REG16) + 4)
  36 #define FR_REG18        ((FR_REG17) + 4)
  37 #define FR_REG19        ((FR_REG18) + 4)
  38 #define FR_REG20        ((FR_REG19) + 4)
  39 #define FR_REG21        ((FR_REG20) + 4)
  40 #define FR_REG22        ((FR_REG21) + 4)
  41 #define FR_REG23        ((FR_REG22) + 4)
  42 #define FR_REG24        ((FR_REG23) + 4)
  43 #define FR_REG25        ((FR_REG24) + 4)
  44 
  45 /*
  46  * $26 (k0) and $27 (k1) not saved
  47  */
  48 #define FR_REG28        ((FR_REG25) + 4)
  49 #define FR_REG29        ((FR_REG28) + 4)
  50 #define FR_REG30        ((FR_REG29) + 4)
  51 #define FR_REG31        ((FR_REG30) + 4)
  52 
  53 /*
  54  * Saved special registers
  55  */
  56 #define FR_LO           ((FR_REG31) + 4)
  57 #define FR_HI           ((FR_LO) + 4)
  58 
  59 /*
  60  * Saved cp0 registers follow
  61  */
  62 #define FR_STATUS       ((FR_HI) + 4)
  63 #define FR_EPC          ((FR_STATUS) + 4)
  64 #define FR_CAUSE        ((FR_EPC) + 4)
  65 
  66 /*
  67  * Some goodies...
  68  */
  69 #define FR_INTERRUPT    ((FR_CAUSE) + 4)
  70 #define FR_ORIG_REG2    ((FR_INTERRUPT) + 4)
  71 #define FR_PAD1         ((FR_ORIG_REG2) + 4)
  72 
  73 /*
  74  * Size of stack frame, word/double word alignment
  75  */
  76 #define FR_SIZE         ((((FR_PAD1) + 4) + (PTRSIZE-1)) & ~(PTRSIZE-1))
  77 
  78 #ifdef __R4000__
  79 
  80 #define SAVE_ALL                                        \
  81                 mfc0    k0,CP0_STATUS;                  \
  82                 sll     k0,3;     /* extract cu0 bit */ \
  83                 bltz    k0,8f;                          \
  84                 move    k1,sp;                          \
  85                 /*                                      \
  86                  * Called from user mode, new stack     \
  87                  */                                     \
  88                 lui     k1,%hi(kernelsp);               \
  89                 lw      k1,%lo(kernelsp)(k1);           \
  90 8:              move    k0,sp;                          \
  91                 subu    sp,k1,FR_SIZE;                  \
  92                 sw      k0,FR_REG29(sp);                \
  93                 sw      $2,FR_REG2(sp);                 \
  94                 sw      $2,FR_ORIG_REG2(sp);            \
  95                 mfc0    v0,CP0_STATUS;                  \
  96                 sw      v0,FR_STATUS(sp);               \
  97                 mfc0    v0,CP0_CAUSE;                   \
  98                 sw      v0,FR_CAUSE(sp);                \
  99                 mfc0    v0,CP0_EPC;                     \
 100                 sw      v0,FR_EPC(sp);                  \
 101                 mfhi    v0;                             \
 102                 sw      v0,FR_HI(sp);                   \
 103                 mflo    v0;                             \
 104                 sw      v0,FR_LO(sp);                   \
 105                 sw      $1,FR_REG1(sp);                 \
 106                 sw      $3,FR_REG3(sp);                 \
 107                 sw      $4,FR_REG4(sp);                 \
 108                 sw      $5,FR_REG5(sp);                 \
 109                 sw      $6,FR_REG6(sp);                 \
 110                 sw      $7,FR_REG7(sp);                 \
 111                 sw      $8,FR_REG8(sp);                 \
 112                 sw      $9,FR_REG9(sp);                 \
 113                 sw      $10,FR_REG10(sp);               \
 114                 sw      $11,FR_REG11(sp);               \
 115                 sw      $12,FR_REG12(sp);               \
 116                 sw      $13,FR_REG13(sp);               \
 117                 sw      $14,FR_REG14(sp);               \
 118                 sw      $15,FR_REG15(sp);               \
 119                 sw      $16,FR_REG16(sp);               \
 120                 sw      $17,FR_REG17(sp);               \
 121                 sw      $18,FR_REG18(sp);               \
 122                 sw      $19,FR_REG19(sp);               \
 123                 sw      $20,FR_REG20(sp);               \
 124                 sw      $21,FR_REG21(sp);               \
 125                 sw      $22,FR_REG22(sp);               \
 126                 sw      $23,FR_REG23(sp);               \
 127                 sw      $24,FR_REG24(sp);               \
 128                 sw      $25,FR_REG25(sp);               \
 129                 sw      $28,FR_REG28(sp);               \
 130                 sw      $30,FR_REG30(sp);               \
 131                 sw      $31,FR_REG31(sp)
 132 
 133 /*
 134  * Note that we restore the IE flags from stack. This means
 135  * that a modified IE mask will be nullified.
 136  */
 137 #define RESTORE_ALL                                     \
 138                 .set    mips3;                          \
 139                 mfc0    t0,CP0_STATUS;                  \
 140                 ori     t0,0x1f;                        \
 141                 xori    t0,0x1f;                        \
 142                 mtc0    t0,CP0_STATUS;                  \
 143                 \
 144                 lw      v0,FR_STATUS(sp);               \
 145                 lw      v1,FR_LO(sp);                   \
 146                 mtc0    v0,CP0_STATUS;                  \
 147                 mtlo    v1;                             \
 148                 lw      v0,FR_HI(sp);                   \
 149                 lw      v1,FR_EPC(sp);                  \
 150                 mthi    v0;                             \
 151                 mtc0    v1,CP0_EPC;                     \
 152                 lw      $31,FR_REG31(sp);               \
 153                 lw      $30,FR_REG30(sp);               \
 154                 lw      $28,FR_REG28(sp);               \
 155                 lw      $25,FR_REG25(sp);               \
 156                 lw      $24,FR_REG24(sp);               \
 157                 lw      $23,FR_REG23(sp);               \
 158                 lw      $22,FR_REG22(sp);               \
 159                 lw      $21,FR_REG21(sp);               \
 160                 lw      $20,FR_REG20(sp);               \
 161                 lw      $19,FR_REG19(sp);               \
 162                 lw      $18,FR_REG18(sp);               \
 163                 lw      $17,FR_REG17(sp);               \
 164                 lw      $16,FR_REG16(sp);               \
 165                 lw      $15,FR_REG15(sp);               \
 166                 lw      $14,FR_REG14(sp);               \
 167                 lw      $13,FR_REG13(sp);               \
 168                 lw      $12,FR_REG12(sp);               \
 169                 lw      $11,FR_REG11(sp);               \
 170                 lw      $10,FR_REG10(sp);               \
 171                 lw      $9,FR_REG9(sp);                 \
 172                 lw      $8,FR_REG8(sp);                 \
 173                 lw      $7,FR_REG7(sp);                 \
 174                 lw      $6,FR_REG6(sp);                 \
 175                 lw      $5,FR_REG5(sp);                 \
 176                 lw      $4,FR_REG4(sp);                 \
 177                 lw      $3,FR_REG3(sp);                 \
 178                 lw      $2,FR_REG2(sp);                 \
 179                 lw      $1,FR_REG1(sp);                 \
 180                 lw      sp,FR_REG29(sp); /* Deallocate stack */ \
 181                 .set    mips0
 182 
 183 #else /* !defined (__R4000__) */
 184 
 185 #error "Implement SAVE_ALL and RESTORE_ALL!"
 186 
 187 #endif /* !defined (__R4000__) */
 188 
 189 #endif /* __ASM_MIPS_STACKFRAME_H */
/* */
root/include/asm-mips/stackframe.h

INCLUDED FROM
