arch/mips/kernel/tyne.S

/* */
   1 /*
   2  * arch/mips/kernel/tyne.S
   3  *
   4  * Deskstation Tyne specific Assembler code
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf Electronics
   7  * written by Ralf Baechle and Andreas Busse
   8  */
   9 #include <asm/asm.h>
  10 #include <asm/mipsconfig.h>
  11 #include <asm/mipsregs.h>
  12 #include <asm/stackframe.h>
  13 
  14 /*
  15  * Deskstation Tyne interrupt handler
  16  */
  17                 .text
  18                 .set    noreorder
  19                 .set    noat
  20                 .align  5
  21                 NESTED(deskstation_tyne_handle_int, FR_SIZE, sp)
  22                 SAVE_ALL
  23                 CLI
  24                 .set    at
  25                 lui     s0,%hi(PORT_BASE)
  26                 li      t1,0x0f
  27                 sb      t1,%lo(PORT_BASE+0x20)(s0)      # poll command
  28                 lb      t1,%lo(PORT_BASE+0x20)(s0)      # read result
  29                 li      s1,1
  30                 bgtz    t1,Lpoll_second
  31                 andi    t1,t1,7
  32                 /*
  33                  * Acknowledge first pic
  34                  */
  35                 lb      t2,%lo(PORT_BASE+0x21)(s0)
  36                 lui     s4,%hi(cache_21)
  37                 lb      t0,%lo(cache_21)(s4)
  38                 sllv    s1,s1,t1
  39                 or      t0,t0,s1
  40                 sb      t0,%lo(cache_21)(s4)
  41                 sb      t0,%lo(PORT_BASE+0x21)(s0)
  42                 lui     s3,%hi(intr_count)
  43                 lw      t0,%lo(intr_count)(s3)
  44                 li      t2,0x20
  45                 sb      t2,%lo(PORT_BASE+0x20)(s0)
  46                 /*
  47                  * Now call the real handler
  48                  */
  49                 la      t3,IRQ_vectors
  50                 sll     t2,t1,2
  51                 addu    t3,t3,t2
  52                 lw      t3,(t3)
  53                 addiu   t0,t0,1
  54                 jalr    t3
  55                 sw      t0,%lo(intr_count)(s3)                  # delay slot
  56                 lw      t0,%lo(intr_count)(s3)
  57                 /*
  58                  * Unblock first pic
  59                  */
  60                 lbu     t1,%lo(PORT_BASE+0x21)(s0)
  61                 lb      t1,%lo(cache_21)(s4)
  62                 subu    t0,t0,1
  63                 sw      t0,%lo(intr_count)(s3)
  64                 nor     s1,zero,s1
  65                 and     t1,t1,s1
  66                 sb      t1,%lo(cache_21)(s4)
  67                 jr      v0
  68                 sb      t1,%lo(PORT_BASE+0x21)(s0)      # delay slot
  69 
  70                 .align  5
  71 Lpoll_second:   li      t1,0x0f
  72                 sb      t1,%lo(PORT_BASE+0xa0)(s0)      # poll command
  73                 lb      t1,%lo(PORT_BASE+0xa0)(s0)      # read result
  74                 lui     s4,%hi(cache_A1)
  75                 bgtz    t1,spurious_interrupt
  76                 andi    t1,t1,7
  77                 /*
  78                  * Acknowledge second pic
  79                  */
  80                 lbu     t2,%lo(PORT_BASE+0xa1)(s0)
  81                 lb      t3,%lo(cache_A1)(s4)
  82                 sllv    s1,s1,t1
  83                 or      t3,t3,s1
  84                 sb      t3,%lo(cache_A1)(s4)
  85                 sb      t3,%lo(PORT_BASE+0xa1)(s0)
  86                 li      t3,0x20
  87                 sb      t3,%lo(PORT_BASE+0xa0)(s0)
  88                 lui     s3,%hi(intr_count)
  89                 lw      t0,%lo(intr_count)(s3)
  90                 sb      t3,%lo(PORT_BASE+0x20)(s0)
  91                 /*
  92                  * Now call the real handler
  93                  */
  94                 la      t0,IRQ_vectors
  95                 sll     t2,t1,2
  96                 addu    t0,t0,t2
  97                 lw      t0,32(t0)
  98                 addiu   t0,t0,1
  99                 jalr    t0
 100                 sw      t0,%lo(intr_count)(s3)                  # delay slot
 101                 lw      t0,%lo(intr_count)(s3)
 102                 /*
 103                  * Unblock second pic
 104                  */
 105                 lb      t1,%lo(PORT_BASE+0xa1)(s0)
 106                 lb      t1,%lo(cache_A1)(s4)
 107                 subu    t0,t0,1
 108                 lw      t0,%lo(intr_count)(s3)
 109                 nor     s1,zero,s1
 110                 and     t1,t1,s1
 111                 sb      t1,%lo(cache_A1)(s4)
 112                 jr      v0
 113                 sb      t1,%lo(PORT_BASE+0xa1)(s0)      # delay slot
 114                 END(deskstation_tyne_handle_int)
 115 
 116                 .align  5
 117 LEAF(spurious_interrupt)
 118                 /*
 119                  * Nothing happened... (whistle)
 120                  */
 121                 lui     t1,%hi(spurious_count)
 122                 lw      t0,%lo(spurious_count)(t1)
 123                 la      v0,return
 124                 addiu   t0,1
 125                 jr      ra
 126                 sw      t0,%lo(spurious_count)(t1)
 127                 END(spurious_interrupt)
 128
/* */
root/arch/mips/kernel/tyne.S
