include/asm-i386/smp.h

/* */
This source file includes following definitions.
apic_write
apic_read
smp_processor_id
   1 #ifndef __ASM_SMP_H
   2 #define __ASM_SMP_H
   3 
   4 #ifdef __SMP__
   5 #ifndef ASSEMBLY
   6 
   7 #include <asm/i82489.h>
   8 #include <linux/tasks.h>
   9 #include <linux/ptrace.h>
  10 
  11 /*
  12  *      Support definitions for SMP machines following the intel multiprocessing
  13  *      specification
  14  */
  15 
  16 /*
  17  *      This tag identifies where the SMP configuration
  18  *      information is. 
  19  */
  20  
  21 #define SMP_MAGIC_IDENT ('_'<<24)|('P'<<16)|('M'<<8)|'_'
  22 
  23 struct intel_mp_floating
  24 {
  25         char mpf_signature[4];          /* "_MP_"                       */
  26         unsigned long mpf_physptr;      /* Configuration table address  */
  27         unsigned char mpf_length;       /* Our length (paragraphs)      */
  28         unsigned char mpf_specification;/* Specification version        */
  29         unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
  30         unsigned char mpf_feature1;     /* Standard or configuration ?  */
  31         unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
  32         unsigned char mpf_feature3;     /* Unused (0)                   */
  33         unsigned char mpf_feature4;     /* Unused (0)                   */
  34         unsigned char mpf_feature5;     /* Unused (0)                   */
  35 };
  36 
  37 struct mp_config_table
  38 {
  39         char mpc_signature[4];
  40 #define MPC_SIGNATURE "PCMP"
  41         unsigned short mpc_length;      /* Size of table */
  42         char  mpc_spec;                 /* 0x01 */
  43         char  mpc_checksum;
  44         char  mpc_oem[8];
  45         char  mpc_productid[12];
  46         unsigned long mpc_oemptr;       /* 0 if not present */
  47         unsigned short mpc_oemsize;     /* 0 if not present */
  48         unsigned short mpc_oemcount;
  49         unsigned long mpc_lapic;        /* APIC address */
  50         unsigned long reserved;
  51 };
  52 
  53 /* Followed by entries */
  54 
  55 #define MP_PROCESSOR    0
  56 #define MP_BUS          1
  57 #define MP_IOAPIC       2
  58 #define MP_INTSRC       3
  59 #define MP_LINTSRC      4
  60 
  61 struct mpc_config_processor
  62 {
  63         unsigned char mpc_type;
  64         unsigned char mpc_apicid;       /* Local APIC number */
  65         unsigned char mpc_apicver;      /* Its versions */
  66         unsigned char mpc_cpuflag;
  67 #define CPU_ENABLED             1       /* Processor is available */
  68 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
  69         unsigned long mpc_cpufeature;           
  70 #define CPU_STEPPING_MASK 0x0F
  71 #define CPU_MODEL_MASK  0xF0
  72 #define CPU_FAMILY_MASK 0xF00
  73         unsigned long mpc_featureflag;  /* CPUID feature value */
  74         unsigned long mpc_reserved[2];
  75 };
  76 
  77 struct mpc_config_bus
  78 {
  79         unsigned char mpc_type;
  80         unsigned char mpc_busid;
  81         unsigned char mpc_bustype[6] __attribute((packed));
  82 };
  83 
  84 #define BUSTYPE_EISA    "EISA"
  85 #define BUSTYPE_ISA     "ISA"
  86 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
  87 #define BUSTYPE_MCA     "MCA"
  88 #define BUSTYPE_VL      "VL"            /* Local bus */
  89 #define BUSTYPE_PCI     "PCI"
  90 #define BUSTYPE_PCMCIA  "PCMCIA"
  91 
  92 /* We don't understand the others */
  93 
  94 struct mpc_config_ioapic
  95 {
  96         unsigned char mpc_type;
  97         unsigned char mpc_apicid;
  98         unsigned char mpc_apicver;
  99         unsigned char mpc_flags;
 100 #define MPC_APIC_USABLE         0x01
 101         unsigned long mpc_apicaddr;
 102 };
 103 
 104 struct mpc_config_intsrc
 105 {
 106         unsigned char mpc_type;
 107         unsigned char mpc_irqtype;
 108         unsigned short mpc_irqflag;
 109         unsigned char mpc_srcbus;
 110         unsigned char mpc_srcbusirq;
 111         unsigned char mpc_dstapic;
 112         unsigned char mpc_dstirq;
 113 };
 114 
 115 #define MP_INT_VECTORED         0
 116 #define MP_INT_NMI              1
 117 #define MP_INT_SMI              2
 118 #define MP_INT_EXTINT           3
 119 
 120 #define MP_IRQDIR_DEFAULT       0
 121 #define MP_IRQDIR_HIGH          1
 122 #define MP_IRQDIR_LOW           3
 123 
 124 
 125 struct mpc_config_intlocal
 126 {
 127         unsigned char mpc_type;
 128         unsigned char mpc_irqtype;
 129         unsigned short mpc_irqflag;
 130         unsigned char mpc_srcbusid;
 131         unsigned char mpc_srcbusirq;
 132         unsigned char mpc_destapic;     
 133 #define MP_APIC_ALL     0xFF
 134         unsigned char mpc_destapiclint;
 135 };
 136 
 137 
 138 /*
 139  *      Default configurations
 140  *
 141  *      1       2 CPU ISA 82489DX
 142  *      2       2 CPU EISA 82489DX no IRQ 8 or timer chaining
 143  *      3       2 CPU EISA 82489DX
 144  *      4       2 CPU MCA 82489DX
 145  *      5       2 CPU ISA+PCI
 146  *      6       2 CPU EISA+PCI
 147  *      7       2 CPU MCA+PCI
 148  */
 149 
 150 /*
 151  *      Per process x86 parameters
 152  */
 153  
 154 struct cpuinfo_x86
 155 {
 156         char hard_math;
 157         char x86;
 158         char x86_model;
 159         char x86_mask;
 160         char x86_vendor_id[16];
 161         int  x86_capability;
 162         int  fdiv_bug;
 163         char wp_works_ok;
 164         char hlt_works_ok;
 165         unsigned long udelay_val;
 166 };
 167 
 168 
 169 extern struct cpuinfo_x86 cpu_data[NR_CPUS];
 170 
 171 /*
 172  *      Private routines/data
 173  */
 174  
 175 extern void smp_scan_config(unsigned long, unsigned long);
 176 extern unsigned long smp_alloc_memory(unsigned long mem_base);
 177 extern unsigned char *apic_reg;
 178 extern unsigned char *kernel_stacks[NR_CPUS];
 179 extern unsigned char boot_cpu_id;
 180 extern unsigned long cpu_present_map;
 181 extern void smp_invalidate(void);
 182 extern volatile unsigned long kernel_flag, kernel_counter;
 183 extern volatile unsigned char active_kernel_processor;
 184 extern void smp_message_irq(int cpl, struct pt_regs *regs);
 185 extern void smp_reschedule_irq(int cpl, struct pt_regs *regs);
 186 extern unsigned long ipi_count;
 187 extern void smp_invalidate_rcv(void);           /* Process an NMI */
 188 extern volatile unsigned long kernel_counter;
 189 extern volatile unsigned long syscall_count;
 190 
 191 /*
 192  *      General functions that each host system must provide.
 193  */
 194  
 195 extern void smp_callin(void);
 196 extern void smp_boot_cpus(void);
 197 extern void smp_store_cpu_info(int id);         /* Store per cpu info (like the initial udelay numbers */
 198 
 199 /*
 200  *      APIC handlers: Note according to the Intel specification update
 201  *      you should put reads between APIC writes.
 202  *      Intel Pentium processor specification update [11AP, pg 64]
 203  *              "Back to Back Assertions of HOLD May Cause Lost APIC Write Cycle"
 204  */
 205 
 206 extern __inline void apic_write(unsigned long reg, unsigned long v)
     /*  */
 207 {
 208         *((unsigned long *)(apic_reg+reg))=v;
 209 }
 210 
 211 extern __inline unsigned long apic_read(unsigned long reg)
     /*  */
 212 {
 213         return *((unsigned long *)(apic_reg+reg));
 214 }
 215 
 216 /*
 217  *      This function is needed by all SMP systems. It must _always_ be valid from the initial
 218  *      startup. This may require magic on some systems (in the i86 case we dig out the boot 
 219  *      cpu id from the config and set up a fake apic_reg pointer so that before we activate
 220  *      the apic we get the right answer). Hopefully other processors are more sensible 8)
 221  */
 222  
 223 extern __inline int smp_processor_id(void)
     /*  */
 224 {
 225         return GET_APIC_ID(apic_read(APIC_ID));
 226 }
 227 
 228 #endif /* !ASSEMBLY */
 229 
 230 #define NO_PROC_ID              0xFF            /* No processor magic marker */
 231 
 232 /*
 233  *      This magic constant controls our willingness to transfer
 234  *      a process across CPUs. Such a transfer incurs misses on the L1
 235  *      cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
 236  *      gut feeling is this will vary by board in value. For a board
 237  *      with seperate L2 cache it probably depends also on the RSS, and
 238  *      for a board with shared L2 cache it ought to decay fast as other
 239  *      processes are run.
 240  */
 241  
 242 #define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
 243 
 244 #endif
 245 #endif
/* */
root/include/asm-i386/smp.h

INCLUDED FROM

DEFINITIONS
