drivers/scsi/aic7xxx.c

/* */
This source file includes following definitions.
debug
debug_config
debug_scb
aic7xxx_setup
aic7xxx_loadseq
aic7xxx_delay
aic7xxx_poll_scb
aic7xxx_scb_timeout
aic7xxx_scb_untimeout
aic7xxx_scb_tsleep
rcs_version
aic7xxx_info
aic7xxx_length
aic7xxx_scsirate
aic7xxx_putscb
aic7xxx_putscb_dma
aic7xxx_getscb
aic7xxx_match_scb
aic7xxx_unbusy_target
aic7xxx_done
aic7xxx_add_waiting_scb
aic7xxx_abort_waiting_scb
aic7xxx_reset_device
aic7xxx_reset_current_bus
aic7xxx_reset_channel
aic7xxx_isr
aic7xxx_probe
read_2840_seeprom
read_seeprom
detect_maxscb
aic7xxx_register
aic7xxx_detect
aic7xxx_buildscb
aic7xxx_queue
aic7xxx_abort_scb
aic7xxx_abort
aic7xxx_reset
aic7xxx_biosparam
   1 /*+M*************************************************************************
   2  * Adaptec 274x/284x/294x device driver for Linux.
   3  *
   4  * Copyright (c) 1994 John Aycock
   5  *   The University of Calgary Department of Computer Science.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; see the file COPYING.  If not, write to
  19  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F
  22  * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA
  23  * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide,
  24  * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux,
  25  * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file
  26  * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual,
  27  * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the
  28  * ANSI SCSI-2 specification (draft 10c), ...
  29  *
  30  * ----------------------------------------------------------------
  31  *  Modified to include support for wide and twin bus adapters,
  32  *  DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes,
  33  *  and other rework of the code.
  34  *
  35  *  Parts of this driver are based on the FreeBSD driver by Justin
  36  *  T. Gibbs.
  37  *
  38  *  A Boot time option was also added for not resetting the scsi bus.
  39  *
  40  *    Form:  aic7xxx=extended,no_reset
  41  *
  42  *    -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95
  43  *
  44  *  $Id: aic7xxx.c,v 2.10 1995/11/10 10:49:14 deang Exp $
  45  *-M*************************************************************************/
  46 
  47 #ifdef MODULE
  48 #include <linux/module.h>
  49 #endif
  50 
  51 #include <stdarg.h>
  52 #include <asm/io.h>
  53 #include <linux/string.h>
  54 #include <linux/errno.h>
  55 #include <linux/kernel.h>
  56 #include <linux/ioport.h>
  57 #include <linux/bios32.h>
  58 #include <linux/delay.h>
  59 #include <linux/sched.h>
  60 #include <linux/pci.h>
  61 #include <linux/proc_fs.h>
  62 #include <linux/blk.h>
  63 #include "sd.h"
  64 #include "scsi.h"
  65 #include "hosts.h"
  66 #include "aic7xxx.h"
  67 #include <linux/stat.h>
  68 
  69 #include <linux/config.h>       /* for CONFIG_PCI */
  70 
  71 struct proc_dir_entry proc_scsi_aic7xxx = {
  72     PROC_SCSI_AIC7XXX, 7, "aic7xxx",
  73     S_IFDIR | S_IRUGO | S_IXUGO, 2
  74 };
  75 
  76 #define AIC7XXX_C_VERSION  "$Revision: 2.10 $"
  77 
  78 #define NUMBER(arr)     (sizeof(arr) / sizeof(arr[0]))
  79 #define MIN(a,b)        ((a < b) ? a : b)
  80 #define ALL_TARGETS -1
  81 #ifndef TRUE
  82 #  define TRUE 1
  83 #endif
  84 #ifndef FALSE
  85 #  define FALSE 0
  86 #endif
  87 
  88 /*
  89  * Defines for PCI bus support, testing twin bus support, DMAing of
  90  * SCBs, tagged queueing, commands (SCBs) per lun, and SCSI bus reset
  91  * delay time.
  92  *
  93  *   o PCI bus support - this has been implemented and working since
  94  *     the December 1, 1994 release of this driver. If you don't have
  95  *     a PCI bus and do not wish to configure your kernel with PCI
  96  *     support, then make sure this define is set to the cprrect
  97  *     define for PCI support (CONFIG_PCI) and configure your kernel
  98  *     without PCI support (make config).
  99  *
 100  *   o Twin bus support - this has been tested and does work.
 101  *
 102  *   o DMAing of SCBs - thanks to Kai Makisara, this now works.
 103  *     This define is now taken out and DMAing of SCBs is always
 104  *     performed (8/12/95 - DE).
 105  *
 106  *   o Tagged queueing - this driver is capable of tagged queueing
 107  *     but I am unsure as to how well the higher level driver implements
 108  *     tagged queueing. Therefore, the maximum commands per lun is
 109  *     set to 2. If you want to implement tagged queueing, ensure
 110  *     this define is not commented out.
 111  *
 112  *   o Sharing IRQs - allowed for sharing of IRQs. This will allow
 113  *     for multiple aic7xxx host adapters sharing the same IRQ, but
 114  *     not for sharing IRQs with other devices. The higher level
 115  *     PCI code and interrupt handling needs to be modified to
 116  *     support this.
 117  *
 118  *   o Commands per lun - If tagged queueing is enabled, then you
 119  *     may want to try increasing AIC7XXX_CMDS_PER_LUN to more
 120  *     than 2.  By default, we limit the SCBs per lun to 2 with
 121  *     or without tagged queueing enabled.  If tagged queueing is
 122  *     disabled, the sequencer will keep the 2nd SCB in the input
 123  *     queue until the first one completes - so it is OK to to have
 124  *     more than 1 SCB queued.  If tagged queueing is enabled, then
 125  *     the sequencer will attempt to send the 2nd SCB to the device
 126  *     while the first SCB is executing and the device is disconnected.
 127  *     For adapters limited to 4 SCBs, you may want to actually
 128  *     decrease the commands per lun to 1, if you often have more
 129  *     than 2 devices active at the same time.  This will allocate
 130  *     1 SCB for each device and ensure that there will always be
 131  *     a free SCB for up to 4 devices active at the same time.
 132  *
 133  *  Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95
 134  */
 135 
 136 /* Uncomment this for testing twin bus support. */
 137 #define AIC7XXX_TWIN_SUPPORT
 138 
 139 /* Uncomment this for tagged queueing. */
 140 /* #define AIC7XXX_TAGGED_QUEUEING */
 141 
 142 /* Uncomment this for allowing sharing of IRQs. */
 143 #define AIC7XXX_SHARE_IRQS
 144 
 145 /*
 146  * You can try raising me if tagged queueing is enabled, or lowering
 147  * me if you only have 4 SCBs.
 148  */
 149 #define AIC7XXX_CMDS_PER_LUN 2
 150 
 151 /* Set this to the delay in seconds after SCSI bus reset. */
 152 #define AIC7XXX_RESET_DELAY 15
 153 
 154 /*
 155  * Uncomment the following define for collection of SCSI transfer statistics
 156  * for the /proc filesystem.
 157  *
 158  * NOTE: This does affect performance since it has to maintain statistics.
 159  */
 160 /* #define AIC7XXX_PROC_STATS */
 161 
 162 /*
 163  * Define this to use polling rather than using kernel support for waking
 164  * up a waiting process.
 165  */
 166 #define AIC7XXX_POLL
 167 
 168 /*
 169  * Controller type and options
 170  */
 171 typedef enum {
 172   AIC_NONE,
 173   AIC_274x,    /* EISA aic7770 */
 174   AIC_284x,    /* VLB  aic7770 */
 175   AIC_7870,    /* PCI  aic7870/aic7871 motherboard or 294x */
 176   AIC_7850,    /* PCI  aic7850 */
 177   AIC_7872,    /* PCI  aic7870 on 394x */
 178   AIC_7880,    /* PCI  aic7880/aic7881 motherboard or 294x Ultra */
 179   AIC_7882,    /* PCI  aic7870 on 394x Ultra */
 180 } aha_type;
 181 
 182 typedef enum {
 183   AIC_SINGLE,  /* Single Channel */
 184   AIC_TWIN,    /* Twin Channel */
 185   AIC_WIDE     /* Wide Channel */
 186 } aha_bus_type;
 187 
 188 typedef enum {
 189   AIC_UNKNOWN,
 190   AIC_ENABLED,
 191   AIC_DISABLED
 192 } aha_status_type;
 193 
 194 typedef enum {
 195   LIST_HEAD,
 196   LIST_SECOND,
 197   LIST_TAIL
 198 } insert_type;
 199 
 200 /*
 201  * There should be a specific return value for this in scsi.h, but
 202  * it seems that most drivers ignore it.
 203  */
 204 #define DID_UNDERFLOW   DID_ERROR
 205 
 206 /*
 207  *  What we want to do is have the higher level scsi driver requeue
 208  *  the command to us. There is no specific driver status for this
 209  *  condition, but the higher level scsi driver will requeue the
 210  *  command on a DID_BUS_BUSY error.
 211  */
 212 #define DID_RETRY_COMMAND DID_BUS_BUSY
 213 
 214 /*
 215  * EISA/VL-bus stuff
 216  */
 217 #define MINSLOT         1
 218 #define MAXSLOT         15
 219 #define SLOTBASE(x)     ((x) << 12)
 220 #define MAXIRQ          15
 221 
 222 /*
 223  * Standard EISA Host ID regs  (Offset from slot base)
 224  */
 225 #define HID0(x)         ((x) + 0xC80)   /* 0,1: msb of ID2, 2-7: ID1      */
 226 #define HID1(x)         ((x) + 0xC81)   /* 0-4: ID3, 5-7: LSB ID2         */
 227 #define HID2(x)         ((x) + 0xC82)   /* product                        */
 228 #define HID3(x)         ((x) + 0xC83)   /* firmware revision              */
 229 
 230 /*
 231  * AIC-7770 I/O range to reserve for a card
 232  */
 233 #define MINREG(x)       ((x) + 0xC00ul)
 234 #define MAXREG(x)       ((x) + 0xCBFul)
 235 
 236 /* -------------------- AIC-7770 offset definitions ----------------------- */
 237 
 238 /*
 239  * SCSI Sequence Control (p. 3-11).
 240  * Each bit, when set starts a specific SCSI sequence on the bus
 241  */
 242 #define SCSISEQ(x)              ((x) + 0xC00ul)
 243 #define         TEMODEO         0x80
 244 #define         ENSELO          0x40
 245 #define         ENSELI          0x20
 246 #define         ENRSELI         0x10
 247 #define         ENAUTOATNO      0x08
 248 #define         ENAUTOATNI      0x04
 249 #define         ENAUTOATNP      0x02
 250 #define         SCSIRSTO        0x01
 251 
 252 
 253 /*
 254  * SCSI Transfer Control 0 Register (pp. 3-13).
 255  * Controls the SCSI module data path.
 256  */
 257 #define SXFRCTL0(x)             ((x) + 0xC01ul)
 258 #define         DFON            0x80
 259 #define         DFPEXP          0x40
 260 #define         ULTRAEN         0x20
 261 #define         CLRSTCNT        0x10
 262 #define         SPIOEN          0x08
 263 #define         SCAMEN          0x04
 264 #define         CLRCHN          0x02
 265 /*  UNUSED                      0x01 */
 266 
 267 /*
 268  * SCSI Transfer Control 1 Register (pp. 3-14,15).
 269  * Controls the SCSI module data path.
 270  */
 271 #define SXFRCTL1(x)             ((x) + 0xC02ul)
 272 #define         BITBUCKET       0x80
 273 #define         SWRAPEN         0x40
 274 #define         ENSPCHK         0x20
 275 #define         STIMESEL        0x18
 276 #define         ENSTIMER        0x04
 277 #define         ACTNEGEN        0x02
 278 #define         STPWEN          0x01            /* Powered Termination */
 279 
 280 /*
 281  * SCSI Control Signal Read Register (p. 3-15).
 282  * Reads the actual state of the SCSI bus pins
 283  */
 284 #define SCSISIGI(x)             ((x) + 0xC03ul)
 285 #define         CDI             0x80
 286 #define         IOI             0x40
 287 #define         MSGI            0x20
 288 #define         ATNI            0x10
 289 #define         SELI            0x08
 290 #define         BSYI            0x04
 291 #define         REQI            0x02
 292 #define         ACKI            0x01
 293 
 294 /*
 295  * SCSI Contol Signal Write Register (p. 3-16).
 296  * Writing to this register modifies the control signals on the bus. Only
 297  * those signals that are allowed in the current mode (Initiator/Target) are
 298  * asserted.
 299  */
 300 #define SCSISIGO(x)             ((x) + 0xC03ul)
 301 #define         CDO             0x80
 302 #define         IOO             0x40
 303 #define         MSGO            0x20
 304 #define         ATNO            0x10
 305 #define         SELO            0x08
 306 #define         BSYO            0x04
 307 #define         REQO            0x02
 308 #define         ACKO            0x01
 309 
 310 /*
 311  * SCSI Rate
 312  */
 313 #define SCSIRATE(x)             ((x) + 0xC04ul)
 314 #define WIDEXFER                0x80            /* Wide transfer control */
 315 #define SXFR                    0x70            /* Sync transfer rate */
 316 #define SOFS                    0x0F            /* Sync offset */
 317 
 318 /*
 319  * SCSI ID (p. 3-18).
 320  * Contains the ID of the board and the current target on the
 321  * selected channel
 322  */
 323 #define SCSIID(x)               ((x) + 0xC05ul)
 324 #define         TID             0xF0            /* Target ID mask */
 325 #define         OID             0x0F            /* Our ID mask */
 326 
 327 /*
 328  * SCSI Transfer Count (pp. 3-19,20)
 329  * These registers count down the number of bytes transfered
 330  * across the SCSI bus.  The counter is decremented only once
 331  * the data has been safely transfered.  SDONE in SSTAT0 is
 332  * set when STCNT goes to 0
 333  */
 334 #define STCNT(x)                ((x) + 0xC08ul)
 335 
 336 /*
 337  * SCSI Status 0 (p. 3-21)
 338  * Contains one set of SCSI Interrupt codes
 339  * These are most likely of interest to the sequencer
 340  */
 341 #define SSTAT0(x)               ((x) + 0xC0Bul)
 342 #define         TARGET          0x80            /* Board is a target */
 343 #define         SELDO           0x40            /* Selection Done */
 344 #define         SELDI           0x20            /* Board has been selected */
 345 #define         SELINGO         0x10            /* Selection In Progress */
 346 #define         SWRAP           0x08            /* 24bit counter wrap */
 347 #define         SDONE           0x04            /* STCNT = 0x000000 */
 348 #define         SPIORDY         0x02            /* SCSI PIO Ready */
 349 #define         DMADONE         0x01            /* DMA transfer completed */
 350 
 351 /*
 352  * Clear SCSI Interrupt 1 (p. 3-23)
 353  * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 354  */
 355 #define CLRSINT1(x)             ((x) + 0xC0Cul)
 356 #define         CLRSELTIMEO     0x80
 357 #define         CLRATNO         0x40
 358 #define         CLRSCSIRSTI     0x20
 359 /*  UNUSED                      0x10 */
 360 #define         CLRBUSFREE      0x08
 361 #define         CLRSCSIPERR     0x04
 362 #define         CLRPHASECHG     0x02
 363 #define         CLRREQINIT      0x01
 364 
 365 /*
 366  * SCSI Status 1 (p. 3-24)
 367  * These interrupt bits are of interest to the kernel driver
 368  */
 369 #define SSTAT1(x)               ((x) + 0xC0Cul)
 370 #define         SELTO           0x80
 371 #define         ATNTARG         0x40
 372 #define         SCSIRSTI        0x20
 373 #define         PHASEMIS        0x10
 374 #define         BUSFREE         0x08
 375 #define         SCSIPERR        0x04
 376 #define         PHASECHG        0x02
 377 #define         REQINIT         0x01
 378 
 379 /*
 380  * SCSI Interrrupt Mode 1 (pp. 3-28,29).
 381  * Set bits in this register enable the corresponding
 382  * interrupt source.
 383  */
 384 #define SIMODE1(x)              ((x) + 0xC11ul)
 385 #define         ENSELTIMO       0x80
 386 #define         ENATNTARG       0x40
 387 #define         ENSCSIRST       0x20
 388 #define         ENPHASEMIS      0x10
 389 #define         ENBUSFREE       0x08
 390 #define         ENSCSIPERR      0x04
 391 #define         ENPHASECHG      0x02
 392 #define         ENREQINIT       0x01
 393 
 394 /*
 395  * SCSI/Host Address (p. 3-30)
 396  * These registers hold the host address for the byte about to be
 397  * transfered on the SCSI bus.  They are counted up in the same
 398  * manner as STCNT is counted down.  SHADDR should always be used
 399  * to determine the address of the last byte transfered since HADDR
 400  * can be squewed by write ahead.
 401  */
 402 #define SHADDR(x)               ((x) + 0xC14ul)
 403 
 404 /*
 405  * Selection/Reselection ID (p. 3-31)
 406  * Upper four bits are the device id. The ONEBIT is set when the re/selecting
 407  * device did not set its own ID.
 408  */
 409 #define SELID(x)                ((x) + 0xC19ul)
 410 #define         SELID_MASK      0xF0
 411 #define         ONEBIT          0x08
 412 /*  UNUSED                      0x07 */
 413 
 414 /*
 415  * SCSI Block Control (p. 3-32)
 416  * Controls Bus type and channel selection. In a twin channel configuration
 417  * addresses 0x00-0x1E are gated to the appropriate channel based on this
 418  * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
 419  * on a wide bus.
 420  */
 421 #define SBLKCTL(x)              ((x) + 0xC1Ful)
 422 /*  UNUSED                      0xC0 */
 423 #define         DIAGLEDEN       0x80
 424 #define         DIAGLEDON       0x40
 425 #define         AUTOFLUSHDIS    0x20            /* used for Rev C check */
 426 /*  UNUSED                      0x10 */
 427 #define         SELBUS_MASK     0x0F
 428 #define         SELBUSB         0x08
 429 /*  UNUSED                      0x04 */
 430 #define         SELWIDE         0x02
 431 /*  UNUSED                      0x01 */
 432 #define         SELSINGLE       0x00
 433 
 434 /*
 435  * Sequencer Control (p. 3-33)
 436  * Error detection mode and speed configuration
 437  */
 438 #define SEQCTL(x)               ((x) + 0xC60ul)
 439 #define         PERRORDIS       0x80
 440 #define         PAUSEDIS        0x40
 441 #define         FAILDIS         0x20
 442 #define         FASTMODE        0x10
 443 #define         BRKADRINTEN     0x08
 444 #define         STEP            0x04
 445 #define         SEQRESET        0x02
 446 #define         LOADRAM         0x01
 447 
 448 /*
 449  * Sequencer RAM Data (p. 3-34)
 450  * Single byte window into the Scratch Ram area starting at the address
 451  * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
 452  * four bytes in sucessesion. The SEQADDRs will increment after the most
 453  * significant byte is written
 454  */
 455 #define SEQRAM(x)               ((x) + 0xC61ul)
 456 
 457 /*
 458  * Sequencer Address Registers (p. 3-35)
 459  * Only the first bit of SEQADDR1 holds addressing information
 460  */
 461 #define SEQADDR0(x)             ((x) + 0xC62ul)
 462 #define SEQADDR1(x)             ((x) + 0xC63ul)
 463 
 464 #define ACCUM(x)                ((x) + 0xC64ul)         /* accumulator */
 465 #define SINDEX(x)               ((x) + 0xC65ul)
 466 
 467 /*
 468  * Board Control (p. 3-43)
 469  */
 470 #define BCTL(x)                 ((x) + 0xC84ul)
 471 /*   RSVD                       0xF0 */
 472 #define         ACE             0x08    /* Support for external processors */
 473 /*   RSVD                       0x06 */
 474 #define         ENABLE          0x01
 475 
 476 /*
 477  * Bus On/Off Time (p. 3-44)
 478  */
 479 #define BUSTIME(x)              ((x) + 0xC85ul)
 480 #define         BOFF            0xF0
 481 #define         BON             0x0F
 482 
 483 /*
 484  * Bus Speed (p. 3-45)
 485  */
 486 #define BUSSPD(x)               ((x) + 0xC86ul)
 487 #define         DFTHRSH         0xC0
 488 #define         STBOFF          0x38
 489 #define         STBON           0x07
 490 
 491 /*
 492  * Host Control (p. 3-47) R/W
 493  * Overal host control of the device.
 494  */
 495 #define HCNTRL(x)               ((x) + 0xC87ul)
 496 /*    UNUSED                    0x80 */
 497 #define         POWRDN          0x40
 498 /*    UNUSED                    0x20 */
 499 #define         SWINT           0x10
 500 #define         IRQMS           0x08
 501 #define         PAUSE           0x04
 502 #define         INTEN           0x02
 503 #define         CHIPRST         0x01
 504 #define         REQ_PAUSE       IRQMS | INTEN | PAUSE
 505 #define         UNPAUSE_274X    IRQMS | INTEN
 506 #define         UNPAUSE_284X    INTEN
 507 #define         UNPAUSE_294X    IRQMS | INTEN
 508 
 509 /*
 510  * Host Address (p. 3-48)
 511  * This register contains the address of the byte about
 512  * to be transfered across the host bus.
 513  */
 514 #define HADDR(x)                ((x) + 0xC88ul)
 515 
 516 /*
 517  * SCB Pointer (p. 3-49)
 518  * Gate one of the four SCBs into the SCBARRAY window.
 519  */
 520 #define SCBPTR(x)               ((x) + 0xC90ul)
 521 
 522 /*
 523  * Interrupt Status (p. 3-50)
 524  * Status for system interrupts
 525  */
 526 #define INTSTAT(x)              ((x) + 0xC91ul)
 527 #define         SEQINT_MASK     0xF0            /* SEQINT Status Codes */
 528 #define                 BAD_PHASE       0x00
 529 #define                 SEND_REJECT     0x10
 530 #define                 NO_IDENT        0x20
 531 #define                 NO_MATCH        0x30
 532 #define                 MSG_SDTR        0x40
 533 #define                 MSG_WDTR        0x50
 534 #define                 MSG_REJECT      0x60
 535 #define                 BAD_STATUS      0x70
 536 #define                 RESIDUAL        0x80
 537 #define                 ABORT_TAG       0x90
 538 #define                 AWAITING_MSG    0xA0
 539 #define                 IMMEDDONE       0xB0
 540 #define         BRKADRINT 0x08
 541 #define         SCSIINT   0x04
 542 #define         CMDCMPLT  0x02
 543 #define         SEQINT    0x01
 544 #define         INT_PEND  (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
 545 
 546 /*
 547  * Hard Error (p. 3-53)
 548  * Reporting of catastrophic errors. You usually cannot recover from
 549  * these without a full board reset.
 550  */
 551 #define ERROR(x)                ((x) + 0xC92ul)
 552 /*    UNUSED                    0xF0 */
 553 #define         PARERR          0x08
 554 #define         ILLOPCODE       0x04
 555 #define         ILLSADDR        0x02
 556 #define         ILLHADDR        0x01
 557 
 558 /*
 559  * Clear Interrupt Status (p. 3-52)
 560  */
 561 #define CLRINT(x)               ((x) + 0xC92ul)
 562 #define         CLRBRKADRINT    0x08
 563 #define         CLRSCSIINT      0x04
 564 #define         CLRCMDINT       0x02
 565 #define         CLRSEQINT       0x01
 566 
 567 /*
 568  * SCB Auto Increment (p. 3-59)
 569  * Byte offset into the SCB Array and an optional bit to allow auto
 570  * incrementing of the address during download and upload operations
 571  */
 572 #define SCBCNT(x)               ((x) + 0xC9Aul)
 573 #define         SCBAUTO         0x80
 574 #define         SCBCNT_MASK     0x1F
 575 
 576 /*
 577  * Queue In FIFO (p. 3-60)
 578  * Input queue for queued SCBs (commands that the seqencer has yet to start)
 579  */
 580 #define QINFIFO(x)              ((x) + 0xC9Bul)
 581 
 582 /*
 583  * Queue In Count (p. 3-60)
 584  * Number of queued SCBs
 585  */
 586 #define QINCNT(x)               ((x) + 0xC9Cul)
 587 
 588 /*
 589  * Queue Out FIFO (p. 3-61)
 590  * Queue of SCBs that have completed and await the host
 591  */
 592 #define QOUTFIFO(x)             ((x) + 0xC9Dul)
 593 
 594 /*
 595  * Queue Out Count (p. 3-61)
 596  * Number of queued SCBs in the Out FIFO
 597  */
 598 #define QOUTCNT(x)              ((x) + 0xC9Eul)
 599 
 600 #define SCBARRAY(x)             ((x) + 0xCA0ul)
 601 
 602 /* ---------------- END AIC-7770 Register Definitions ----------------- */
 603 
 604 /* --------------------- AHA-2840-only definitions -------------------- */
 605 
 606 #define SEECTL_2840(x)          ((x) + 0xCC0ul)
 607 /*    UNUSED                    0xF8 */
 608 #define         CS_2840         0x04
 609 #define         CK_2840         0x02
 610 #define         DO_2840         0x01
 611 
 612 #define STATUS_2840(x)          ((x) + 0xCC1ul)
 613 #define         EEPROM_TF       0x80
 614 #define         BIOS_SEL        0x60
 615 #define         ADSEL           0x1E
 616 #define         DI_2840         0x01
 617 
 618 /* --------------------- AIC-7870-only definitions -------------------- */
 619 
 620 #define DSPCISTATUS(x)          ((x) + 0xC86ul)
 621 #define         DFTHRESH        0xC0
 622 
 623 /*
 624  * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 625  * Controls the reading and writing of an external serial 1-bit
 626  * EEPROM Device.  In order to access the serial EEPROM, you must
 627  * first set the SEEMS bit that generates a request to the memory
 628  * port for access to the serial EEPROM device.  When the memory
 629  * port is not busy servicing another request, it reconfigures
 630  * to allow access to the serial EEPROM.  When this happens, SEERDY
 631  * gets set high to verify that the memory port access has been
 632  * granted.  See aic7xxx_read_eprom for detailed information on
 633  * the protocol necessary to read the serial EEPROM.
 634  */
 635 #define SEECTL(x)               ((x) + 0xC1Eul)
 636 #define         EXTARBACK       0x80
 637 #define         EXTARBREQ       0x40
 638 #define         SEEMS           0x20
 639 #define         SEERDY          0x10
 640 #define         SEECS           0x08
 641 #define         SEECK           0x04
 642 #define         SEEDO           0x02
 643 #define         SEEDI           0x01
 644 
 645 #define DEVREVID                0x08ul
 646 
 647 #define DEVSTATUS               0x40ul
 648 #define         MPORTMODE       0x04    /* aic7870 only */
 649 #define         RAMPSM          0x02    /* aic7870 only */
 650 #define         VOLSENSE        0x01
 651 
 652 #define DEVCONFIG               0x41ul
 653 #define         SCBRAMSEL       0x80
 654 #define         MRDCEN          0x40
 655 #define         EXTSCBTIME      0x20    /* aic7870 only */
 656 #define         EXTSCBPEN       0x10    /* aic7870 only */
 657 #define         BERREN          0x08
 658 #define         DACEN           0x04
 659 #define         STPWLEVEL       0x02
 660 #define         DIFACTNEGEN     0x01    /* aic7870 only */
 661 
 662 /* Scratch RAM offset definitions */
 663 
 664 /* ---------------------- Scratch RAM Offsets ------------------------- */
 665 /* These offsets are either to values that are initialized by the board's
 666  * BIOS or are specified by the Linux sequencer code. If I can figure out
 667  * how to read the EISA configuration info at probe time, the cards could
 668  * be run without BIOS support installed
 669  */
 670 
 671 /*
 672  * 1 byte per target starting at this address for configuration values
 673  */
 674 #define HA_TARG_SCRATCH(x)      ((x) + 0xC20ul)
 675 
 676 /*
 677  * The sequencer will stick the first byte of any rejected message here so
 678  * we can see what is getting thrown away.
 679  */
 680 #define HA_REJBYTE(x)           ((x) + 0xC31ul)
 681 
 682 /*
 683  * Bit vector of targets that have disconnection disabled.
 684  */
 685 #define HA_DISC_DSB(x)          ((x) + 0xC32ul)
 686 
 687 /*
 688  * Length of pending message
 689  */
 690 #define HA_MSG_LEN(x)           ((x) + 0xC34ul)
 691 
 692 /*
 693  * Outgoing Message Body
 694  */
 695 #define HA_MSG_START(x)         ((x) + 0xC35ul)
 696 
 697 /*
 698  * These are offsets into the card's scratch ram. Some of the values are
 699  * specified in the AHA2742 technical reference manual and are initialized
 700  * by the BIOS at boot time.
 701  */
 702 #define HA_ARG_1(x)             ((x) + 0xC4Aul) /* sdtr <-> rate parameters */
 703 #define HA_RETURN_1(x)          ((x) + 0xC4Aul)
 704 #define         SEND_SENSE      0x80
 705 #define         SEND_SDTR       0x80
 706 #define         SEND_WDTR       0x80
 707 #define         SEND_REJ        0x40
 708 
 709 #define SG_COUNT(x)             ((x) + 0xC4Dul)
 710 #define SG_NEXT(x)              ((x) + 0xC4Eul)
 711 #define HA_SIGSTATE(x)          ((x) + 0xC4Bul) /* value in SCSISIGO */
 712 #define HA_SCBCOUNT(x)          ((x) + 0xC52ul) /* number of hardware SCBs */
 713 
 714 #define HA_FLAGS(x)             ((x) + 0xC53ul) /* TWIN and WIDE bus flags */
 715 #define         SINGLE_BUS      0x00
 716 #define         TWIN_BUS        0x01
 717 #define         WIDE_BUS        0x02
 718 #define         ACTIVE_MSG      0x20
 719 #define         IDENTIFY_SEEN   0x40
 720 #define         RESELECTING     0x80
 721 
 722 #define HA_ACTIVE0(x)           ((x) + 0xC54ul) /* Active bits; targets 0-7 */
 723 #define HA_ACTIVE1(x)           ((x) + 0xC55ul) /* Active bits; targets 8-15 */
 724 #define SAVED_TCL(x)            ((x) + 0xC56ul) /* Saved target, channel, LUN */
 725 #define WAITING_SCBH(x)         ((x) + 0xC57ul) /* Head of disconnected targets list. */
 726 #define WAITING_SCBT(x)         ((x) + 0xC58ul) /* Tail of disconnected targets list. */
 727 
 728 #define HA_SCSICONF(x)          ((x) + 0xC5Aul) /* SCSI config register */
 729 #define HA_INTDEF(x)            ((x) + 0xC5Cul) /* interrupt def'n register */
 730 #define HA_HOSTCONF(x)          ((x) + 0xC5Dul) /* host config def'n register */
 731 
 732 #define HA_274_BIOSCTRL(x)      ((x) + 0xC5Ful) /* BIOS enabled for 274x */
 733 #define BIOSMODE                0x30
 734 #define BIOSDISABLED            0x30
 735 
 736 #define MSG_ABORT               0x06
 737 #define MSG_BUS_DEVICE_RESET    0x0C
 738 #define BUS_8_BIT               0x00
 739 #define BUS_16_BIT              0x01
 740 #define BUS_32_BIT              0x02
 741 
 742 
 743 /*
 744  *
 745  * Define the format of the SEEPROM registers (16 bits).
 746  *
 747  */
 748 struct seeprom_config {
 749 
 750 /*
 751  * SCSI ID Configuration Flags
 752  */
 753 #define CFXFER          0x0007          /* synchronous transfer rate */
 754 #define CFSYNCH         0x0008          /* enable synchronous transfer */
 755 #define CFDISC          0x0010          /* enable disconnection */
 756 #define CFWIDEB         0x0020          /* wide bus device */
 757 /* UNUSED               0x00C0 */
 758 #define CFSTART         0x0100          /* send start unit SCSI command */
 759 #define CFINCBIOS       0x0200          /* include in BIOS scan */
 760 #define CFRNFOUND       0x0400          /* report even if not found */
 761 /* UNUSED               0xF800 */
 762   unsigned short device_flags[16];      /* words 0-15 */
 763 
 764 /*
 765  * BIOS Control Bits
 766  */
 767 #define CFSUPREM        0x0001          /* support all removeable drives */
 768 #define CFSUPREMB       0x0002          /* support removeable drives for boot only */
 769 #define CFBIOSEN        0x0004          /* BIOS enabled */
 770 /* UNUSED               0x0008 */
 771 #define CFSM2DRV        0x0010          /* support more than two drives */
 772 /* UNUSED               0x0060 */
 773 #define CFEXTEND        0x0080          /* extended translation enabled */
 774 /* UNUSED               0xFF00 */
 775   unsigned short bios_control;          /* word 16 */
 776 
 777 /*
 778  * Host Adapter Control Bits
 779  */
 780 /* UNUSED               0x0001 */
 781 #define CFULTRAEN       0x0002          /* Ultra SCSI speed enable (Ultra cards) */
 782 #define CFSTERM         0x0004          /* SCSI low byte termination (non-wide cards) */
 783 #define CFWSTERM        0x0008          /* SCSI high byte termination (wide card) */
 784 #define CFSPARITY       0x0010          /* SCSI parity */
 785 /* UNUSED               0x0020 */
 786 #define CFRESETB        0x0040          /* reset SCSI bus at IC initialization */
 787 /* UNUSED               0xFF80 */
 788   unsigned short adapter_control;       /* word 17 */
 789 
 790 /*
 791  * Bus Release, Host Adapter ID
 792  */
 793 #define CFSCSIID        0x000F          /* host adapter SCSI ID */
 794 /* UNUSED               0x00F0 */
 795 #define CFBRTIME        0xFF00          /* bus release time */
 796   unsigned short brtime_id;             /* word 18 */
 797 
 798 /*
 799  * Maximum targets
 800  */
 801 #define CFMAXTARG       0x00FF  /* maximum targets */
 802 /* UNUSED               0xFF00 */
 803   unsigned short max_targets;           /* word 19 */
 804 
 805   unsigned short res_1[11];             /* words 20-30 */
 806   unsigned short checksum;              /* word 31 */
 807 
 808 };
 809 
 810 
 811 #define AIC7XXX_DEBUG
 812 
 813 /*
 814  * Pause the sequencer and wait for it to actually stop - this
 815  * is important since the sequencer can disable pausing for critical
 816  * sections.
 817  */
 818 #define PAUSE_SEQUENCER(p) \
 819   outb(p->pause, HCNTRL(p->base));                      \
 820   while ((inb(HCNTRL(p->base)) & PAUSE) == 0)           \
 821     ;                                                   \
 822 
 823 /*
 824  * Unpause the sequencer. Unremarkable, yet done often enough to
 825  * warrant an easy way to do it.
 826  */
 827 #define UNPAUSE_SEQUENCER(p) \
 828   outb(p->unpause, HCNTRL(p->base))
 829 
 830 /*
 831  * Restart the sequencer program from address zero
 832  */
 833 #define RESTART_SEQUENCER(p) \
 834   do {                                                  \
 835     outb(SEQRESET | FASTMODE, SEQCTL(p->base));         \
 836   } while (inb(SEQADDR0(p->base)) != 0 &&               \
 837            inb(SEQADDR1(p->base)) != 0);                \
 838   UNPAUSE_SEQUENCER(p);
 839 
 840 /*
 841  * If an error occurs during a data transfer phase, run the comand
 842  * to completion - it's easier that way - making a note of the error
 843  * condition in this location. This then will modify a DID_OK status
 844  * into an appropriate error for the higher-level SCSI code.
 845  */
 846 #define aic7xxx_error(cmd)      ((cmd)->SCp.Status)
 847 
 848 /*
 849  * Keep track of the targets returned status.
 850  */
 851 #define aic7xxx_status(cmd)     ((cmd)->SCp.sent_command)
 852 
 853 /*
 854  * The position of the SCSI commands scb within the scb array.
 855  */
 856 #define aic7xxx_position(cmd)   ((cmd)->SCp.have_data_in)
 857 
 858 /*
 859  * Since the sequencer code DMAs the scatter-gather structures
 860  * directly from memory, we use this macro to assert that the
 861  * kernel structure hasn't changed.
 862  */
 863 #define SG_STRUCT_CHECK(sg) \
 864   ((char *) &(sg).address - (char *) &(sg) != 0 ||  \
 865    (char *) &(sg).length  - (char *) &(sg) != 8 ||  \
 866    sizeof((sg).address) != 4 ||                   \
 867    sizeof((sg).length)  != 4 ||                   \
 868    sizeof(sg)           != 12)
 869 
 870 /*
 871  * "Static" structures. Note that these are NOT initialized
 872  * to zero inside the kernel - we have to initialize them all
 873  * explicitly.
 874  *
 875  * We support multiple adapter cards per interrupt, but keep a
 876  * linked list of Scsi_Host structures for each IRQ.  On an interrupt,
 877  * use the IRQ as an index into aic7xxx_boards[] to locate the card
 878  * information.
 879  */
 880 static struct Scsi_Host *aic7xxx_boards[MAXIRQ + 1];
 881 
 882 /*
 883  * When we detect and register the card, it is possible to
 884  * have the card raise a spurious interrupt.  Because we need
 885  * to support multiple cards, we cannot tell which card caused
 886  * the spurious interrupt.  And, we might not even have added
 887  * the card info to the linked list at the time the spurious
 888  * interrupt gets raised.  This variable is suppose to keep track
 889  * of when we are registering a card and how many spurious
 890  * interrupts we have encountered.
 891  *
 892  *   0 - do not allow spurious interrupts.
 893  *   1 - allow 1 spurious interrupt
 894  *   2 - have 1 spurious interrupt, do not allow any more.
 895  *
 896  * I've made it an integer instead of a boolean in case we
 897  * want to allow more than one spurious interrupt for debugging
 898  * purposes.  Otherwise, it could just go from true to false to
 899  * true (or something like that).
 900  *
 901  * When the driver detects the cards, we'll set the count to 1
 902  * for each card detection and registration.  After the registration
 903  * of a card completes, we'll set the count back to 0.  So far, it
 904  * seems to be enough to allow a spurious interrupt only during
 905  * card registration; if a spurious interrupt is going to occur,
 906  * this is where it happens.
 907  *
 908  * We should be able to find a way to avoid getting the spurious
 909  * interrupt.  But until we do, we have to keep this ugly code.
 910  */
 911 static int aic7xxx_spurious_count;
 912 
 913 /*
 914  * The driver keeps up to four scb structures per card in memory. Only the
 915  * first 26 bytes of the structure are valid for the hardware, the rest used
 916  * for driver level bookeeping.
 917  */
 918 #define SCB_DOWNLOAD_SIZE       26      /* amount to actually download */
 919 #define SCB_UPLOAD_SIZE         26      /* amount to actually upload */
 920 
 921 struct aic7xxx_scb {
 922 /* ------------    Begin hardware supported fields    ---------------- */
 923 /*1 */  unsigned char control;
 924 #define SCB_NEEDWDTR 0x80                       /* Initiate Wide Negotiation */
 925 #define SCB_DISCENB  0x40                       /* Disconnection Enable */
 926 #define SCB_TE       0x20                       /* Tag enable */
 927 #define SCB_NEEDSDTR 0x10                       /* Initiate Sync Negotiation */
 928 #define SCB_NEEDDMA  0x08                       /* Refresh SCB from host ram */
 929 #define SCB_DIS      0x04
 930 #define SCB_TAG_TYPE 0x03
 931 #define         SIMPLE_QUEUE    0x00
 932 #define         HEAD_QUEUE      0x01
 933 #define         OR_QUEUE        0x02
 934 /*              ILLEGAL      0x03 */
 935 /*2 */  unsigned char target_channel_lun;       /* 4/1/3 bits */
 936 /*3 */  unsigned char SG_segment_count;
 937 /*7 */  unsigned char SG_list_pointer[4] __attribute__ ((packed));
 938 /*11*/  unsigned char SCSI_cmd_pointer[4] __attribute__ ((packed));
 939 /*12*/  unsigned char SCSI_cmd_length;
 940 /*14*/  unsigned char RESERVED[2];              /* must be zero */
 941 /*15*/  unsigned char target_status;
 942 /*18*/  unsigned char residual_data_count[3];
 943 /*19*/  unsigned char residual_SG_segment_count;
 944 /*23*/  unsigned char data_pointer[4] __attribute__ ((packed));
 945 /*26*/  unsigned char data_count[3];
 946 /*30*/  unsigned char host_scb[4] __attribute__ ((packed));
 947 /*31*/  u_char next_waiting;            /* Used to thread SCBs awaiting selection. */
 948 #define SCB_LIST_NULL 0xFF              /* SCB list equivelent to NULL */
 949 #if 0
 950         /*
 951          *  No real point in transferring this to the
 952          *  SCB registers.
 953          */
 954         unsigned char RESERVED[1];
 955 #endif
 956 
 957         /*-----------------end of hardware supported fields----------------*/
 958         struct aic7xxx_scb *next;       /* next ptr when in free list */
 959         Scsi_Cmnd          *cmd;        /* Scsi_Cmnd for this scb */
 960 #define SCB_FREE               0x00
 961 #define SCB_ACTIVE             0x01
 962 #define SCB_ABORTED            0x02
 963 #define SCB_DEVICE_RESET       0x04
 964 #define SCB_IMMED              0x08
 965 #define SCB_SENSE              0x10
 966         int                 state;          /* current state of scb */
 967         unsigned int        position;       /* Position in scb array */
 968         struct scatterlist  sg;
 969         struct scatterlist  sense_sg;
 970         unsigned char       sense_cmd[6];   /* Allocate 6 characters for sense command */
 971 #define TIMER_ENABLED           0x01
 972 #define TIMER_EXPIRED           0x02
 973 #define TIMED_CMD_DONE          0x04
 974         volatile unsigned char timer_status;
 975 #ifndef AIC7XXX_POLL
 976         struct wait_queue   *waiting;       /* wait queue for device reset command */
 977         struct wait_queue   waitq;          /* waiting points to this */
 978         struct timer_list   timer;          /* timeout for device reset command */
 979 #endif
 980 };
 981 
 982 typedef void (*timeout_fn)(unsigned long);
 983 
 984 static struct {
 985   unsigned char errno;
 986   const char *errmesg;
 987 } hard_error[] = {
 988   { ILLHADDR,  "Illegal Host Access" },
 989   { ILLSADDR,  "Illegal Sequencer Address referrenced" },
 990   { ILLOPCODE, "Illegal Opcode in sequencer program" },
 991   { PARERR,    "Sequencer Ram Parity Error" }
 992 };
 993 
 994 static unsigned char
 995 generic_sense[] = { REQUEST_SENSE, 0, 0, 0, 255, 0 };
 996 
 997 /*
 998  * The maximum number of SCBs we could have for ANY type
 999  * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE
1000  * SEQUENCER CODE IF THIS IS MODIFIED!
1001  */
1002 #define AIC7XXX_MAXSCB  255
1003 
1004 /*
1005  * Define a structure used for each host adapter, only one per IRQ.
1006  */
1007 struct aic7xxx_host {
1008   int                      base;             /* card base address */
1009   int                      maxscb;           /* hardware SCBs */
1010   int                      numscb;           /* current number of scbs */
1011   int                      extended;         /* extended xlate? */
1012   aha_type                 type;             /* card type */
1013   int                      ultra_enabled;    /* Ultra SCSI speed enabled */
1014   int                      chan_num;         /* for 3940/3985, channel number */
1015   aha_bus_type             bus_type;         /* normal/twin/wide bus */
1016   unsigned char            a_scanned;        /* 0 not scanned, 1 scanned */
1017   unsigned char            b_scanned;        /* 0 not scanned, 1 scanned */
1018   unsigned int             isr_count;        /* Interrupt count */
1019   volatile unsigned char   unpause;          /* unpause value for HCNTRL */
1020   volatile unsigned char   pause;            /* pause value for HCNTRL */
1021   volatile unsigned short  needsdtr_copy;    /* default config */
1022   volatile unsigned short  needsdtr;
1023   volatile unsigned short  sdtr_pending;
1024   volatile unsigned short  needwdtr_copy;    /* default config */
1025   volatile unsigned short  needwdtr;
1026   volatile unsigned short  wdtr_pending;
1027   volatile unsigned short  discenable;       /* Targets allowed to disconnect */
1028   struct seeprom_config    seeprom;
1029   int                      have_seeprom;
1030   struct Scsi_Host        *next;             /* allow for multiple IRQs */
1031   struct aic7xxx_scb       scb_array[AIC7XXX_MAXSCB];  /* active commands */
1032   struct aic7xxx_scb      *free_scb;         /* list of free SCBs */
1033 #ifdef AIC7XXX_PROC_STATS
1034   /*
1035    * Statistics Kept:
1036    *
1037    * Total Xfers (count for each command that has a data xfer),
1038    * broken down further by reads && writes.
1039    *
1040    * Binned sizes, writes && reads:
1041    *    < 512, 512, 1-2K, 2-4K, 4-8K, 8-16K, 16-32K, 32-64K, 64K-128K, > 128K
1042    *
1043    * Total amounts read/written above 512 bytes (amts under ignored)
1044    */
1045   struct aic7xxx_xferstats {
1046     long xfers;                              /* total xfer count */
1047     long w_total;                            /* total writes */
1048     long w_total512;                         /* 512 byte blocks written */
1049     long w_bins[10];                         /* binned write */
1050     long r_total;                            /* total reads */
1051     long r_total512;                         /* 512 byte blocks read */
1052     long r_bins[10];                         /* binned reads */
1053   } stats[2][16][8];                         /* channel, target, lun */
1054 #endif /* AIC7XXX_PROC_STATS */
1055 };
1056 
1057 struct aic7xxx_host_config {
1058   int              irq;        /* IRQ number */
1059   int              base;       /* I/O base */
1060   int              maxscb;     /* hardware SCBs */
1061   int              unpause;    /* unpause value for HCNTRL */
1062   int              pause;      /* pause value for HCNTRL */
1063   int              scsi_id;    /* host SCSI ID */
1064   int              scsi_id_b;  /* host SCSI ID B channel for twin cards */
1065   int              extended;   /* extended xlate? */
1066   int              busrtime;   /* bus release time */
1067   int              walk_scbs;  /* external SCB RAM detected; walk the scb array */
1068   aha_type         type;       /* card type */
1069   int              ultra_enabled;    /* Ultra SCSI speed enabled */
1070   int              chan_num;   /* for 3940/3985, channel number */
1071   aha_bus_type     bus_type;   /* normal/twin/wide bus */
1072   aha_status_type  parity;     /* bus parity enabled/disabled */
1073   aha_status_type  low_term;   /* bus termination low byte */
1074   aha_status_type  high_term;  /* bus termination high byte (wide cards only) */
1075 };
1076 
1077 /*
1078  * Valid SCSIRATE values. (p. 3-17)
1079  * Provides a mapping of tranfer periods in ns to the proper value to
1080  * stick in the scsiscfr reg to use that transfer rate.
1081  */
1082 static struct {
1083   short period;
1084   /* Rates in Ultra mode have bit 8 of sxfr set */
1085 #define         ULTRA_SXFR 0x100
1086   short rate;
1087   const char *english;
1088 } aic7xxx_syncrates[] = {
1089   {  50,  0x100,  "20.0" },
1090   {  62,  0x110,  "16.0" },
1091   {  75,  0x120,  "13.4" },
1092   { 100,  0x140,  "10.0" },
1093   { 100,  0x000,  "10.0" },
1094   { 125,  0x010,  "8.0"  },
1095   { 150,  0x020,  "6.67" },
1096   { 175,  0x030,  "5.7"  },
1097   { 200,  0x040,  "5.0"  },
1098   { 225,  0x050,  "4.4"  },
1099   { 250,  0x060,  "4.0"  },
1100   { 275,  0x070,  "3.6"  }
1101 };
1102 
1103 static int num_aic7xxx_syncrates =
1104     sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
1105 
1106 static int number_of_3940s = 0;
1107 
1108 #ifdef AIC7XXX_DEBUG
1109 
1110 static void
1111 debug(const char *fmt, ...)
     /*  */
1112 {
1113   va_list ap;
1114   char buf[256];
1115 
1116   va_start(ap, fmt);
1117   vsprintf(buf, fmt, ap);
1118   printk(buf);
1119   va_end(ap);
1120 }
1121 
1122 static void
1123 debug_config(struct aic7xxx_host_config *p)
     /*  */
1124 {
1125   int host_conf, scsi_conf;
1126   unsigned char brelease;
1127   unsigned char dfthresh;
1128 
1129   static int DFT[] = { 0, 50, 75, 100 };
1130   static int SST[] = { 256, 128, 64, 32 };
1131   static const char *BUSW[] = { "", "-TWIN", "-WIDE" };
1132 
1133   host_conf = inb(HA_HOSTCONF(p->base));
1134   scsi_conf = inb(HA_SCSICONF(p->base));
1135 
1136   /*
1137    * The 7870 gets the bus release time and data FIFO threshold
1138    * from the serial EEPROM (stored in the config structure) and
1139    * scsi_conf register respectively.  The 7770 gets the bus
1140    * release time and data FIFO threshold from the scsi_conf and
1141    * host_conf registers respectively.
1142    */
1143   if ((p->type == AIC_274x) || (p->type == AIC_284x))
1144   {
1145     dfthresh = (host_conf >> 6);
1146   }
1147   else
1148   {
1149     dfthresh = (scsi_conf >> 6);
1150   }
1151 
1152   brelease = p->busrtime;
1153   if (brelease == 0)
1154   {
1155     brelease = 2;
1156   }
1157 
1158   switch (p->type)
1159   {
1160     case AIC_274x:
1161       printk("AIC7770%s AT EISA SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
1162       break;
1163 
1164     case AIC_284x:
1165       printk("AIC7770%s AT VLB SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
1166       break;
1167 
1168     case AIC_7870:
1169       printk("AIC7870/7871%s (PCI-bus):\n", BUSW[p->bus_type]);
1170       break;
1171 
1172     case AIC_7850:
1173       printk("AIC7850%s (PCI-bus):\n", BUSW[p->bus_type]);
1174       break;
1175 
1176     case AIC_7872:
1177       printk("AIC7872%s (PCI-bus):\n", BUSW[p->bus_type]);
1178       break;
1179 
1180     case AIC_7880:
1181       printk("AIC7880/7881%s (PCI-bus):\n", BUSW[p->bus_type]);
1182       break;
1183 
1184     case AIC_7882:
1185       printk("AIC7882%s (PCI-bus):\n", BUSW[p->bus_type]);
1186       break;
1187 
1188     default:
1189       panic("aic7xxx debug_config: internal error\n");
1190   }
1191 
1192   printk("    irq %d\n"
1193          "    bus release time %d bclks\n"
1194          "    data fifo threshold %d%%\n",
1195          p->irq,
1196          brelease,
1197          DFT[dfthresh]);
1198 
1199   printk("    SCSI CHANNEL A:\n"
1200          "        scsi id %d\n"
1201          "        scsi selection timeout %d ms\n"
1202          "        scsi bus reset at power-on %sabled\n",
1203          scsi_conf & 0x07,
1204          SST[(scsi_conf >> 3) & 0x03],
1205          (scsi_conf & 0x40) ? "en" : "dis");
1206 
1207   if (((p->type == AIC_274x) || (p->type == AIC_284x)) && p->parity == AIC_UNKNOWN)
1208   {
1209     /*
1210      * Set the parity for 7770 based cards.
1211      */
1212     p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
1213   }
1214   if (p->parity != AIC_UNKNOWN)
1215   {
1216     printk("        scsi bus parity %sabled\n",
1217            (p->parity == AIC_ENABLED) ? "en" : "dis");
1218   }
1219 
1220   if (p->type == AIC_274x)
1221   {
1222     p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
1223   }
1224   if (p->low_term != AIC_UNKNOWN)
1225   {
1226     printk("        scsi bus termination (low byte) %sabled\n",
1227           (p->low_term == AIC_ENABLED) ? "en" : "dis");
1228   }
1229   if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1230   {
1231     printk("        scsi bus termination (high byte) %sabled\n",
1232           (p->high_term == AIC_ENABLED) ? "en" : "dis");
1233   }
1234 }
1235 
1236 #if 0
1237 static void
1238 debug_scb(struct aic7xxx_scb *scb)
     /*  */
1239 {
1240   printk("control 0x%x, tcl 0x%x, sg_count %d, sg_ptr 0x%x, cmdp 0x%x, cmdlen %d\n",
1241          scb->control, scb->target_channel_lun, scb->SG_segment_count,
1242          (scb->SG_list_pointer[3] << 24) | (scb->SG_list_pointer[2] << 16) |
1243          (scb->SG_list_pointer[1] << 8) | scb->SG_list_pointer[0],
1244          (scb->SCSI_cmd_pointer[3] << 24) | (scb->SCSI_cmd_pointer[2] << 16) |
1245          (scb->SCSI_cmd_pointer[1] << 8) | scb->SCSI_cmd_pointer[0],
1246          scb->SCSI_cmd_length);
1247   printk("reserved 0x%x, target status 0x%x, resid SG count %d, resid data count %d\n",
1248          (scb->RESERVED[1] << 8) | scb->RESERVED[0], scb->target_status,
1249          scb->residual_SG_segment_count, (scb->residual_data_count[2] << 16) |
1250          (scb->residual_data_count[1] << 8) | scb->residual_data_count[0]);
1251   printk("data ptr 0x%x, data count %d, host scb 0x%x, next waiting %d\n",
1252          (scb->data_pointer[3] << 24) | (scb->data_pointer[2] << 16) |
1253          (scb->data_pointer[1] << 8) | scb->data_pointer[0],
1254          (scb->data_count[2] << 16) | (scb->data_count[1] << 8) | scb->data_count[0],
1255          (unsigned int) scb->host_scb, scb->next_waiting);
1256   printk("next ptr 0x%lx, Scsi Cmnd 0x%lx, state 0x%x, position %d\n",
1257          (unsigned long) scb->next, (unsigned long) scb->cmd, scb->state,
1258          scb->position);
1259 }
1260 #endif
1261 
1262 #else
1263 #  define debug(fmt, args...)
1264 #  define debug_config(x)
1265 #  define debug_scb(x)
1266 #endif AIC7XXX_DEBUG
1267 
1268 /*
1269  * XXX - these options apply unilaterally to _all_ 274x/284x/294x
1270  *       cards in the system. This should be fixed, but then,
1271  *       does anyone really have more than one in a machine?
1272  */
1273 static unsigned int aic7xxx_extended = 0;    /* extended translation on? */
1274 static unsigned int aic7xxx_no_reset = 0;    /* no resetting of SCSI bus */
1275 
1276 /*+F*************************************************************************
1277  * Function:
1278  *   aic7xxx_setup
1279  *
1280  * Description:
1281  *   Handle Linux boot parameters. This routine allows for assigning a value
1282  *   to a parameter with a ':' between the parameter and the value.
1283  *   ie. aic7xxx=unpause:0x0A,extended
1284  *-F*************************************************************************/
1285 void
1286 aic7xxx_setup(char *s, int *dummy)
     /*  */
1287 {
1288   int   i, n;
1289   char *p;
1290 
1291   static struct {
1292     const char *name;
1293     unsigned int *flag;
1294   } options[] = {
1295     { "extended",    &aic7xxx_extended },
1296     { "no_reset",    &aic7xxx_no_reset },
1297     { NULL,          NULL }
1298   };
1299 
1300   for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1301   {
1302     for (i = 0; options[i].name; i++)
1303     {
1304       n = strlen(options[i].name);
1305       if (!strncmp(options[i].name, p, n))
1306       {
1307         if (p[n] == ':')
1308         {
1309           *(options[i].flag) = simple_strtoul(p + n + 1, NULL, 0);
1310         }
1311         else
1312         {
1313           *(options[i].flag) = !0;
1314         }
1315       }
1316     }
1317   }
1318 }
1319 
1320 /*+F*************************************************************************
1321  * Function:
1322  *   aic7xxx_loadseq
1323  *
1324  * Description:
1325  *   Load the sequencer code into the controller memory.
1326  *-F*************************************************************************/
1327 static void
1328 aic7xxx_loadseq(int base)
     /*  */
1329 {
1330   static unsigned char seqprog[] = {
1331     /*
1332      * Each sequencer instruction is 29 bits
1333      * long (fill in the excess with zeroes)
1334      * and has to be loaded from least -> most
1335      * significant byte, so this table has the
1336      * byte ordering reversed.
1337      */
1338 #   include "aic7xxx_seq.h"
1339   };
1340 
1341   /*
1342    * When the AIC-7770 is paused (as on chip reset), the
1343    * sequencer address can be altered and a sequencer
1344    * program can be loaded by writing it, byte by byte, to
1345    * the sequencer RAM port - the Adaptec documentation
1346    * recommends using REP OUTSB to do this, hence the inline
1347    * assembly. Since the address autoincrements as we load
1348    * the program, reset it back to zero afterward. Disable
1349    * sequencer RAM parity error detection while loading, and
1350    * make sure the LOADRAM bit is enabled for loading.
1351    */
1352   outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1353 
1354   asm volatile("cld\n\t"
1355                "rep\n\t"
1356                "outsb"
1357                : /* no output */
1358                :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1359                :"si", "cx", "dx");
1360 
1361   /*
1362    * WARNING!  This is a magic sequence!  After extensive
1363    * experimentation, it seems that you MUST turn off the
1364    * LOADRAM bit before you play with SEQADDR again, else
1365    * you will end up with parity errors being flagged on
1366    * your sequencer program. (You would also think that
1367    * turning off LOADRAM and setting SEQRESET to reset the
1368    * address to zero would work, but you need to do it twice
1369    * for it to take effect on the address. Timing problem?)
1370    */
1371   do {
1372     /*
1373      * Actually, reset it until
1374      * the address shows up as
1375      * zero just to be safe..
1376      */
1377     outb(SEQRESET | FASTMODE, SEQCTL(base));
1378   } while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1379 }
1380 
1381 /*+F*************************************************************************
1382  * Function:
1383  *   aic7xxx_delay
1384  *
1385  * Description:
1386  *   Delay for specified amount of time.
1387  *-F*************************************************************************/
1388 static void
1389 aic7xxx_delay(int seconds)
     /*  */
1390 {
1391   unsigned long i;
1392 
1393   i = jiffies + (seconds * HZ);  /* compute time to stop */
1394 
1395   while (jiffies < i)
1396   {
1397     ;  /* Do nothing! */
1398   }
1399 }
1400 
1401 #ifdef AIC7XXX_POLL
1402 /*+F*************************************************************************
1403  * Function:
1404  *   aic7xxx_poll_scb
1405  *
1406  * Description:
1407  *   Function to poll for command completion when in aborting an SCB.
1408  *-F*************************************************************************/
1409 static void
1410 aic7xxx_poll_scb(struct aic7xxx_host *p,
     /*  */
1411                  struct aic7xxx_scb  *scb,
1412                  unsigned long       timeout_ticks)
1413 {
1414   unsigned long timer_expiration = jiffies + timeout_ticks;
1415 
1416   while ((jiffies < timer_expiration) && !(scb->timer_status & TIMED_CMD_DONE))
1417   {
1418     udelay(1000);  /* delay for 1 msec. */
1419   }
1420 }
1421 
1422 #else
1423 /*+F*************************************************************************
1424  * Function:
1425  *   aic7xxx_scb_timeout
1426  *
1427  * Description:
1428  *   Called when a SCB reset command times out.  The input is actually
1429  *   a pointer to the SCB.
1430  *-F*************************************************************************/
1431 static void
1432 aic7xxx_scb_timeout(unsigned long data)
     /*  */
1433 {
1434   struct aic7xxx_scb *scb = (struct aic7xxx_scb *) data;
1435 
1436   scb->timer_status |= TIMER_EXPIRED;
1437   wake_up(&(scb->waiting));
1438 }
1439 
1440 /*+F*************************************************************************
1441  * Function:
1442  *   aic7xxx_scb_untimeout
1443  *
1444  * Description:
1445  *   This function clears the timeout and wakes up a waiting SCB.
1446  *-F*************************************************************************/
1447 static void
1448 aic7xxx_scb_untimeout(struct aic7xxx_scb *scb)
     /*  */
1449 {
1450   if (scb->timer_status & TIMER_ENABLED)
1451   {
1452     scb->timer_status = TIMED_CMD_DONE;
1453     wake_up(&(scb->waiting));
1454   }
1455 }
1456 #endif
1457 
1458 /*+F*************************************************************************
1459  * Function:
1460  *   aic7xxx_scb_tsleep
1461  *
1462  * Description:
1463  *   Emulates a BSD tsleep where a process can sleep for a specified
1464  *   amount of time, but may be awakened before that.  Linux provides
1465  *   a sleep_on, wake_up, add_timer, and del_timer which can be used to
1466  *   emulate tsleep, but there's not enough information available on
1467  *   how to use them.  For now, we'll just poll for SCB completion.
1468  *
1469  *   The parameter ticks is the number of clock ticks
1470  *   to wait before a timeout.  A 0 is returned if the scb does not
1471  *   timeout, 1 is returned for a timeout.
1472  *-F*************************************************************************/
1473 static int
1474 aic7xxx_scb_tsleep(struct aic7xxx_host *p,
     /*  */
1475                    struct aic7xxx_scb  *scb,
1476                    unsigned long        ticks)
1477 {
1478   scb->timer_status = TIMER_ENABLED;
1479 #ifdef AIC7XXX_POLL
1480   UNPAUSE_SEQUENCER(p);
1481   aic7xxx_poll_scb(p, scb, ticks);
1482 #else
1483   scb->waiting = &(scb->waitq);
1484   scb->timer.expires = jiffies + ticks;
1485   scb->timer.data = (unsigned long) scb;
1486   scb->timer.function = (timeout_fn) aic7xxx_scb_timeout;
1487   add_timer(&scb->timer);
1488   UNPAUSE_SEQUENCER(p);
1489   sleep_on(&(scb->waiting));
1490   del_timer(&scb->timer);
1491 #endif
1492   if (!(scb->timer_status & TIMED_CMD_DONE))
1493   {
1494     scb->timer_status = 0x0;
1495     return (1);
1496   }
1497   else
1498   {
1499     scb->timer_status = 0x0;
1500     return (0);
1501   }
1502 }
1503 
1504 /*+F*************************************************************************
1505  * Function:
1506  *   rcs_version
1507  *
1508  * Description:
1509  *   Return a string containing just the RCS version number from either
1510  *   an Id or Revison RCS clause.
1511  *-F*************************************************************************/
1512 const char *
1513 rcs_version(const char *version_info)
     /*  */
1514 {
1515   static char buf[10];
1516   char *bp, *ep;
1517 
1518   bp = NULL;
1519   strcpy(buf, "????");
1520   if (!strncmp(version_info, "$Id: ", 5))
1521   {
1522     if ((bp = strchr(version_info, ' ')) != NULL)
1523     {
1524       bp++;
1525       if ((bp = strchr(bp, ' ')) != NULL)
1526       {
1527         bp++;
1528       }
1529     }
1530   }
1531   else
1532   {
1533     if (!strncmp(version_info, "$Revision: ", 11))
1534     {
1535       if ((bp = strchr(version_info, ' ')) != NULL)
1536       {
1537         bp++;
1538       }
1539     }
1540   }
1541 
1542   if (bp != NULL)
1543   {
1544     if ((ep = strchr(bp, ' ')) != NULL)
1545     {
1546       register int len = ep - bp;
1547 
1548       strncpy(buf, bp, len);
1549       buf[len] = '\0';
1550     }
1551   }
1552 
1553   return buf;
1554 }
1555 
1556 /*+F*************************************************************************
1557  * Function:
1558  *   aic7xxx_info
1559  *
1560  * Description:
1561  *   Return a string describing the driver.
1562  *-F*************************************************************************/
1563 const char *
1564 aic7xxx_info(struct Scsi_Host *notused)
     /*  */
1565 {
1566   static char buffer[128];
1567 
1568   strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1569   strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1570   strcat(buffer, "/");
1571   strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1572   strcat(buffer, "/");
1573   strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1574 
1575   return buffer;
1576 }
1577 
1578 /*+F*************************************************************************
1579  * Function:
1580  *   aic7xxx_length
1581  *
1582  * Description:
1583  *   How much data should be transferred for this SCSI command? Stop
1584  *   at segment sg_last if it's a scatter-gather command so we can
1585  *   compute underflow easily.
1586  *-F*************************************************************************/
1587 static unsigned
1588 aic7xxx_length(Scsi_Cmnd *cmd, int sg_last)
     /*  */
1589 {
1590   int i, segments;
1591   unsigned length;
1592   struct scatterlist *sg;
1593 
1594   segments = cmd->use_sg - sg_last;
1595   sg = (struct scatterlist *) cmd->buffer;
1596 
1597   if (cmd->use_sg)
1598   {
1599     for (i = length = 0; (i < cmd->use_sg) && (i < segments); i++)
1600     {
1601       length += sg[i].length;
1602     }
1603   }
1604   else
1605   {
1606     length = cmd->request_bufflen;
1607   }
1608 
1609   return (length);
1610 }
1611 
1612 /*+F*************************************************************************
1613  * Function:
1614  *   aic7xxx_scsirate
1615  *
1616  * Description:
1617  *   Look up the valid period to SCSIRATE conversion in our table
1618  *-F*************************************************************************/
1619 static void
1620 aic7xxx_scsirate(struct aic7xxx_host *p, unsigned char *scsirate,
     /*  */
1621                  unsigned char period, unsigned char offset,
1622                  int target, char channel)
1623 {
1624   int i;
1625 
1626   for (i = 0; i < num_aic7xxx_syncrates; i++)
1627   {
1628     if ((aic7xxx_syncrates[i].period - period) >= 0)
1629     {
1630       /*
1631        * Watch out for Ultra speeds when ultra is not enabled and
1632        * vice-versa.
1633        */
1634       if (p->ultra_enabled)
1635       {
1636         if (! (aic7xxx_syncrates[i].rate & ULTRA_SXFR))
1637         {
1638           printk ("aic7xxx: target %d, channel %c, requests %sMB/s transfers, "
1639                   "but adapter in Ultra mode can only sync at 10MB/s or "
1640                   "above.\n", target, channel, aic7xxx_syncrates[i].english);
1641           break;  /* Use asynchronous transfers. */
1642         }
1643       }
1644       else
1645       {
1646         /*
1647          * Check for an Ultra device trying to negotiate an Ultra rate
1648          * on an adapter with Ultra mode disabled.
1649          */
1650         if (aic7xxx_syncrates[i].rate & ULTRA_SXFR)
1651         {
1652           /*
1653            * This should only happen if the driver is the first to negotiate
1654            * and chooses a high rate.  We'll just move down the table until
1655            * we hit a non Ultra speed.
1656            */
1657            continue;
1658         }
1659       }
1660       *scsirate = (aic7xxx_syncrates[i].rate) | (offset & 0x0F);
1661       printk("aic7xxx: target %d, channel %c, now synchronous at %sMB/s, "
1662              "offset = 0x%x\n",
1663              target, channel, aic7xxx_syncrates[i].english, offset);
1664       return;
1665     }
1666   }
1667 
1668   /*
1669    * Default to asyncronous transfer
1670    */
1671   *scsirate = 0;
1672   printk("aic7xxx: target %d, channel %c, using asynchronous transfers\n",
1673          target, channel);
1674 }
1675 
1676 /*+F*************************************************************************
1677  * Function:
1678  *   aic7xxx_putscb
1679  *
1680  * Description:
1681  *   Transfer a SCB to the controller.
1682  *-F*************************************************************************/
1683 static void
1684 aic7xxx_putscb(int base, struct aic7xxx_scb *scb)
     /*  */
1685 {
1686   /*
1687    * All we need to do, is to output the position
1688    * of the SCB in the SCBARRAY to the QINFIFO
1689    * of the host adapter.
1690    */
1691   outb(scb->position, QINFIFO(base));
1692 }
1693 
1694 /*+F*************************************************************************
1695  * Function:
1696  *   aic7xxx_putscb_dma
1697  *
1698  * Description:
1699  *   DMA a SCB to the controller.
1700  *-F*************************************************************************/
1701 static void
1702 aic7xxx_putscb_dma(int base, struct aic7xxx_scb *scb)
     /*  */
1703 {
1704   /*
1705    * By turning on the SCB auto increment, any reference
1706    * to the SCB I/O space postincrements the SCB address
1707    * we're looking at. So turn this on and dump the relevant
1708    * portion of the SCB to the card.
1709    */
1710   outb(SCBAUTO, SCBCNT(base));
1711 
1712   asm volatile("cld\n\t"
1713                "rep\n\t"
1714                "outsb"
1715                : /* no output */
1716                :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1717                :"si", "cx", "dx");
1718 
1719   outb(0, SCBCNT(base));
1720 }
1721 
1722 /*+F*************************************************************************
1723  * Function:
1724  *   aic7xxx_getscb
1725  *
1726  * Description:
1727  *   Get a SCB from the controller.
1728  *-F*************************************************************************/
1729 static void
1730 aic7xxx_getscb(int base, struct aic7xxx_scb *scb)
     /*  */
1731 {
1732   /*
1733    * This is almost identical to aic7xxx_putscb().
1734    */
1735   outb(SCBAUTO, SCBCNT(base));
1736 
1737   asm volatile("cld\n\t"
1738                "rep\n\t"
1739                "insb"
1740                : /* no output */
1741                :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1742                :"di", "cx", "dx");
1743 
1744   outb(0, SCBCNT(base));
1745 }
1746 
1747 /*+F*************************************************************************
1748  * Function:
1749  *   aic7xxx_match_scb
1750  *
1751  * Description:
1752  *   Checks to see if an scb matches the target/channel as specified.
1753  *   If target is ALL_TARGETS (-1), then we're looking for any device
1754  *   on the specified channel; this happens when a channel is going
1755  *   to be reset and all devices on that channel must be aborted.
1756  *-F*************************************************************************/
1757 static int
1758 aic7xxx_match_scb(struct aic7xxx_scb *scb, int target, char channel)
     /*  */
1759 {
1760   int targ = (scb->target_channel_lun >> 4) & 0x0F;
1761   char chan = (scb->target_channel_lun & SELBUSB) ? 'B' : 'A';
1762 
1763   if (target == ALL_TARGETS)
1764   {
1765     return (chan == channel);
1766   }
1767   else
1768   {
1769     return ((chan == channel) && (targ == target));
1770   }
1771 }
1772 
1773 /*+F*************************************************************************
1774  * Function:
1775  *   aic7xxx_unbusy_target
1776  *
1777  * Description:
1778  *   Set the specified target inactive.
1779  *-F*************************************************************************/
1780 static void
1781 aic7xxx_unbusy_target(unsigned char target, char channel, int base)
     /*  */
1782 {
1783   unsigned char active;
1784   unsigned long active_port = HA_ACTIVE0(base);
1785 
1786   if ((target > 0x07) || (channel == 'B'))
1787   {
1788     /*
1789      * targets on the Second channel or above id 7 store info in byte two
1790      * of HA_ACTIVE
1791      */
1792     active_port++;
1793   }
1794   active = inb(active_port);
1795   active &= ~(0x01 << (target & 0x07));
1796   outb(active_port, active);
1797 }
1798 
1799 /*+F*************************************************************************
1800  * Function:
1801  *   aic7xxx_done
1802  *
1803  * Description:
1804  *   Calls the higher level scsi done function and frees the scb.
1805  *-F*************************************************************************/
1806 static void
1807 aic7xxx_done(struct aic7xxx_host *p, struct aic7xxx_scb *scb)
     /*  */
1808 {
1809   long flags;
1810   Scsi_Cmnd *cmd = scb->cmd;
1811 
1812   if (scb->timer_status & TIMER_ENABLED)
1813   {
1814 #ifdef AIC7XXX_POLL
1815     scb->timer_status |= TIMED_CMD_DONE;
1816 #else
1817     aic7xxx_scb_untimeout(scb);
1818 #endif
1819   }
1820   else
1821   {
1822     /*
1823      * This is a critical section, since we don't want the
1824      * queue routine mucking with the host data.
1825      */
1826     save_flags(flags);
1827     cli();
1828 
1829     /*
1830      * Process the command after marking the scb as free
1831      * and adding it to the free list.
1832      */
1833     scb->state = SCB_FREE;
1834     scb->next = p->free_scb;
1835     p->free_scb = &(p->scb_array[scb->position]);
1836     scb->cmd = NULL;
1837 
1838     restore_flags(flags);
1839 
1840     cmd->scsi_done(cmd);
1841   }
1842 }
1843 
1844 /*+F*************************************************************************
1845  * Function:
1846  *   aic7xxx_add_waiting_scb
1847  *
1848  * Description:
1849  *   Add this SCB to the "waiting for selection" list.
1850  *-F*************************************************************************/
1851 static void
1852 aic7xxx_add_waiting_scb(u_long              base,
     /*  */
1853                         struct aic7xxx_scb *scb,
1854                         insert_type         where)
1855 {
1856   unsigned char head, tail;
1857   unsigned char curscb;
1858 
1859   curscb = inb(SCBPTR(base));
1860   head = inb(WAITING_SCBH(base));
1861   tail = inb(WAITING_SCBT(base));
1862   if (head == SCB_LIST_NULL)
1863   {
1864     /*
1865      * List was empty
1866      */
1867     head = scb->position;
1868     tail = SCB_LIST_NULL;
1869   }
1870   else
1871   {
1872     if (where == LIST_HEAD)
1873     {
1874       outb(scb->position, SCBPTR(base));
1875       outb(head, SCBARRAY(base) + 30);
1876       head = scb->position;
1877     }
1878     else
1879     {
1880       if (tail == SCB_LIST_NULL)
1881       {
1882         /*
1883          * List had one element
1884          */
1885         tail = scb->position;
1886         outb(head, SCBPTR(base));
1887         outb(tail, SCBARRAY(base) + 30);
1888       }
1889       else
1890       {
1891         if (where == LIST_SECOND)
1892         {
1893           unsigned char third_scb;
1894 
1895           outb(head, SCBPTR(base));
1896           third_scb = inb(SCBARRAY(base) + 30);
1897           outb(scb->position, SCBARRAY(base) + 30);
1898           outb(scb->position, SCBPTR(base));
1899           outb(third_scb, SCBARRAY(base) + 30);
1900         }
1901         else
1902         {
1903           outb(tail, SCBPTR(base));
1904           tail = scb->position;
1905           outb(tail, SCBARRAY(base) + 30);
1906         }
1907       }
1908     }
1909   }
1910   outb(head, WAITING_SCBH(base));
1911   outb(tail, WAITING_SCBT(base));
1912   outb(curscb, SCBPTR(base));
1913 }
1914 
1915 /*+F*************************************************************************
1916  * Function:
1917  *   aic7xxx_abort_waiting_scb
1918  *
1919  * Description:
1920  *   Manipulate the waiting for selection list and return the
1921  *   scb that follows the one that we remove.
1922  *-F*************************************************************************/
1923 static unsigned char
1924 aic7xxx_abort_waiting_scb(struct aic7xxx_host *p, struct aic7xxx_scb *scb,
     /*  */
1925                           unsigned char prev, unsigned char timedout_scb)
1926 {
1927   unsigned char curscb, next;
1928   int target = (scb->target_channel_lun >> 4) & 0x0F;
1929   char channel = (scb->target_channel_lun & SELBUSB) ? 'B' : 'A';
1930   int base = p->base;
1931 
1932   /*
1933    * Select the SCB we want to abort and
1934    * pull the next pointer out of it.
1935    */
1936   curscb = inb(SCBPTR(base));
1937   outb(scb->position, SCBPTR(base));
1938   next = inb(SCBARRAY(base) + 30);
1939 
1940   /*
1941    * Clear the necessary fields
1942    */
1943   outb(SCB_NEEDDMA, SCBARRAY(base));
1944   outb(SCB_LIST_NULL, SCBARRAY(base) + 30);
1945   aic7xxx_unbusy_target(target, channel, base);
1946 
1947   /*
1948    * Update the waiting list
1949    */
1950   if (prev == SCB_LIST_NULL)
1951   {
1952     /*
1953      * First in the list
1954      */
1955     outb(next, WAITING_SCBH(base));
1956   }
1957   else
1958   {
1959     /*
1960      * Select the scb that pointed to us and update its next pointer.
1961      */
1962     outb(prev, SCBPTR(base));
1963     outb(next, SCBARRAY(base) + 30);
1964   }
1965   /*
1966    * Update the tale pointer
1967    */
1968   if (inb(WAITING_SCBT(base)) == scb->position)
1969   {
1970     outb(prev, WAITING_SCBT(base));
1971   }
1972 
1973   /*
1974    * Point us back at the original scb position
1975    * and inform the SCSI system that the command
1976    * has been aborted.
1977    */
1978   outb(curscb, SCBPTR(base));
1979   scb->state |= SCB_ABORTED;
1980   scb->cmd->result = (DID_RESET << 16);
1981   aic7xxx_done(p, scb);
1982 
1983   return (next);
1984 }
1985 
1986 /*+F*************************************************************************
1987  * Function:
1988  *   aic7xxx_reset_device
1989  *
1990  * Description:
1991  *   The device at the given target/channel has been reset.  Abort
1992  *   all active and queued scbs for that target/channel.
1993  *-F*************************************************************************/
1994 static int
1995 aic7xxx_reset_device(struct aic7xxx_host *p, int target, char channel,
     /*  */
1996                      unsigned char timedout_scb)
1997 {
1998   int base = p->base;
1999   struct aic7xxx_scb *scb;
2000   unsigned char active_scb;
2001   int i = 0;
2002   int found = 0;
2003 
2004   /*
2005    * Restore this when we're done
2006    */
2007   active_scb = inb(SCBPTR(base));
2008 
2009   /*
2010    * Search the QINFIFO.
2011    */
2012   {
2013     int saved_queue[AIC7XXX_MAXSCB];
2014     int queued = inb(QINCNT(base));
2015 
2016     for (i = 0; i < (queued - found); i++)
2017     {
2018       saved_queue[i] = inb(QINFIFO(base));
2019       scb = &(p->scb_array[saved_queue[i]]);
2020       if (aic7xxx_match_scb(scb, target, channel))
2021       {
2022         /*
2023          * We found an scb that needs to be aborted.
2024          */
2025         scb->state |= SCB_ABORTED;
2026         scb->cmd->result = (DID_RESET << 16);
2027         aic7xxx_done(p, scb);
2028         outb(scb->position, SCBPTR(base));
2029         outb(SCB_NEEDDMA, SCBARRAY(base));
2030         i--;
2031         found++;
2032       }
2033     }
2034     /*
2035      * Now put the saved scbs back.
2036      */
2037     for (queued = 0; queued < i; queued++)
2038     {
2039       outb(saved_queue[queued], QINFIFO(base));
2040     }
2041   }
2042 
2043   /*
2044    * Search waiting for selection list.
2045    */
2046   {
2047     unsigned char next, prev;
2048 
2049     next = inb(WAITING_SCBH(base));  /* Start at head of list. */
2050     prev = SCB_LIST_NULL;
2051 
2052     while (next != SCB_LIST_NULL)
2053     {
2054       scb = &(p->scb_array[next]);
2055       /*
2056        * Select the SCB.
2057        */
2058       if (aic7xxx_match_scb(scb, target, channel))
2059       {
2060         next = aic7xxx_abort_waiting_scb(p, scb, prev, timedout_scb);
2061         found++;
2062       }
2063       else
2064       {
2065         outb(scb->position, SCBPTR(base));
2066         prev = next;
2067         next = inb(SCBARRAY(base) + 30);
2068       }
2069     }
2070   }
2071 
2072   /*
2073    * Go through the entire SCB array now and look for
2074    * commands for this target that are active.  These
2075    * are other (most likely tagged) commands that
2076    * were disconnected when the reset occured.
2077    */
2078   for(i = 0; i < p->numscb; i++)
2079   {
2080     scb = &(p->scb_array[i]);
2081     if ((scb->state & SCB_ACTIVE) && aic7xxx_match_scb(scb, target, channel))
2082     {
2083       /*
2084        * Ensure the target is "free"
2085        */
2086       aic7xxx_unbusy_target(target, channel, base);
2087       outb(scb->position, SCBPTR(base));
2088       outb(SCB_NEEDDMA, SCBARRAY(base));
2089       scb->state |= SCB_ABORTED;
2090       scb->cmd->result = (DID_RESET << 16);
2091       aic7xxx_done(p, scb);
2092       found++;
2093     }
2094   }
2095 
2096   outb(active_scb, SCBPTR(base));
2097   return (found);
2098 }
2099 
2100 /*+F*************************************************************************
2101  * Function:
2102  *   aic7xxx_reset_current_bus
2103  *
2104  * Description:
2105  *   Reset the current SCSI bus.
2106  *-F*************************************************************************/
2107 static void
2108 aic7xxx_reset_current_bus(int base)
     /*  */
2109 {
2110   outb(SCSIRSTO, SCSISEQ(base));
2111   udelay(1000);
2112   outb(0, SCSISEQ(base));
2113 }
2114 
2115 /*+F*************************************************************************
2116  * Function:
2117  *   aic7xxx_reset_channel
2118  *
2119  * Description:
2120  *   Reset the channel.
2121  *-F*************************************************************************/
2122 static int
2123 aic7xxx_reset_channel(struct aic7xxx_host *p, char channel,
     /*  */
2124                      unsigned char timedout_scb)
2125 {
2126   int base = p->base;
2127   unsigned char sblkctl;
2128   char cur_channel;
2129   unsigned long offset, offset_max;
2130   int found;
2131 
2132   /*
2133    * Clean up all the state information for the
2134    * pending transactions on this bus.
2135    */
2136   found = aic7xxx_reset_device(p, ALL_TARGETS, channel, timedout_scb);
2137 
2138   if (channel == 'B')
2139   {
2140     p->needsdtr |= (p->needsdtr_copy & 0xFF00);
2141     p->sdtr_pending &= 0x00FF;
2142     outb(0, HA_ACTIVE1(base));
2143     offset = HA_TARG_SCRATCH(base) + 8;
2144     offset_max = HA_TARG_SCRATCH(base) + 16;
2145   }
2146   else
2147   {
2148     if (p->bus_type == AIC_WIDE)
2149     {
2150       p->needsdtr = p->needsdtr_copy;
2151       p->needwdtr = p->needwdtr_copy;
2152       p->sdtr_pending = 0;
2153       p->wdtr_pending = 0;
2154       outb(0, HA_ACTIVE0(base));
2155       outb(0, HA_ACTIVE1(base));
2156       offset = HA_TARG_SCRATCH(base);
2157       offset_max = HA_TARG_SCRATCH(base) + 16;
2158     }
2159     else
2160     {
2161       p->needsdtr |= (p->needsdtr_copy & 0x00FF);
2162       p->sdtr_pending &= 0xFF00;
2163       outb(0, HA_ACTIVE0(base));
2164       offset = HA_TARG_SCRATCH(base);
2165       offset_max = HA_TARG_SCRATCH(base) + 8;
2166     }
2167   }
2168   while (offset < offset_max)
2169   {
2170     /*
2171      * Revert to async/narrow transfers
2172      * until we renegotiate.
2173      */
2174     u_char targ_scratch;
2175     targ_scratch = inb(offset);
2176     targ_scratch &= SXFR;
2177     outb(targ_scratch, offset);
2178     offset++;
2179   }
2180 
2181   /*
2182    * Reset the bus and unpause/restart the controller
2183    */
2184 
2185   /*
2186    * Case 1: Command for another bus is active
2187    */
2188   sblkctl = inb(SBLKCTL(base));
2189   cur_channel = (sblkctl & SELBUSB) ? 'B' : 'A';
2190   if (cur_channel != channel)
2191   {
2192     /*
2193      * Stealthily reset the other bus without upsetting the current bus
2194      */
2195     outb(sblkctl ^ SELBUSB, SBLKCTL(base));
2196     aic7xxx_reset_current_bus(base);
2197     outb(sblkctl, SBLKCTL(base));
2198 
2199     UNPAUSE_SEQUENCER(p);
2200   }
2201   /*
2202    * Case 2: A command from this bus is active or we're idle
2203    */
2204   else
2205   {
2206     aic7xxx_reset_current_bus(base);
2207     RESTART_SEQUENCER(p);
2208   }
2209 
2210   return found;
2211 }
2212 
2213 /*+F*************************************************************************
2214  * Function:
2215  *   aic7xxx_isr
2216  *
2217  * Description:
2218  *   SCSI controller interrupt handler.
2219  *
2220  *   NOTE: Since we declared this using SA_INTERRUPT, interrupts should
2221  *         be disabled all through this function unless we say otherwise.
2222  *-F*************************************************************************/
2223 static void
2224 aic7xxx_isr(int irq, struct pt_regs * regs)
     /*  */
2225 {
2226   int base, intstat;
2227   struct aic7xxx_host *p;
2228   struct aic7xxx_scb *scb;
2229   unsigned char ha_flags, transfer;
2230   unsigned char scsi_id, bus_width;
2231   unsigned char offset, rate, scratch, scratch_offset;
2232   unsigned char max_offset, rej_byte;
2233   unsigned short target_mask, active;
2234   char channel;
2235   void *addr;
2236   int actual;
2237   int scb_index;
2238   Scsi_Cmnd *cmd;
2239 
2240   p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
2241 
2242   /*
2243    * Search for the host with a pending interrupt.  If we can't find
2244    * one, then we've encountered a spurious interrupt.
2245    */
2246   while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
2247   {
2248     if (p->next == NULL)
2249     {
2250       p = NULL;
2251     }
2252     else
2253     {
2254       p = (struct aic7xxx_host *) p->next->hostdata;
2255     }
2256   }
2257 
2258   if (p == NULL)
2259   {
2260     if (aic7xxx_spurious_count == 1)
2261     {
2262       aic7xxx_spurious_count = 2;
2263       printk("aic7xxx_isr: Encountered spurious interrupt.\n");
2264       return;
2265     }
2266     else
2267     {
2268       /*
2269        * The best we can do is to set p back to head of list and process
2270        * the erroneous interrupt - most likely a BRKADRINT.
2271        */
2272       p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
2273     }
2274   }
2275 
2276   /*
2277    * Keep track of interrupts for /proc/scsi
2278    */
2279   p->isr_count++;
2280 
2281   if ((p->a_scanned == 0) && (p->isr_count == 1))
2282   {
2283     /*
2284      * We must only have one card at this IRQ and it must have been
2285      * added to the board data before the spurious interrupt occurred.
2286      * It is sufficient that we check isr_count and not the spurious
2287      * interrupt count.
2288      */
2289     printk("aic7xxx_isr: Encountered spurious interrupt.\n");
2290     return;
2291   }
2292 
2293   base = p->base;
2294   /*
2295    * Handle all the interrupt sources - especially for SCSI
2296    * interrupts, we won't get a second chance at them.
2297    */
2298   intstat = inb(INTSTAT(base));
2299 
2300   if (intstat & BRKADRINT)
2301   {
2302     int i;
2303     unsigned char errno = inb(ERROR(base));
2304 
2305     printk("aic7xxx_isr: brkadrint (0x%x):\n", errno);
2306     for (i = 0; i < NUMBER(hard_error); i++)
2307     {
2308       if (errno & hard_error[i].errno)
2309       {
2310         printk("  %s\n", hard_error[i].errmesg);
2311       }
2312     }
2313 
2314     panic("aic7xxx_isr: brkadrint, error = 0x%x, seqaddr = 0x%x\n",
2315           inb(ERROR(base)), (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
2316   }
2317 
2318   if (intstat & SEQINT)
2319   {
2320     /*
2321      * Although the sequencer is paused immediately on
2322      * a SEQINT, an interrupt for a SCSIINT condition will
2323      * unpaused the sequencer before this point.
2324      */
2325     PAUSE_SEQUENCER(p);
2326 
2327     scsi_id = (inb(SCSIID(base)) >> 4) & 0x0F;
2328     scratch_offset = scsi_id;
2329     channel = 'A';
2330     if (inb(SBLKCTL(base)) & SELBUSB)
2331     {
2332       channel = 'B';
2333       scratch_offset += 8;
2334     }
2335     target_mask = (0x01 << scratch_offset);
2336 
2337     switch (intstat & SEQINT_MASK)
2338     {
2339       case BAD_PHASE:
2340         panic("aic7xxx_isr: unknown scsi bus phase\n");
2341         break;
2342 
2343       case SEND_REJECT:
2344         rej_byte = inb(HA_REJBYTE(base));
2345         if (rej_byte != 0x20)
2346         {
2347           debug("aic7xxx_isr warning: issuing message reject, 1st byte 0x%x\n",
2348                 rej_byte);
2349         }
2350         else
2351         {
2352           scb_index = inb(SCBPTR(base));
2353           scb = &(p->scb_array[scb_index]);
2354           printk("aic7xxx_isr warning: Tagged message rejected for target %d,"
2355                  " channel %c.\n", scsi_id, channel);
2356           scb->cmd->device->tagged_supported = 0;
2357           scb->cmd->device->tagged_queue = 0;
2358         }
2359         break;
2360 
2361       case NO_IDENT:
2362         panic("aic7xxx_isr: Target %d, channel %c, did not send an IDENTIFY "
2363               "message.  SAVED_TCL = 0x%x\n",
2364               scsi_id, channel, inb(SAVED_TCL(base)));
2365         break;
2366 
2367       case NO_MATCH:
2368         printk("aic7xxx_isr: No active SCB for reconnecting target %d, "
2369               "channel %c - issuing ABORT\n", scsi_id, channel);
2370         printk("SAVED_TCL = 0x%x\n", inb(SAVED_TCL(base)));
2371         aic7xxx_unbusy_target(scsi_id, channel, base);
2372         outb(SCB_NEEDDMA, SCBARRAY(base));
2373 
2374         outb(CLRSELTIMEO, CLRSINT1(base));
2375         RESTART_SEQUENCER(p);
2376         break;
2377 
2378       case MSG_SDTR:
2379         /*
2380          * Help the sequencer to translate the negotiated
2381          * transfer rate. Transfer is 1/4 the period
2382          * in ns as is returned by the sync negotiation
2383          * message. So, we must multiply by four.
2384          */
2385         transfer = (inb(HA_ARG_1(base)) << 2);
2386         offset = inb(ACCUM(base));
2387         scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2388         /*
2389          * The maximum offset for a wide device is 0x08; for a
2390          * 8-bit bus device the maximum offset is 0x0F.
2391          */
2392         if (scratch & WIDEXFER)
2393         {
2394           max_offset = 0x08;
2395         }
2396         else
2397         {
2398           max_offset = 0x0F;
2399         }
2400         aic7xxx_scsirate(p, &rate, transfer, MIN(offset, max_offset), scsi_id, channel);
2401         /*
2402          * Preserve the wide transfer flag.
2403          */
2404         scratch = rate | (scratch & WIDEXFER);
2405         outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2406         outb(scratch, SCSIRATE(base));
2407         if ((scratch & 0x0F) == 0)
2408         { /*
2409            * The requested rate was so low that asynchronous transfers
2410            * are faster (not to mention the controller won't support
2411            * them), so we issue a reject to ensure we go to asynchronous
2412            * transfers.
2413            */
2414            outb(SEND_REJ, HA_RETURN_1(base));
2415         }
2416         else
2417         {
2418           /*
2419            * See if we initiated Sync Negotiation
2420            */
2421           if (p->sdtr_pending & target_mask)
2422           {
2423             /*
2424              * Don't send an SDTR back to the target.
2425              */
2426             outb(0, HA_RETURN_1(base));
2427           }
2428           else
2429           {
2430             /*
2431              * Send our own SDTR in reply.
2432              */
2433             printk("aic7xxx_isr: Sending SDTR!!\n");
2434             outb(SEND_SDTR, HA_RETURN_1(base));
2435           }
2436         }
2437         /*
2438          * Clear the flags.
2439          */
2440         p->needsdtr &= ~target_mask;
2441         p->sdtr_pending &= ~target_mask;
2442 #if 0
2443   scb_index = inb(SCBPTR(base));
2444   scb = &(p->scb_array[scb_index]);
2445   debug_scb(scb);
2446 #endif
2447 
2448         break;
2449 
2450       case MSG_WDTR:
2451       {
2452         bus_width = inb(ACCUM(base));
2453         printk("aic7xxx_isr: Received MSG_WDTR, scsi_id %d, channel %c "
2454                "needwdtr = 0x%x\n", scsi_id, channel, p->needwdtr);
2455         scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2456 
2457         if (p->wdtr_pending & target_mask)
2458         {
2459           /*
2460            * Don't send an WDTR back to the target, since we asked first.
2461            */
2462           outb(0, HA_RETURN_1(base));
2463           switch (bus_width)
2464           {
2465             case BUS_8_BIT:
2466               scratch &= 0x7F;
2467               break;
2468 
2469             case BUS_16_BIT:
2470               printk("aic7xxx_isr: target %d, channel %c, using 16 bit transfers\n",
2471                      scsi_id, channel);
2472               scratch |= 0x80;
2473               break;
2474           }
2475         }
2476         else
2477         {
2478           /*
2479            * Send our own WDTR in reply.
2480            */
2481           printk("aic7xxx_isr: Will send WDTR!!\n");
2482           switch (bus_width)
2483           {
2484             case BUS_8_BIT:
2485               scratch &= 0x7F;
2486               break;
2487 
2488             case BUS_32_BIT:
2489               /*
2490                * Negotiate 16 bits.
2491                */
2492               bus_width = BUS_16_BIT;
2493               /* Yes, we mean to fall thru here. */
2494 
2495             case BUS_16_BIT:
2496               printk("aic7xxx_isr: target %d, channel %c, using 16 bit transfers\n",
2497                      scsi_id, channel);
2498               scratch |= 0x80;
2499               break;
2500           }
2501           outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
2502         }
2503         p->needwdtr &= ~target_mask;
2504         p->wdtr_pending &= ~target_mask;
2505         outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2506         outb(scratch, SCSIRATE(base));
2507         break;
2508       }
2509 
2510       case MSG_REJECT:
2511       {
2512         /*
2513          * What we care about here is if we had an
2514          * outstanding SDTR or WDTR message for this
2515          * target. If we did, this is a signal that
2516          * the target is refusing negotiation.
2517          */
2518 
2519         scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2520 
2521         if (p->wdtr_pending & target_mask)
2522         {
2523           /*
2524            * note 8bit xfers and clear flag
2525            */
2526           scratch &= 0x7F;
2527           p->needwdtr &= ~target_mask;
2528           p->wdtr_pending &= ~target_mask;
2529           outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2530           printk("aic7xxx: target %d, channel %c, refusing WIDE negotiation. "
2531                  "Using 8 bit transfers\n", scsi_id, channel);
2532         }
2533         else
2534         {
2535           if (p->sdtr_pending & target_mask)
2536           {
2537             /*
2538              * note asynch xfers and clear flag
2539              */
2540             scratch &= 0xF0;
2541             p->needsdtr &= ~target_mask;
2542             p->sdtr_pending &= ~target_mask;
2543             outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2544             printk("aic7xxx: target %d, channel %c, refusing syncronous negotiation. "
2545                    "Using asyncronous transfers\n", scsi_id, channel);
2546           }
2547           /*
2548            * Otherwise, we ignore it.
2549            */
2550         }
2551         outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2552         outb(scratch, SCSIRATE(base));
2553         break;
2554       }
2555 
2556       case BAD_STATUS:
2557         scb_index = inb(SCBPTR(base));
2558         scb = &(p->scb_array[scb_index]);
2559         outb(0, HA_RETURN_1(base));   /* CHECK_CONDITION may change this */
2560         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2561         {
2562           printk("aic7xxx_isr: referenced scb not valid "
2563                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2564                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2565         }
2566         else
2567         {
2568           cmd = scb->cmd;
2569           aic7xxx_getscb(base, scb);
2570           aic7xxx_status(cmd) = scb->target_status;
2571 
2572           cmd->result |= scb->target_status;
2573 
2574           switch (status_byte(scb->target_status))
2575           {
2576             case GOOD:
2577               printk("aic7xxx_isr: Interrupted for status of 0???\n");
2578               break;
2579 
2580             case CHECK_CONDITION:
2581               if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
2582               {
2583                 unsigned char tcl;
2584                 unsigned char control;
2585                 void         *req_buf;
2586 
2587                 tcl = scb->target_channel_lun;
2588                 /*
2589                  * Send a sense command to the requesting target.
2590                  */
2591                 cmd->flags |= WAS_SENSE;
2592                 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
2593                        sizeof(generic_sense));
2594 
2595                 scb->sense_cmd[1] = (cmd->lun << 5);
2596                 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
2597 
2598                 scb->sense_sg.address = (char *) &cmd->sense_buffer;
2599                 scb->sense_sg.length = sizeof(cmd->sense_buffer);
2600                 req_buf = &scb->sense_sg;
2601                 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
2602                 control = scb->control;
2603                 memset(scb, 0, SCB_DOWNLOAD_SIZE);
2604                 scb->control = control & SCB_DISCENB;
2605                 scb->target_channel_lun = tcl;
2606                 addr = scb->sense_cmd;
2607                 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
2608                 memcpy(scb->SCSI_cmd_pointer, &addr,
2609                        sizeof(scb->SCSI_cmd_pointer));
2610                 scb->SG_segment_count = 1;
2611                 memcpy(scb->SG_list_pointer, &req_buf,
2612                         sizeof(scb->SG_list_pointer));
2613                 scb->data_count[0] = scb->sense_sg.length & 0xFF;
2614                 scb->data_count[1] = (scb->sense_sg.length >> 8) & 0xFF;
2615                 scb->data_count[2] = (scb->sense_sg.length >> 16) & 0xFF;
2616                 memcpy(scb->data_pointer, &(scb->sense_sg.address), 4);
2617 
2618                 outb(SCBAUTO, SCBCNT(base));
2619                 asm volatile("cld\n\t"
2620                              "rep\n\t"
2621                              "outsb"
2622                              : /* no output */
2623                              :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
2624                              :"si", "cx", "dx");
2625                 outb(0, SCBCNT(base));
2626                 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
2627                 /*
2628                  * Ensure that the target is "BUSY" so we don't get overlapping
2629                  * commands if we happen to be doing tagged I/O.
2630                  */
2631                 active = inb(HA_ACTIVE0(base)) | (inb(HA_ACTIVE1(base)) << 8);
2632                 active |= target_mask;
2633                 outb(active & 0xFF, HA_ACTIVE0(base));
2634                 outb((active >> 8) & 0xFF, HA_ACTIVE1(base));
2635 
2636                 aic7xxx_add_waiting_scb(base, scb, LIST_HEAD);
2637                 outb(SEND_SENSE, HA_RETURN_1(base));
2638               }  /* first time sense, no errors */
2639               else
2640               {
2641                 /*
2642                  * Indicate that we asked for sense, have the sequencer do
2643                  * a normal command complete, and have the scsi driver handle
2644                  * this condition.
2645                  */
2646                 cmd->flags |= ASKED_FOR_SENSE;
2647               }
2648               break;
2649 
2650             case BUSY:
2651               printk("aic7xxx_isr: Target busy\n");
2652               if (!aic7xxx_error(cmd))
2653               {
2654                 aic7xxx_error(cmd) = DID_BUS_BUSY;
2655               }
2656               break;
2657 
2658             case QUEUE_FULL:
2659               printk("aic7xxx_isr: Queue full\n");
2660               if (!aic7xxx_error(cmd))
2661               {
2662                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2663               }
2664               break;
2665 
2666             default:
2667               printk("aic7xxx_isr: Unexpected target status 0x%x\n",
2668                      scb->target_status);
2669               if (!aic7xxx_error(cmd))
2670               {
2671                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2672               }
2673               break;
2674           }  /* end switch */
2675         }  /* end else of */
2676         break;
2677 
2678       case RESIDUAL:
2679         scb_index = inb(SCBPTR(base));
2680         scb = &(p->scb_array[scb_index]);
2681         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2682         {
2683           printk("aic7xxx_isr: referenced scb not valid "
2684                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2685                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2686         }
2687         else
2688         {
2689           cmd = scb->cmd;
2690           /*
2691            *  Don't destroy valid residual information with
2692            *  residual coming from a check sense operation.
2693            */
2694           if (!(cmd->flags & WAS_SENSE))
2695           {
2696             /*
2697              *  We had an underflow. At this time, there's only
2698              *  one other driver that bothers to check for this,
2699              *  and cmd->underflow seems to be set rather half-
2700              *  heartedly in the higher-level SCSI code.
2701              */
2702             actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
2703 
2704             actual -= ((inb(SCBARRAY(base + 17)) << 16) |
2705                        (inb(SCBARRAY(base + 16)) <<  8) |
2706                        inb(SCBARRAY(base + 15)));
2707 
2708             if (actual < cmd->underflow)
2709             {
2710               printk("aic7xxx: target %d underflow - "
2711                      "wanted (at least) %u, got %u, count=%d\n",
2712                      cmd->target, cmd->underflow, actual, inb(SCBARRAY(base + 18)));
2713               aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2714               aic7xxx_status(cmd) = scb->target_status;
2715             }
2716           }
2717         }
2718         break;
2719 
2720       case ABORT_TAG:
2721         scb_index = inb(SCBPTR(base));
2722         scb = &(p->scb_array[scb_index]);
2723         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2724         {
2725           printk("aic7xxx_isr: referenced scb not valid "
2726                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2727                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2728         }
2729         else
2730         {
2731           cmd = scb->cmd;
2732           /*
2733            * We didn't recieve a valid tag back from the target
2734            * on a reconnect.
2735            */
2736           printk("aic7xxx_isr: invalid tag recieved on channel %c "
2737                  "target %d, lun %d -- sending ABORT_TAG\n",
2738                   channel, scsi_id, cmd->lun & 0x07);
2739 
2740           cmd->result = (DID_RETRY_COMMAND << 16);
2741           aic7xxx_done(p, scb);
2742         }
2743         break;
2744 
2745       case AWAITING_MSG:
2746         scb_index = inb(SCBPTR(base));
2747         scb = &(p->scb_array[scb_index]);
2748         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2749         {
2750           printk("aic7xxx_isr: referenced scb not valid "
2751                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2752                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2753         }
2754         else
2755         {
2756           /*
2757            * This SCB had a zero length command, informing the sequencer
2758            * that we wanted to send a special message to this target.
2759            * We only do this for BUS_DEVICE_RESET messages currently.
2760            */
2761            if (scb->state & SCB_DEVICE_RESET)
2762            {
2763              outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
2764              outb(1, HA_MSG_LEN(base));
2765            }
2766            else
2767            {
2768              panic("aic7xxx_isr: AWAITING_SCB for an SCB that does "
2769                    "not have a waiting message");
2770            }
2771         }
2772         break;
2773 
2774       case IMMEDDONE:
2775         scb_index = inb(SCBPTR(base));
2776         scb = &(p->scb_array[scb_index]);
2777         if (scb->state & SCB_DEVICE_RESET)
2778         {
2779           int found;
2780 
2781           /*
2782            * Go back to async/narrow transfers and renogiate.
2783            */
2784           aic7xxx_unbusy_target(scsi_id, channel, base);
2785           p->needsdtr |= (p->needsdtr_copy & target_mask);
2786           p->needwdtr |= (p->needwdtr_copy & target_mask);
2787           p->sdtr_pending &= ~target_mask;
2788           p->wdtr_pending &= ~target_mask;
2789           scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2790           scratch &= SXFR;
2791           outb(scratch, HA_TARG_SCRATCH(base));
2792           found = aic7xxx_reset_device(p, (int) scsi_id, channel, SCB_LIST_NULL);
2793         }
2794         else
2795         {
2796           panic("aic7xxx_isr: Immediate complete for unknown operation.\n");
2797         }
2798         break;
2799 
2800       default:               /* unknown */
2801         debug("aic7xxx_isr: seqint, intstat = 0x%x, scsisigi = 0x%x\n",
2802               intstat, inb(SCSISIGI(base)));
2803         break;
2804     }
2805     outb(CLRSEQINT, CLRINT(base));
2806     UNPAUSE_SEQUENCER(p);
2807   }
2808 
2809   if (intstat & SCSIINT)
2810   {
2811     int status = inb(SSTAT1(base));
2812 
2813     scb_index = inb(SCBPTR(base));
2814     scb = &(p->scb_array[scb_index]);
2815     if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2816     {
2817       printk("aic7xxx_isr: no command for scb (scsiint)\n");
2818       /*
2819        * Turn off the interrupt and set status
2820        * to zero, so that it falls through the
2821        * reset of the SCSIINT code.
2822        */
2823       outb(status, CLRSINT1(base));
2824       UNPAUSE_SEQUENCER(p);
2825       outb(CLRSCSIINT, CLRINT(base));
2826       status = 0;
2827       scb = NULL;
2828     }
2829     else
2830     {
2831       cmd = scb->cmd;
2832 
2833       /*
2834        * Only the SCSI Status 1 register has information
2835        * about exceptional conditions that we'd have a
2836        * SCSIINT about; anything in SSTAT0 will be handled
2837        * by the sequencer. Note that there can be multiple
2838        * bits set.
2839        */
2840       if (status & SELTO)
2841       {
2842         unsigned char target_mask = (1 << (cmd->target & 0x07));
2843         unsigned char waiting;
2844 
2845         /*
2846          * Hardware selection timer has expired. Turn
2847          * off SCSI selection sequence.
2848          */
2849         outb(ENRSELI, SCSISEQ(base));
2850         cmd->result = (DID_TIME_OUT << 16);
2851         /*
2852          * Clear an pending messages for the timed out
2853          * target and mark the target as free.
2854          */
2855         ha_flags = inb(HA_FLAGS(base));
2856         outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2857 
2858         if (scb->target_channel_lun & 0x88)
2859         {
2860           active = inb(HA_ACTIVE1(base));
2861           active = active & ~(target_mask);
2862           outb(active, HA_ACTIVE1(base));
2863         }
2864         else
2865         {
2866           active = inb(HA_ACTIVE0(base));
2867           active &= ~(target_mask);
2868           outb(active, HA_ACTIVE0(base));
2869         }
2870 
2871         outb(SCB_NEEDDMA, SCBARRAY(base));
2872 
2873         /*
2874          * Shut off the offending interrupt sources, reset
2875          * the sequencer address to zero and unpause it,
2876          * then call the high-level SCSI completion routine.
2877          *
2878          * WARNING!  This is a magic sequence!  After many
2879          * hours of guesswork, turning off the SCSI interrupts
2880          * in CLRSINT? does NOT clear the SCSIINT bit in
2881          * INTSTAT. By writing to the (undocumented, unused
2882          * according to the AIC-7770 manual) third bit of
2883          * CLRINT, you can clear INTSTAT. But, if you do it
2884          * while the sequencer is paused, you get a BRKADRINT
2885          * with an Illegal Host Address status, so the
2886          * sequencer has to be restarted first.
2887          */
2888         outb(CLRSELTIMEO, CLRSINT1(base));
2889 
2890         outb(CLRSCSIINT, CLRINT(base));
2891 
2892         /*
2893          * Shift the waiting for selection queue forward
2894          */
2895         waiting = inb(WAITING_SCBH(base));
2896         outb(waiting, SCBPTR(base));
2897         waiting = inb(SCBARRAY(base) + 30);
2898         outb(waiting, WAITING_SCBH(base));
2899 
2900         RESTART_SEQUENCER(p);
2901         aic7xxx_done(p, scb);
2902 #if 0
2903   printk("aic7xxx_isr: SELTO scb(%d) state(%x), cmd(%x)\n",
2904          scb->position, scb->state, (unsigned int) scb->cmd);
2905 #endif
2906       }
2907       else
2908       {
2909         if (status & SCSIPERR)
2910         {
2911           /*
2912            * A parity error has occurred during a data
2913            * transfer phase. Flag it and continue.
2914            */
2915           printk("aic7xxx: parity error on target %d, "
2916                  "channel %d, lun %d\n",
2917                  cmd->target,
2918                  cmd->channel & 0x01,
2919                  cmd->lun & 0x07);
2920           aic7xxx_error(cmd) = DID_PARITY;
2921 
2922           /*
2923            * Clear interrupt and resume as above.
2924            */
2925           outb(CLRSCSIPERR, CLRSINT1(base));
2926           UNPAUSE_SEQUENCER(p);
2927 
2928           outb(CLRSCSIINT, CLRINT(base));
2929           scb = NULL;
2930         }
2931         else
2932         {
2933           if (!(status & BUSFREE))
2934           {
2935              /*
2936               * We don't know what's going on. Turn off the
2937               * interrupt source and try to continue.
2938               */
2939              printk("aic7xxx_isr: sstat1 = 0x%x\n", status);
2940              outb(status, CLRSINT1(base));
2941              UNPAUSE_SEQUENCER(p);
2942              outb(CLRSCSIINT, CLRINT(base));
2943              scb = NULL;
2944           }
2945         }
2946       }
2947     }  /* else */
2948   }
2949 
2950   if (intstat & CMDCMPLT)
2951   {
2952     int complete;
2953 
2954     /*
2955      * The sequencer will continue running when it
2956      * issues this interrupt. There may be >1 commands
2957      * finished, so loop until we've processed them all.
2958      */
2959     do {
2960       complete = inb(QOUTFIFO(base));
2961 
2962       scb = &(p->scb_array[complete]);
2963       if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2964       {
2965         printk("aic7xxx warning: "
2966                "no command for scb %d (cmdcmplt)\n"
2967                "QOUTCNT = %d, SCB state = 0x%x, CMD = 0x%x, pos = %d\n",
2968                complete, inb(QOUTFIFO(base)),
2969                scb->state, (unsigned int) scb->cmd, scb->position);
2970         outb(CLRCMDINT, CLRINT(base));
2971         continue;
2972       }
2973       cmd = scb->cmd;
2974 
2975       cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2976       if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2977       {
2978         /*
2979          * Got sense information.
2980          */
2981         cmd->flags &= ASKED_FOR_SENSE;
2982       }
2983 #if 0
2984       printk("aic7xxx_intr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2985              scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2986 #endif
2987 
2988       /*
2989        * Clear interrupt status before checking
2990        * the output queue again. This eliminates
2991        * a race condition whereby a command could
2992        * complete between the queue poll and the
2993        * interrupt clearing, so notification of the
2994        * command being complete never made it back
2995        * up to the kernel.
2996        */
2997       outb(CLRCMDINT, CLRINT(base));
2998       aic7xxx_done(p, scb);
2999 #if 0
3000   if (scb != &p->scb_array[scb->position])
3001   {
3002     printk("aic7xxx_isr: (complete) address mismatch, pos %d\n", scb->position);
3003   }
3004   printk("aic7xxx_isr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
3005          scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
3006 #endif
3007 
3008 #ifdef AIC7XXX_PROC_STATS
3009       /*
3010        * XXX: we should actually know how much actually transferred
3011        * XXX: for each command, but apparently that's too difficult.
3012        */
3013       actual = aic7xxx_length(cmd, 0);
3014       if (((cmd->flags & WAS_SENSE) == 0) && (actual > 0))
3015       {
3016         struct aic7xxx_xferstats *sp;
3017         long *ptr;
3018         int x;
3019 
3020         sp = &p->stats[cmd->channel & 0x01][cmd->target & 0x0F][cmd->lun & 0x07];
3021         sp->xfers++;
3022 
3023         if (cmd->request.cmd == WRITE)
3024         {
3025           sp->w_total++;
3026           sp->w_total512 += (actual >> 9);
3027           ptr = sp->w_bins;
3028         }
3029         else
3030         {
3031           sp->r_total++;
3032           sp->r_total512 += (actual >> 9);
3033           ptr = sp->r_bins;
3034         }
3035         for (x = 9; x <= 17; x++)
3036         {
3037           if (actual < (1 << x))
3038           {
3039             ptr[x - 9]++;
3040             break;
3041           }
3042         }
3043         if (x > 17)
3044         {
3045           ptr[x - 9]++;
3046         }
3047       }
3048 #endif /* AIC7XXX_PROC_STATS */
3049 
3050     } while (inb(QOUTCNT(base)));
3051   }
3052 }
3053 
3054 /*+F*************************************************************************
3055  * Function:
3056  *   aic7xxx_probe
3057  *
3058  * Description:
3059  *   Probing for EISA boards: it looks like the first two bytes
3060  *   are a manufacturer code - three characters, five bits each:
3061  *
3062  *               BYTE 0   BYTE 1   BYTE 2   BYTE 3
3063  *              ?1111122 22233333 PPPPPPPP RRRRRRRR
3064  *
3065  *   The characters are baselined off ASCII '@', so add that value
3066  *   to each to get the real ASCII code for it. The next two bytes
3067  *   appear to be a product and revision number, probably vendor-
3068  *   specific. This is what is being searched for at each port,
3069  *   and what should probably correspond to the ID= field in the
3070  *   ECU's .cfg file for the card - if your card is not detected,
3071  *   make sure your signature is listed in the array.
3072  *
3073  *   The fourth byte's lowest bit seems to be an enabled/disabled
3074  *   flag (rest of the bits are reserved?).
3075  *-F*************************************************************************/
3076 static aha_type
3077 aic7xxx_probe(int slot, int base)
     /*  */
3078 {
3079   int i;
3080   unsigned char buf[4];
3081 
3082   static struct {
3083     int n;
3084     unsigned char signature[sizeof(buf)];
3085     aha_type type;
3086   } AIC7xxx[] = {
3087     { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_274x },  /* host adapter 274x */
3088     { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_274x },  /* motherboard 274x  */
3089     { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x },  /* 284x, BIOS enabled */
3090     { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x }   /* 284x, BIOS disabled */
3091   };
3092 
3093   /*
3094    * The VL-bus cards need to be primed by
3095    * writing before a signature check.
3096    */
3097   for (i = 0; i < sizeof(buf); i++)
3098   {
3099     outb(0x80 + i, base);
3100     buf[i] = inb(base + i);
3101   }
3102 
3103   for (i = 0; i < NUMBER(AIC7xxx); i++)
3104   {
3105     /*
3106      * Signature match on enabled card?
3107      */
3108     if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
3109     {
3110       if (inb(base + 4) & 1)
3111       {
3112         return (AIC7xxx[i].type);
3113       }
3114 
3115       printk("aic7xxx disabled at slot %d, ignored\n", slot);
3116     }
3117   }
3118 
3119   return (AIC_NONE);
3120 }
3121 
3122 /*+F*************************************************************************
3123  * Function:
3124  *   read_2840_seeprom
3125  *
3126  * Description:
3127  *   Reads the 2840 serial EEPROM and returns 1 if successful and 0 if
3128  *   not successful.
3129  *
3130  *   See read_seeprom (for the 2940) for the instruction set of the 93C46
3131  *   chip.
3132  *
3133  *   The 2840 interface to the 93C46 serial EEPROM is through the
3134  *   STATUS_2840 and SEECTL_2840 registers.  The CS_2840, CK_2840, and
3135  *   DO_2840 bits of the SEECTL_2840 register are connected to the chip
3136  *   select, clock, and data out lines respectively of the serial EEPROM.
3137  *   The DI_2840 bit of the STATUS_2840 is connected to the data in line
3138  *   of the serial EEPROM.  The EEPROM_TF bit of STATUS_2840 register is
3139  *   useful in that it gives us an 800 nsec timer.  After a read from the
3140  *   SEECTL_2840 register the timing flag is cleard and goes high 800 nsec
3141  *   later.
3142  *
3143  *-F*************************************************************************/
3144 static int
3145 read_2840_seeprom(int base, struct seeprom_config *sc)
     /*  */
3146 {
3147   int i = 0, k = 0;
3148   unsigned char temp;
3149   unsigned short checksum = 0;
3150   unsigned short *seeprom = (unsigned short *) sc;
3151   struct seeprom_cmd {
3152     unsigned char len;
3153     unsigned char bits[3];
3154   };
3155   struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
3156 
3157 #define CLOCK_PULSE(p) \
3158   while ((inb(STATUS_2840(base)) & EEPROM_TF) == 0)     \
3159   {                                             \
3160     ;  /* Do nothing */                         \
3161   }                                             \
3162   (void) inb(SEECTL_2840(base));
3163 
3164   /*
3165    * Read the first 32 registers of the seeprom.  For the 2840,
3166    * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers
3167    * but only the first 32 are used by Adaptec BIOS.  The loop
3168    * will range from 0 to 31.
3169    */
3170   for (k = 0; k < (sizeof(*sc) / 2); k++)
3171   {
3172     /*
3173      * Send chip select for one clock cycle.
3174      */
3175     outb(CK_2840 | CS_2840, SEECTL_2840(base));
3176     CLOCK_PULSE(base);
3177 
3178     /*
3179      * Now we're ready to send the read command followed by the
3180      * address of the 16-bit register we want to read.
3181      */
3182     for (i = 0; i < seeprom_read.len; i++)
3183     {
3184       temp = CS_2840 | seeprom_read.bits[i];
3185       outb(temp, SEECTL_2840(base));
3186       CLOCK_PULSE(base);
3187       temp = temp ^ CK_2840;
3188       outb(temp, SEECTL_2840(base));
3189       CLOCK_PULSE(base);
3190     }
3191     /*
3192      * Send the 6 bit address (MSB first, LSB last).
3193      */
3194     for (i = 5; i >= 0; i--)
3195     {
3196       temp = k;
3197       temp = (temp >> i) & 1;  /* Mask out all but lower bit. */
3198       temp = CS_2840 | temp;
3199       outb(temp, SEECTL_2840(base));
3200       CLOCK_PULSE(base);
3201       temp = temp ^ CK_2840;
3202       outb(temp, SEECTL_2840(base));
3203       CLOCK_PULSE(base);
3204     }
3205 
3206     /*
3207      * Now read the 16 bit register.  An initial 0 precedes the
3208      * register contents which begins with bit 15 (MSB) and ends
3209      * with bit 0 (LSB).  The initial 0 will be shifted off the
3210      * top of our word as we let the loop run from 0 to 16.
3211      */
3212     for (i = 0; i <= 16; i++)
3213     {
3214       temp = CS_2840;
3215       outb(temp, SEECTL_2840(base));
3216       CLOCK_PULSE(base);
3217       temp = temp ^ CK_2840;
3218       seeprom[k] = (seeprom[k] << 1) | (inb(STATUS_2840(base)) & DI_2840);
3219       outb(temp, SEECTL_2840(base));
3220       CLOCK_PULSE(base);
3221     }
3222     /*
3223      * The serial EEPROM has a checksum in the last word.  Keep a
3224      * running checksum for all words read except for the last
3225      * word.  We'll verify the checksum after all words have been
3226      * read.
3227      */
3228     if (k < (sizeof(*sc) / 2) - 1)
3229     {
3230       checksum = checksum + seeprom[k];
3231     }
3232 
3233     /*
3234      * Reset the chip select for the next command cycle.
3235      */
3236     outb(0, SEECTL_2840(base));
3237     CLOCK_PULSE(base);
3238     outb(CK_2840, SEECTL_2840(base));
3239     CLOCK_PULSE(base);
3240     outb(0, SEECTL_2840(base));
3241     CLOCK_PULSE(base);
3242   }
3243 
3244 #if 0
3245   printk("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
3246   printk("Serial EEPROM:");
3247   for (k = 0; k < (sizeof(*sc) / 2); k++)
3248   {
3249     if (((k % 8) == 0) && (k != 0))
3250     {
3251       printk("\n              ");
3252     }
3253     printk(" 0x%x", seeprom[k]);
3254   }
3255   printk("\n");
3256 #endif
3257 
3258   if (checksum != sc->checksum)
3259   {
3260     printk("aic7xxx: SEEPROM checksum error, ignoring SEEPROM settings.\n");
3261     return (0);
3262   }
3263 
3264   return (1);
3265 #undef CLOCK_PULSE
3266 }
3267 
3268 /*+F*************************************************************************
3269  * Function:
3270  *   read_seeprom
3271  *
3272  * Description:
3273  *   Reads the serial EEPROM and returns 1 if successful and 0 if
3274  *   not successful.
3275  *
3276  *   The instruction set of the 93C46 chip is as follows:
3277  *
3278  *               Start  OP
3279  *     Function   Bit  Code  Address    Data     Description
3280  *     -------------------------------------------------------------------
3281  *     READ        1    10   A5 - A0             Reads data stored in memory,
3282  *                                               starting at specified address
3283  *     EWEN        1    00   11XXXX              Write enable must preceed
3284  *                                               all programming modes
3285  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
3286  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
3287  *     ERAL        1    00   10XXXX              Erase all registers
3288  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
3289  *     EWDS        1    00   00XXXX              Disables all programming
3290  *                                               instructions
3291  *     *Note: A value of X for address is a don't care condition.
3292  *
3293  *   The 93C46 has a four wire interface: clock, chip select, data in, and
3294  *   data out.  In order to perform one of the above functions, you need
3295  *   to enable the chip select for a clock period (typically a minimum of
3296  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
3297  *   respectively.  While the chip select remains high, you can clock in
3298  *   the instructions (above) starting with the start bit, followed by the
3299  *   OP code, Address, and Data (if needed).  For the READ instruction, the
3300  *   requested 16-bit register contents is read from the data out line but
3301  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
3302  *   first).  The clock cycling from low to high initiates the next data
3303  *   bit to be sent from the chip.
3304  *
3305  *   The 7870 interface to the 93C46 serial EEPROM is through the SEECTL
3306  *   register.  After successful arbitration for the memory port, the
3307  *   SEECS bit of the SEECTL register is connected to the chip select.
3308  *   The SEECK, SEEDO, and SEEDI are connected to the clock, data out,
3309  *   and data in lines respectively.  The SEERDY bit of SEECTL is useful
3310  *   in that it gives us an 800 nsec timer.  After a write to the SEECTL
3311  *   register, the SEERDY goes high 800 nsec later.  The one exception
3312  *   to this is when we first request access to the memory port.  The
3313  *   SEERDY goes high to signify that access has been granted and, for
3314  *   this case, has no implied timing.
3315  *
3316  *-F*************************************************************************/
3317 static int
3318 read_seeprom(int base, int offset, struct seeprom_config *sc)
     /*  */
3319 {
3320   int i = 0, k;
3321   unsigned long timeout;
3322   unsigned char temp;
3323   unsigned short checksum = 0;
3324   unsigned short *seeprom = (unsigned short *) sc;
3325   struct seeprom_cmd {
3326     unsigned char len;
3327     unsigned char bits[3];
3328   };
3329   struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
3330 
3331 #define CLOCK_PULSE(p) \
3332   while ((inb(SEECTL(base)) & SEERDY) == 0)     \
3333   {                                             \
3334     ;  /* Do nothing */                         \
3335   }
3336 
3337   /*
3338    * Request access of the memory port.  When access is
3339    * granted, SEERDY will go high.  We use a 1 second
3340    * timeout which should be near 1 second more than
3341    * is needed.  Reason: after the 7870 chip reset, there
3342    * should be no contention.
3343    */
3344   outb(SEEMS, SEECTL(base));
3345   timeout = jiffies + 100;  /* 1 second timeout */
3346   while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
3347   {
3348     ; /* Do nothing!  Wait for access to be granted.  */
3349   }
3350   if ((inb(SEECTL(base)) & SEERDY) == 0)
3351   {
3352     outb(0, SEECTL(base));
3353     return (0);
3354   }
3355 
3356   /*
3357    * Read the first 32 registers of the seeprom.  For the 7870,
3358    * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers
3359    * but only the first 32 are used by Adaptec BIOS.  The loop
3360    * will range from 0 to 31.
3361    */
3362   for (k = 0; k < (sizeof(*sc) / 2); k++)
3363   {
3364     /*
3365      * Send chip select for one clock cycle.
3366      */
3367     outb(SEEMS | SEECK | SEECS, SEECTL(base));
3368     CLOCK_PULSE(base);
3369 
3370     /*
3371      * Now we're ready to send the read command followed by the
3372      * address of the 16-bit register we want to read.
3373      */
3374     for (i = 0; i < seeprom_read.len; i++)
3375     {
3376       temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
3377       outb(temp, SEECTL(base));
3378       CLOCK_PULSE(base);
3379       temp = temp ^ SEECK;
3380       outb(temp, SEECTL(base));
3381       CLOCK_PULSE(base);
3382     }
3383     /*
3384      * Send the 6 bit address (MSB first, LSB last).
3385      */
3386     for (i = 5; i >= 0; i--)
3387     {
3388       temp = k + offset;
3389       temp = (temp >> i) & 1;  /* Mask out all but lower bit. */
3390       temp = SEEMS | SEECS | (temp << 1);
3391       outb(temp, SEECTL(base));
3392       CLOCK_PULSE(base);
3393       temp = temp ^ SEECK;
3394       outb(temp, SEECTL(base));
3395       CLOCK_PULSE(base);
3396     }
3397 
3398     /*
3399      * Now read the 16 bit register.  An initial 0 precedes the
3400      * register contents which begins with bit 15 (MSB) and ends
3401      * with bit 0 (LSB).  The initial 0 will be shifted off the
3402      * top of our word as we let the loop run from 0 to 16.
3403      */
3404     for (i = 0; i <= 16; i++)
3405     {
3406       temp = SEEMS | SEECS;
3407       outb(temp, SEECTL(base));
3408       CLOCK_PULSE(base);
3409       temp = temp ^ SEECK;
3410       seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
3411       outb(temp, SEECTL(base));
3412       CLOCK_PULSE(base);
3413     }
3414 
3415     /*
3416      * The serial EEPROM has a checksum in the last word.  Keep a
3417      * running checksum for all words read except for the last
3418      * word.  We'll verify the checksum after all words have been
3419      * read.
3420      */
3421     if (k < (sizeof(*sc) / 2) - 1)
3422     {
3423       checksum = checksum + seeprom[k];
3424     }
3425 
3426     /*
3427      * Reset the chip select for the next command cycle.
3428      */
3429     outb(SEEMS, SEECTL(base));
3430     CLOCK_PULSE(base);
3431     outb(SEEMS | SEECK, SEECTL(base));
3432     CLOCK_PULSE(base);
3433     outb(SEEMS, SEECTL(base));
3434     CLOCK_PULSE(base);
3435   }
3436 
3437   /*
3438    * Release access to the memory port and the serial EEPROM.
3439    */
3440   outb(0, SEECTL(base));
3441 
3442 #if 0
3443   printk("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
3444   printk("Serial EEPROM:");
3445   for (k = 0; k < (sizeof(*sc) / 2); k++)
3446   {
3447     if (((k % 8) == 0) && (k != 0))
3448     {
3449       printk("\n              ");
3450     }
3451     printk(" 0x%x", seeprom[k]);
3452   }
3453   printk("\n");
3454 #endif
3455 
3456   if (checksum != sc->checksum)
3457   {
3458     printk("aic7xxx: SEEPROM checksum error, ignoring SEEPROM settings.\n");
3459     return (0);
3460   }
3461 
3462   return (1);
3463 #undef CLOCK_PULSE
3464 }
3465 
3466 /*+F*************************************************************************
3467  * Function:
3468  *   detect_maxscb
3469  *
3470  * Description:
3471  *   Return the maximum number of SCB's allowed for a given controller.
3472  *-F*************************************************************************/
3473 static int
3474 detect_maxscb(aha_type type, int base, int walk_scbs)
     /*  */
3475 {
3476   unsigned char sblkctl_reg, scb_byte;
3477   int maxscb = 0, i;
3478 
3479   switch (type)
3480   {
3481     case AIC_274x:
3482     case AIC_284x:
3483       /*
3484        * Check for Rev C or E boards. Rev E boards can supposedly have
3485        * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.
3486        * Until we know how to access more than 4 SCBs for the Rev E chips,
3487        * we limit them, along with the Rev C chips, to 4 SCBs.
3488        *
3489        * The Rev E boards have a read/write autoflush bit in the
3490        * SBLKCTL registor, while in the Rev C boards it is read only.
3491        */
3492       sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
3493       outb(sblkctl_reg, SBLKCTL(base));
3494       if (inb(SBLKCTL(base)) == sblkctl_reg)
3495       {
3496         /*
3497          * We detected a Rev E board.
3498          */
3499         printk("aic7770: Rev E and subsequent; using 4 SCB's\n");
3500         outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
3501         maxscb = 4;
3502       }
3503       else
3504       {
3505         printk("aic7770: Rev C and previous; using 4 SCB's\n");
3506         maxscb = 4;
3507       }
3508       break;
3509 
3510     case AIC_7850:
3511       maxscb = 3;
3512       break;
3513 
3514     case AIC_7870:
3515     case AIC_7880:
3516       maxscb = 16;
3517       break;
3518 
3519     case AIC_7872:
3520     case AIC_7882:
3521       /*
3522        * Is suppose to have 255 SCBs, but we'll walk the SCBs
3523        * looking for more if external RAM is detected.
3524        */
3525       maxscb = 16;
3526       break;
3527 
3528     case AIC_NONE:
3529       /*
3530        * This should never happen... But just in case.
3531        */
3532       break;
3533   }
3534   if (walk_scbs)
3535   {
3536     /*
3537      * This adapter has external SCB memory.
3538      * Walk the SCBs to determine how many there are.
3539      */
3540     i = 0;
3541     while (i < AIC7XXX_MAXSCB)
3542     {
3543       outb(i, SCBPTR(base));
3544       scb_byte = ~(inb(SCBARRAY(base)));  /* complement the byte */
3545       outb(scb_byte, SCBARRAY(base));     /* write it back out */
3546       if (inb(SCBARRAY(base)) != scb_byte)
3547       {
3548         break;
3549       }
3550       i++;
3551     }
3552     maxscb = i;         
3553   }
3554 
3555   return (maxscb);
3556 }
3557 
3558 /*+F*************************************************************************
3559  * Function:
3560  *   aic7xxx_register
3561  *
3562  * Description:
3563  *   Register a Adaptec aic7xxx chip SCSI controller with the kernel.
3564  *-F*************************************************************************/
3565 static int
3566 aic7xxx_register(Scsi_Host_Template *template,
     /*  */
3567                  struct aic7xxx_host_config *config)
3568 {
3569   static const char * board_name[] = {"", "274x", "284x", "7870", "7850",
3570                                       "7872", "7881"};
3571   int i;
3572   unsigned char sblkctl;
3573   int max_targets;
3574   int found = 1, base;
3575   int bios_disabled = 0;
3576   unsigned char target_settings;
3577   unsigned char scsi_conf, host_conf;
3578   int have_seeprom = 0;
3579   struct Scsi_Host *host;
3580   struct aic7xxx_host *p;
3581   struct seeprom_config sc;
3582 
3583   base = config->base;
3584 
3585   /*
3586    * Lock out other contenders for our i/o space.
3587    */
3588   request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
3589 
3590   switch (config->type)
3591   {
3592     case AIC_274x:
3593 #if 0
3594       printk("aha274x: HCNTRL:0x%x\n", inb(HCNTRL(base)));
3595 #endif
3596       /*
3597        * For some 274x boards, we must clear the CHIPRST bit
3598        * and pause the sequencer. For some reason, this makes
3599        * the driver work. For 284x boards, we give it a
3600        * CHIPRST just like the 294x boards.
3601        *
3602        * Use the BIOS settings to determine the interrupt
3603        * trigger type (level or edge) and use this value
3604        * for pausing and unpausing the sequencer.
3605        */
3606       config->unpause = (inb(HCNTRL(base)) & IRQMS) | INTEN;
3607       config->pause = config->unpause | PAUSE;
3608       config->extended = aic7xxx_extended;
3609 
3610       outb(config->pause | CHIPRST, HCNTRL(base));
3611       aic7xxx_delay(1);
3612       if (inb(HCNTRL(base)) & CHIPRST)
3613       {
3614         printk("aic7xxx_register: Chip reset not cleared; clearing manually.\n");
3615       }
3616       outb(config->pause, HCNTRL(base));
3617 
3618       /*
3619        * Just to be on the safe side with the 274x, we will re-read the irq
3620        * since there was some issue about reseting the board.
3621        */
3622       config->irq = inb(HA_INTDEF(base)) & 0x0F;
3623       if ((inb(HA_274_BIOSCTRL(base)) & BIOSMODE) == BIOSDISABLED)
3624       {
3625         bios_disabled = 1;
3626       }
3627       host_conf = inb(HA_HOSTCONF(base));
3628       config->busrtime = host_conf & 0x3C;
3629       /* XXX Is this valid for motherboard based controllers? */
3630       /* Setup the FIFO threshold and the bus off time */
3631       outb(host_conf & DFTHRSH, BUSSPD(base));
3632       outb((host_conf << 2) & BOFF, BUSTIME(base));
3633 
3634       /*
3635        * A reminder until this can be detected automatically.
3636        */
3637       printk("aha274x: Extended translation %sabled\n",
3638              config->extended ? "en" : "dis");
3639       break;
3640 
3641     case AIC_284x:
3642 #if 0
3643       printk("aha284x: HCNTRL:0x%x\n", inb(HCNTRL(base)));
3644 #endif
3645       outb(CHIPRST, HCNTRL(base));
3646       config->unpause = UNPAUSE_284X;
3647       config->pause = REQ_PAUSE; /* DWG would like to be like the rest */
3648       aic7xxx_delay(1);
3649       outb(config->pause, HCNTRL(base));
3650 
3651       config->extended = aic7xxx_extended;
3652       config->irq = inb(HA_INTDEF(base)) & 0x0F;
3653       if ((inb(HA_274_BIOSCTRL(base)) & BIOSMODE) == BIOSDISABLED)
3654       {
3655         bios_disabled = 1;
3656       }
3657       host_conf = inb(HA_HOSTCONF(base));
3658 
3659       printk("aha284x: Reading SEEPROM...");
3660       have_seeprom = read_2840_seeprom(base, &sc);
3661       if (!have_seeprom)
3662       {
3663         printk("aha284x: Unable to read SEEPROM\n");
3664         config->busrtime = host_conf & 0x3C;
3665       }
3666       else
3667       {
3668         printk("done.\n");
3669         config->extended = ((sc.bios_control & CFEXTEND) >> 7);
3670         config->scsi_id = (sc.brtime_id & CFSCSIID);
3671         config->parity = (sc.adapter_control & CFSPARITY) ?
3672                          AIC_ENABLED : AIC_DISABLED;
3673         config->low_term = (sc.adapter_control & CFSTERM) ?
3674                               AIC_ENABLED : AIC_DISABLED;
3675         config->high_term = (sc.adapter_control & CFWSTERM) ?
3676                               AIC_ENABLED : AIC_DISABLED;
3677         config->busrtime = ((sc.brtime_id & CFBRTIME) >> 8);
3678       }
3679       /* XXX Is this valid for motherboard based controllers? */
3680       /* Setup the FIFO threshold and the bus off time */
3681       outb(host_conf & DFTHRSH, BUSSPD(base));
3682       outb((host_conf << 2) & BOFF, BUSTIME(base));
3683 
3684       printk("aha284x: Extended translation %sabled\n",
3685              config->extended ? "en" : "dis");
3686       break;
3687 
3688     case AIC_7850:
3689     case AIC_7870:
3690     case AIC_7872:
3691     case AIC_7880:
3692     case AIC_7882:
3693 #if 0
3694       printk("aic%s HCNTRL:0x%x\n", board_name[config->type], inb(HCNTRL(base)));
3695 #endif
3696 
3697       outb(CHIPRST, HCNTRL(base));
3698       config->unpause = UNPAUSE_294X;
3699       config->pause = config->unpause | PAUSE;
3700       aic7xxx_delay(1);
3701       outb(config->pause, HCNTRL(base));
3702 
3703       config->extended = aic7xxx_extended;
3704       config->scsi_id = 7;
3705 
3706       printk("aic78xx: Reading SEEPROM...");
3707       have_seeprom = read_seeprom(base, config->chan_num * (sizeof(sc) / 2), &sc);
3708       if (!have_seeprom)
3709       {
3710         printk("aic78xx: Unable to read SEEPROM\n");
3711       }
3712       else
3713       {
3714         printk("done.\n");
3715         config->extended = ((sc.bios_control & CFEXTEND) >> 7);
3716         config->scsi_id = (sc.brtime_id & CFSCSIID);
3717         config->parity = (sc.adapter_control & CFSPARITY) ?
3718                          AIC_ENABLED : AIC_DISABLED;
3719         config->low_term = (sc.adapter_control & CFSTERM) ?
3720                               AIC_ENABLED : AIC_DISABLED;
3721         config->high_term = (sc.adapter_control & CFWSTERM) ?
3722                               AIC_ENABLED : AIC_DISABLED;
3723         config->busrtime = ((sc.brtime_id & CFBRTIME) >> 8);
3724         if (((config->type == AIC_7880) || (config->type == AIC_7882)) &&
3725             (sc.adapter_control & CFULTRAEN))
3726         {
3727           printk ("aic7xxx: Enabling support for Ultra SCSI speed.\n");
3728           config->ultra_enabled = TRUE;
3729         }
3730       }
3731 
3732       /*
3733        * XXX - force data fifo threshold to 100%. Why does this
3734        *       need to be done?
3735        */
3736       outb(inb(DSPCISTATUS(base)) | DFTHRESH, DSPCISTATUS(base));
3737       outb(config->scsi_id | DFTHRESH, HA_SCSICONF(base));
3738 
3739       /*
3740        * In case we are a wide card, place scsi ID in second conf byte.
3741        */
3742       outb(config->scsi_id, (HA_SCSICONF(base) + 1));
3743 
3744       printk("aic%s: Extended translation %sabled\n", board_name[config->type],
3745              config->extended ? "en" : "dis");
3746       break;
3747 
3748     default:
3749       panic("aic7xxx_register: internal error\n");
3750   }
3751 
3752   config->maxscb = detect_maxscb(config->type, base, config->walk_scbs);
3753 
3754   if ((config->type == AIC_274x) || (config->type == AIC_284x))
3755   {
3756     if (config->pause & IRQMS)
3757     {
3758       printk("aic7xxx: Using Level Sensitive Interrupts\n");
3759     }
3760     else
3761     {
3762       printk("aic7xxx: Using Edge Triggered Interrupts\n");
3763     }
3764   }
3765 
3766   /*
3767    * Read the bus type from the SBLKCTL register. Set the FLAGS
3768    * register in the sequencer for twin and wide bus cards.
3769    */
3770   sblkctl = inb(SBLKCTL(base));
3771   switch (sblkctl & SELBUS_MASK)
3772   {
3773     case SELSINGLE:     /* narrow/normal bus */
3774       config->scsi_id = inb(HA_SCSICONF(base)) & 0x07;
3775       config->bus_type = AIC_SINGLE;
3776       outb(SINGLE_BUS, HA_FLAGS(base));
3777       break;
3778 
3779     case SELWIDE:     /* Wide bus */
3780       config->scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
3781       config->bus_type = AIC_WIDE;
3782       printk("aic7xxx: Enabling wide channel of %s-Wide\n",
3783              board_name[config->type]);
3784       outb(WIDE_BUS, HA_FLAGS(base));
3785       break;
3786 
3787     case SELBUSB:     /* Twin bus */
3788       config->scsi_id = inb(HA_SCSICONF(base)) & 0x07;
3789 #ifdef AIC7XXX_TWIN_SUPPORT
3790       config->scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
3791       config->bus_type = AIC_TWIN;
3792       printk("aic7xxx: Enabled channel B of %s-Twin\n",
3793              board_name[config->type]);
3794       outb(TWIN_BUS, HA_FLAGS(base));
3795 #else
3796       config->bus_type = AIC_SINGLE;
3797       printk("aic7xxx: Channel B of %s-Twin will be ignored\n",
3798              board_name[config->type]);
3799       outb(0, HA_FLAGS(base));
3800 #endif
3801       break;
3802 
3803     default:
3804       printk("aic7xxx is an unsupported type 0x%x, please "
3805              "mail deang@ims.com\n", inb(SBLKCTL(base)));
3806       outb(0, HA_FLAGS(base));
3807       return (0);
3808   }
3809 
3810   /*
3811    * For the 294x cards, clearing DIAGLEDEN and DIAGLEDON, will
3812    * take the card out of diagnostic mode and make the host adatper
3813    * LED follow bus activity (will not always be on).
3814    */
3815   outb(sblkctl & ~(DIAGLEDEN | DIAGLEDON), SBLKCTL(base));
3816 
3817   /*
3818    * The IRQ level in i/o port 4 maps directly onto the real
3819    * IRQ number. If it's ok, register it with the kernel.
3820    *
3821    * NB. the Adaptec documentation says the IRQ number is only
3822    *     in the lower four bits; the ECU information shows the
3823    *     high bit being used as well. Which is correct?
3824    *
3825    * The 294x cards (PCI) get their interrupt from PCI BIOS.
3826    */
3827   if (((config->type == AIC_274x) || (config->type == AIC_284x)) &&
3828       (config->irq < 9 || config->irq > 15))
3829   {
3830     printk("aic7xxx uses unsupported IRQ level, ignoring.\n");
3831     return (0);
3832   }
3833 
3834   /*
3835    * Check the IRQ to see if it is shared by another aic7xxx
3836    * controller. If it is and sharing of IRQs is not defined,
3837    * then return 0 hosts found. If sharing of IRQs is allowed
3838    * or the IRQ is not shared by another host adapter, then
3839    * proceed.
3840    */
3841 #ifndef AIC7XXX_SHARE_IRQS
3842    if (aic7xxx_boards[config->irq] != NULL)
3843    {
3844      printk("aic7xxx_register: Sharing of IRQs is not configured.\n");
3845      return (0);
3846    }
3847 #endif
3848 
3849   /*
3850    * Print out debugging information before re-enabling
3851    * the card - a lot of registers on it can't be read
3852    * when the sequencer is active.
3853    */
3854   debug_config(config);
3855 
3856   /*
3857    * Before registry, make sure that the offsets of the
3858    * struct scatterlist are what the sequencer will expect,
3859    * otherwise disable scatter-gather altogether until someone
3860    * can fix it. This is important since the sequencer will
3861    * DMA elements of the SG array in while executing commands.
3862    */
3863   if (template->sg_tablesize != SG_NONE)
3864   {
3865     struct scatterlist sg;
3866 
3867     if (SG_STRUCT_CHECK(sg))
3868     {
3869       printk("aic7xxx warning: kernel scatter-gather "
3870              "structures changed, disabling it.\n");
3871       template->sg_tablesize = SG_NONE;
3872     }
3873   }
3874 
3875   /*
3876    * Register each "host" and fill in the returned Scsi_Host
3877    * structure as best we can. Some of the parameters aren't
3878    * really relevant for bus types beyond ISA, and none of the
3879    * high-level SCSI code looks at it anyway. Why are the fields
3880    * there? Also save the pointer so that we can find the
3881    * information when an IRQ is triggered.
3882    */
3883   host = scsi_register(template, sizeof(struct aic7xxx_host));
3884   host->can_queue = config->maxscb;
3885   host->cmd_per_lun = AIC7XXX_CMDS_PER_LUN;
3886   host->this_id = config->scsi_id;
3887   host->irq = config->irq;
3888   if (config->bus_type == AIC_WIDE)
3889   {
3890     host->max_id = 16;
3891   }
3892   if (config->bus_type == AIC_TWIN)
3893   {
3894     host->max_channel = 1;
3895   }
3896 
3897   p = (struct aic7xxx_host *) host->hostdata;
3898 
3899   /*
3900    * Initialize the scb array by setting the state to free.
3901    */
3902   for (i = 0; i < AIC7XXX_MAXSCB; i++)
3903   {
3904     p->scb_array[i].state = SCB_FREE;
3905     p->scb_array[i].next = NULL;
3906     p->scb_array[i].cmd = NULL;
3907   }
3908 
3909   p->isr_count = 0;
3910   p->a_scanned = 0;
3911   p->b_scanned = 0;
3912   p->base = base;
3913   p->maxscb = config->maxscb;
3914   p->numscb = 0;
3915   p->extended = config->extended;
3916   p->type = config->type;
3917   p->ultra_enabled = config->ultra_enabled;
3918   p->chan_num = config->chan_num;
3919   p->bus_type = config->bus_type;
3920   p->have_seeprom = have_seeprom;
3921   p->seeprom = sc;
3922   p->free_scb = NULL;
3923   p->next = NULL;
3924 
3925   p->unpause = config->unpause;
3926   p->pause = config->pause;
3927 
3928   if (aic7xxx_boards[config->irq] == NULL)
3929   {
3930     /*
3931      * Warning! This must be done before requesting the irq.  It is
3932      * possible for some boards to raise an interrupt as soon as
3933      * they are enabled.  So when we request the irq from the Linux
3934      * kernel, an interrupt is triggered immediately.  Therefore, we
3935      * must ensure the board data is correctly set before the request.
3936      */
3937     aic7xxx_boards[config->irq] = host;
3938 
3939     /*
3940      * Register IRQ with the kernel.
3941      */
3942     if (request_irq(config->irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
3943     {
3944       printk("aic7xxx couldn't register irq %d, ignoring\n", config->irq);
3945       aic7xxx_boards[config->irq] = NULL;
3946       return (0);
3947     }
3948   }
3949   else
3950   {
3951     /*
3952      * We have found a host adapter sharing an IRQ of a previously
3953      * registered host adapter. Add this host adapter's Scsi_Host
3954      * to the beginning of the linked list of hosts at the same IRQ.
3955      */
3956     p->next = aic7xxx_boards[config->irq];
3957     aic7xxx_boards[config->irq] = host;
3958   }
3959 
3960   /*
3961    * Load the sequencer program, then re-enable the board -
3962    * resetting the AIC-7770 disables it, leaving the lights
3963    * on with nobody home. On the PCI bus you *may* be home,
3964    * but then your mailing address is dynamically assigned
3965    * so no one can find you anyway :-)
3966    */
3967   printk("aic7xxx: Downloading sequencer code...");
3968   aic7xxx_loadseq(base);
3969 
3970   /*
3971    * Set Fast Mode and Enable the board
3972    */
3973   outb(FASTMODE, SEQCTL(base));
3974 
3975   if ((p->type == AIC_274x) || (p->type == AIC_284x))
3976   {
3977     outb(ENABLE, BCTL(base));
3978   }
3979 
3980   printk("done.\n");
3981 
3982   /*
3983    * Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels
3984    */
3985   if (p->bus_type == AIC_TWIN)
3986   {
3987     /*
3988      * Select Channel B.
3989      */
3990     outb((sblkctl & ~SELBUS_MASK) | SELBUSB, SBLKCTL(base));
3991 
3992     outb(config->scsi_id_b, SCSIID(base));
3993     scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
3994     outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
3995     outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3996     if (p->ultra_enabled)
3997     {
3998       outb(ULTRAEN, SXFRCTL0(base));
3999     }
4000 
4001     /*
4002      * Select Channel A
4003      */
4004     outb((sblkctl & ~SELBUS_MASK) | SELSINGLE, SBLKCTL(base));
4005   }
4006   outb(config->scsi_id, SCSIID(base));
4007   scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
4008   outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
4009   outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
4010   if (p->ultra_enabled)
4011   {
4012     outb(ULTRAEN, SXFRCTL0(base));
4013   }
4014 
4015   /*
4016    * Look at the information that board initialization or the board
4017    * BIOS has left us. In the lower four bits of each target's
4018    * scratch space any value other than 0 indicates that we should
4019    * initiate synchronous transfers. If it's zero, the user or the
4020    * BIOS has decided to disable synchronous negotiation to that
4021    * target so we don't activate the needsdtr flag.
4022    */
4023   p->needsdtr_copy = 0;
4024   p->sdtr_pending = 0;
4025   p->needwdtr_copy = 0;
4026   p->wdtr_pending = 0;
4027   if (p->bus_type == AIC_SINGLE)
4028   {
4029     max_targets = 8;
4030   }
4031   else
4032   {
4033     max_targets = 16;
4034   }
4035 
4036   /*
4037    * Grab the disconnection disable table and invert it for our needs
4038    */
4039   if (have_seeprom)
4040   {
4041     p->discenable = 0;
4042   }
4043   else
4044   {
4045     if (bios_disabled)
4046     {
4047       printk("aic7xxx : Host Adapter Bios disabled. Using default SCSI "
4048              "device parameters\n");
4049       p->discenable = 0xFFFF;
4050     }
4051     else
4052     {
4053       p->discenable = ~((inb(HA_DISC_DSB(base + 1)) << 8) |
4054           inb(HA_DISC_DSB(base)));
4055     }
4056   }
4057 
4058   for (i = 0; i < max_targets; i++)
4059   {
4060     if (have_seeprom)
4061     {
4062       target_settings = ((sc.device_flags[i] & CFXFER) << 4);
4063       if (sc.device_flags[i] & CFSYNCH)
4064       {
4065         p->needsdtr_copy |= (0x01 << i);
4066       }
4067       if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
4068       {
4069         p->needwdtr_copy |= (0x01 << i);
4070       }
4071       if (sc.device_flags[i] & CFDISC)
4072       {
4073         p->discenable |= (0x01 << i);
4074       }
4075     }
4076     else
4077     {
4078       target_settings = inb(HA_TARG_SCRATCH(base) + i);
4079       if (target_settings & 0x0F)
4080       {
4081         p->needsdtr_copy |= (0x01 << i);
4082         /*
4083          * Default to asynchronous transfers (0 offset)
4084          */
4085         target_settings &= 0xF0;
4086       }
4087       /*
4088        * If we are not wide, forget WDTR. This makes the driver
4089        * work on some cards that don't leave these fields cleared
4090        * when BIOS is not installed.
4091        */
4092       if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
4093       {
4094         p->needwdtr_copy |= (0x01 << i);
4095         target_settings &= 0x7F;
4096       }
4097     }
4098     outb(target_settings, (HA_TARG_SCRATCH(base) + i));
4099   }
4100 
4101   p->needsdtr = p->needsdtr_copy;
4102   p->needwdtr = p->needwdtr_copy;
4103 #if 0
4104   printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
4105   printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
4106 #endif
4107 
4108   /*
4109    * Clear the control byte for every SCB so that the sequencer
4110    * doesn't get confused and think that one of them is valid
4111    */
4112   for (i = 0; i < config->maxscb; i++)
4113   {
4114     outb(i, SCBPTR(base));
4115     outb(0, SCBARRAY(base));
4116   }
4117 
4118   /*
4119    * For reconnecting targets, the sequencer code needs to
4120    * know how many SCBs it has to search through.
4121    */
4122   outb(config->maxscb, HA_SCBCOUNT(base));
4123 
4124   /*
4125    * Clear the active flags - no targets are busy.
4126    */
4127   outb(0, HA_ACTIVE0(base));
4128   outb(0, HA_ACTIVE1(base));
4129 
4130   /*
4131    * We don't have any waiting selections
4132    */
4133   outb(SCB_LIST_NULL, WAITING_SCBH(base));
4134   outb(SCB_LIST_NULL, WAITING_SCBT(base));
4135 
4136   /*
4137    * Reset the SCSI bus. Is this necessary?
4138    *   There may be problems for a warm boot without resetting
4139    *   the SCSI bus. Either BIOS settings in scratch RAM
4140    *   will not get reinitialized, or devices may stay at
4141    *   previous negotiated settings (SDTR and WDTR) while
4142    *   the driver will think that no negotiations have been
4143    *   performed.
4144    *
4145    * Some devices need a long time to "settle" after a SCSI
4146    * bus reset.
4147    */
4148 
4149   if (!aic7xxx_no_reset)
4150   {
4151     printk("aic7xxx: Resetting the SCSI bus...");
4152     if (p->bus_type == AIC_TWIN)
4153     {
4154       /*
4155        * Select Channel B.
4156        */
4157       outb((sblkctl & ~SELBUS_MASK) | SELBUSB, SBLKCTL(base));
4158 
4159       outb(SCSIRSTO, SCSISEQ(base));
4160       udelay(1000);
4161       outb(0, SCSISEQ(base));
4162 
4163       /*
4164        * Select Channel A.
4165        */
4166       outb((sblkctl & ~SELBUS_MASK) | SELSINGLE, SBLKCTL(base));
4167     }
4168 
4169     outb(SCSIRSTO, SCSISEQ(base));
4170     udelay(1000);
4171     outb(0, SCSISEQ(base));
4172 
4173     aic7xxx_delay(AIC7XXX_RESET_DELAY);
4174 
4175     printk("done.\n");
4176   }
4177 
4178   /*
4179    * Unpause the sequencer before returning and enable
4180    * interrupts - we shouldn't get any until the first
4181    * command is sent to us by the high-level SCSI code.
4182    */
4183   UNPAUSE_SEQUENCER(p);
4184   return (found);
4185 }
4186 
4187 /*+F*************************************************************************
4188  * Function:
4189  *   aic7xxx_detect
4190  *
4191  * Description:
4192  *   Try to detect and register an Adaptec 7770 or 7870 SCSI controller.
4193  *-F*************************************************************************/
4194 int
4195 aic7xxx_detect(Scsi_Host_Template *template)
     /*  */
4196 {
4197   aha_type type = AIC_NONE;
4198   int found = 0, slot, base;
4199   unsigned char irq = 0;
4200   int i;
4201   struct aic7xxx_host_config config;
4202 
4203   template->proc_dir = &proc_scsi_aic7xxx;
4204   config.chan_num = 0;
4205 
4206   /*
4207    * Since we may allow sharing of IRQs, it is imperative
4208    * that we "null-out" the aic7xxx_boards array. It is
4209    * not guaranteed to be initialized to 0 (NULL). We use
4210    * a NULL entry to indicate that no prior hosts have
4211    * been found/registered for that IRQ.
4212    */
4213   for (i = 0; i <= MAXIRQ; i++)
4214   {
4215     aic7xxx_boards[i] = NULL;
4216   }
4217 
4218   /*
4219    * Initialize the spurious count to 0.
4220    */
4221   aic7xxx_spurious_count = 0;
4222 
4223   /*
4224    * EISA/VL-bus card signature probe.
4225    */
4226   for (slot = MINSLOT; slot <= MAXSLOT; slot++)
4227   {
4228     base = SLOTBASE(slot);
4229 
4230     if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
4231     {
4232       /*
4233        * Some other driver has staked a
4234        * claim to this i/o region already.
4235        */
4236       continue;
4237     }
4238 
4239     type = aic7xxx_probe(slot, HID0(base));
4240     if (type != AIC_NONE)
4241     {
4242       /*
4243        * We found a card, allow 1 spurious interrupt.
4244        */
4245       aic7xxx_spurious_count = 1;
4246 
4247 #if 0
4248       printk("aic7xxx: HCNTRL:0x%x\n", inb(HCNTRL(base)));
4249       outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
4250 #endif
4251 
4252       /*
4253        * We "find" a AIC-7770 if we locate the card
4254        * signature and we can set it up and register
4255        * it with the kernel without incident.
4256        */
4257       config.type = type;
4258       config.base = base;
4259       config.irq = irq;
4260       config.parity = AIC_UNKNOWN;
4261       config.low_term = AIC_UNKNOWN;
4262       config.high_term = AIC_UNKNOWN;
4263       config.busrtime = 0;
4264       config.walk_scbs = FALSE;
4265       config.ultra_enabled = FALSE;
4266       found += aic7xxx_register(template, &config);
4267 
4268       /*
4269        * Disallow spurious interrupts.
4270        */
4271       aic7xxx_spurious_count = 0;
4272     }
4273   }
4274 
4275 #ifdef CONFIG_PCI
4276 
4277   /*
4278    * PCI-bus probe.
4279    */
4280   if (pcibios_present())
4281   {
4282     int error;
4283     int done = 0;
4284     unsigned int io_port;
4285     unsigned short index = 0;
4286     unsigned char pci_bus, pci_device_fn;
4287     unsigned char devrevid, devconfig, devstatus;
4288     char rev_id[] = {'B', 'C', 'D'};
4289 
4290     while (!done)
4291     {
4292       if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4293                                 PCI_DEVICE_ID_ADAPTEC_7870,
4294                                 index, &pci_bus, &pci_device_fn)) ||
4295            (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4296                                 PCI_DEVICE_ID_ADAPTEC_7871,
4297                                 index, &pci_bus, &pci_device_fn)))
4298       {
4299         type = AIC_7870;
4300       }
4301       else
4302       {
4303         if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4304                                 PCI_DEVICE_ID_ADAPTEC_7850,
4305                                 index, &pci_bus, &pci_device_fn))
4306         {
4307           type = AIC_7850;
4308         }
4309         else
4310         {
4311           if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4312                                   PCI_DEVICE_ID_ADAPTEC_7872,
4313                                   index, &pci_bus, &pci_device_fn))
4314           {
4315             type = AIC_7872;
4316             config.chan_num = number_of_3940s & 0x1;
4317             number_of_3940s++;
4318           }
4319           else
4320           {
4321             if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4322                                      PCI_DEVICE_ID_ADAPTEC_7881,
4323                                      index, &pci_bus, &pci_device_fn)) ||
4324                 (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4325                                      PCI_DEVICE_ID_ADAPTEC_7880,
4326                                      index, &pci_bus, &pci_device_fn)))
4327             {
4328               type = AIC_7880;
4329             }
4330             else
4331             {
4332               if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4333                                       PCI_DEVICE_ID_ADAPTEC_7882,
4334                                       index, &pci_bus, &pci_device_fn))
4335               {
4336                 type = AIC_7882;
4337               }
4338               else
4339               {
4340                 type = AIC_NONE;
4341                 done = 1;
4342               }
4343             }
4344           }
4345         }
4346       }
4347 
4348       if (!done)
4349       {
4350         /*
4351          * Read esundry information from PCI BIOS.
4352          */
4353         error = pcibios_read_config_dword(pci_bus, pci_device_fn,
4354                                           PCI_BASE_ADDRESS_0, &io_port);
4355         if (error)
4356         {
4357           panic("aic7xxx_detect: error 0x%x reading i/o port.\n", error);
4358         }
4359 
4360         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4361                                          PCI_INTERRUPT_LINE, &irq);
4362         if (error)
4363         {
4364           panic("aic7xxx_detect: error %d reading irq.\n", error);
4365         }
4366 
4367         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4368                                          DEVREVID, &devrevid);
4369         if (error)
4370         {
4371           panic("aic7xxx_detect: error %d reading device revision id.\n", error);
4372         }
4373 
4374         if (devrevid < 3)
4375         {
4376           printk("aic7xxx_detect: AIC-7870 Rev %c\n", rev_id[devrevid]);
4377         }
4378 
4379         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4380                                          DEVCONFIG, &devconfig);
4381         if (error)
4382         {
4383           panic("aic7xxx_detect: error %d reading device configuration.\n", error);
4384         }
4385 
4386         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4387                                          DEVSTATUS, &devstatus);
4388         if (error)
4389         {
4390           panic("aic7xxx_detect: error %d reading device status.\n", error);
4391         }
4392 
4393         printk("aic7xxx_detect: devconfig 0x%x, devstatus 0x%x\n",
4394                devconfig, devstatus);
4395 
4396         /*
4397          * Make the base I/O register look like EISA and VL-bus.
4398          */
4399         base = io_port - 0xC01;
4400 
4401         /*
4402          * I don't think we need to bother with allowing
4403          * spurious interrupts for the 787x/7850, but what
4404          * the hey.
4405          */
4406         aic7xxx_spurious_count = 1;
4407 
4408         config.type = type;
4409         config.base = base;
4410         config.irq = irq;
4411         config.parity = AIC_UNKNOWN;
4412         config.low_term = AIC_UNKNOWN;
4413         config.high_term = AIC_UNKNOWN;
4414         config.busrtime = 0;
4415         config.walk_scbs = FALSE;
4416         config.ultra_enabled = FALSE;
4417         if ((devstatus & RAMPSM) || (devconfig & SCBRAMSEL) ||
4418             (type == AIC_7872))
4419         {
4420           config.walk_scbs = TRUE;
4421         }
4422         found += aic7xxx_register(template, &config);
4423 
4424         /*
4425          * Disable spurious interrupts.
4426          */
4427         aic7xxx_spurious_count = 0;
4428 
4429         index++;
4430       }
4431     }
4432   }
4433 #endif CONFIG_PCI
4434 
4435   template->name = aic7xxx_info(NULL);
4436   return (found);
4437 }
4438 
4439 
4440 /*+F*************************************************************************
4441  * Function:
4442  *   aic7xxx_buildscb
4443  *
4444  * Description:
4445  *   Build a SCB.
4446  *-F*************************************************************************/
4447 static void
4448 aic7xxx_buildscb(struct aic7xxx_host *p,
     /*  */
4449                  Scsi_Cmnd *cmd,
4450                  struct aic7xxx_scb *scb)
4451 {
4452   void *addr;
4453   unsigned short mask;
4454   struct scatterlist *sg;
4455 
4456   /*
4457    * Setup the control byte if we need negotiation and have not
4458    * already requested it.
4459    */
4460 #ifdef AIC7XXX_TAGGED_QUEUEING
4461   if (cmd->device->tagged_supported)
4462   {
4463     if (cmd->device->tagged_queue == 0)
4464     {
4465       printk("aic7xxx_buildscb: Enabling tagged queuing for target %d, "
4466              "channel %d\n", cmd->target, cmd->channel);
4467       cmd->device->tagged_queue = 1;
4468       cmd->device->current_tag = 1;  /* enable tagging */
4469     }
4470     cmd->tag = cmd->device->current_tag;
4471     cmd->device->current_tag++;
4472     scb->control |= SCB_TE;
4473   }
4474 #endif
4475   mask = (0x01 << (cmd->target | (cmd->channel << 3)));
4476   if (p->discenable & mask)
4477   {
4478     scb->control |= SCB_DISCENB;
4479   }
4480   if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
4481   {
4482     p->wdtr_pending |= mask;
4483     scb->control |= SCB_NEEDWDTR;
4484 #if 0
4485     printk("Sending WDTR request to target %d.\n", cmd->target);
4486 #endif
4487   }
4488   else
4489   {
4490     if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
4491     {
4492       p->sdtr_pending |= mask;
4493       scb->control |= SCB_NEEDSDTR;
4494 #if 0
4495       printk("Sending SDTR request to target %d.\n", cmd->target);
4496 #endif
4497     }
4498   }
4499 
4500 #if 0
4501   printk("aic7xxx_queue: target %d, cmd 0x%x (size %u), wdtr 0x%x, mask 0x%x\n",
4502          cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
4503 #endif
4504   scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
4505         ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
4506 
4507   /*
4508    * The interpretation of request_buffer and request_bufflen
4509    * changes depending on whether or not use_sg is zero; a
4510    * non-zero use_sg indicates the number of elements in the
4511    * scatter-gather array.
4512    */
4513 
4514   /*
4515    * XXX - this relies on the host data being stored in a
4516    *       little-endian format.
4517    */
4518   addr = cmd->cmnd;
4519   scb->SCSI_cmd_length = cmd->cmd_len;
4520   memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
4521 
4522   if (cmd->use_sg)
4523   {
4524 #if 0
4525     debug("aic7xxx_buildscb: SG used, %d segments, length %u\n",
4526            cmd->use_sg, length);
4527 #endif
4528     scb->SG_segment_count = cmd->use_sg;
4529     memcpy(scb->SG_list_pointer, &cmd->request_buffer,
4530            sizeof(scb->SG_list_pointer));
4531     memcpy(&sg, &cmd->request_buffer, sizeof(sg));
4532     memcpy(scb->data_pointer, &(sg[0].address), sizeof(scb->data_pointer));
4533     scb->data_count[0] = sg[0].length & 0xFF;
4534     scb->data_count[1] = (sg[0].length >> 8) & 0xFF;
4535     scb->data_count[2] = (sg[0].length >> 16) & 0xFF;
4536   }
4537   else
4538   {
4539 #if 0
4540   debug("aic7xxx_buildscb: Creating scatterlist, addr=0x%lx, length=%d.\n",
4541         (unsigned long) cmd->request_buffer, cmd->request_bufflen);
4542 #endif
4543     if (cmd->request_bufflen == 0)
4544     {
4545       /*
4546        * In case the higher level SCSI code ever tries to send a zero
4547        * length command, ensure the SCB indicates no data.  The driver
4548        * will interpret a zero length command as a Bus Device Reset.
4549        */
4550       scb->SG_segment_count = 0;
4551       memset(scb->SG_list_pointer, 0, sizeof(scb->SG_list_pointer));
4552       memset(scb->data_pointer, 0, sizeof(scb->data_pointer));
4553       memset(scb->data_count, 0, sizeof(scb->data_count));
4554     }
4555     else
4556     {
4557       scb->SG_segment_count = 1;
4558       scb->sg.address = (char *) cmd->request_buffer;
4559       scb->sg.length = cmd->request_bufflen;
4560       addr = &scb->sg;
4561       memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
4562       scb->data_count[0] = scb->sg.length & 0xFF;
4563       scb->data_count[1] = (scb->sg.length >> 8) & 0xFF;
4564       scb->data_count[2] = (scb->sg.length >> 16) & 0xFF;
4565       memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
4566     }
4567   }
4568 }
4569 
4570 /*+F*************************************************************************
4571  * Function:
4572  *   aic7xxx_queue
4573  *
4574  * Description:
4575  *   Queue a SCB to the controller.
4576  *-F*************************************************************************/
4577 int
4578 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
     /*  */
4579 {
4580   long flags;
4581   struct aic7xxx_host *p;
4582   struct aic7xxx_scb *scb;
4583   unsigned char curscb;
4584 
4585   p = (struct aic7xxx_host *) cmd->host->hostdata;
4586 
4587   /*
4588    * Check to see if channel was scanned.
4589    */
4590   if (!p->a_scanned && (cmd->channel == 0))
4591   {
4592     printk("aic7xxx: Scanning channel A for devices.\n");
4593     p->a_scanned = 1;
4594   }
4595   else
4596   {
4597     if (!p->b_scanned && (cmd->channel == 1))
4598     {
4599       printk("aic7xxx: Scanning channel B for devices.\n");
4600       p->b_scanned = 1;
4601     }
4602   }
4603 
4604 #if 0
4605   debug("aic7xxx_queue: cmd 0x%x (size %u), target %d, channel %d, lun %d\n",
4606         cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
4607         cmd->lun & 0x07);
4608 #endif
4609 
4610   /*
4611    * This is a critical section, since we don't want the
4612    * interrupt routine mucking with the host data or the
4613    * card. Since the kernel documentation is vague on
4614    * whether or not we are in a cli/sti pair already, save
4615    * the flags to be on the safe side.
4616    */
4617   save_flags(flags);
4618   cli();
4619 
4620   /*
4621    * Find a free slot in the SCB array to load this command
4622    * into. Since can_queue is set to the maximum number of
4623    * SCBs for the card, we should always find one.
4624    *
4625    * First try to find an scb in the free list. If there are
4626    * none in the free list, then check the current number of
4627    * of scbs and take an unused one from the scb array.
4628    */
4629   scb = p->free_scb;
4630   if (scb != NULL)
4631   { /* found one in the free list */
4632     p->free_scb = scb->next;   /* remove and update head of list */
4633     /*
4634      * Warning! For some unknown reason, the scb at the head
4635      * of the free list is not the same address that it should
4636      * be. That's why we set the scb pointer taken by the
4637      * position in the array. The scb at the head of the list
4638      * should match this address, but it doesn't.
4639      */
4640     scb = &(p->scb_array[scb->position]);
4641     scb->control = 0;
4642     scb->state = SCB_ACTIVE;
4643   }
4644   else
4645   {
4646     if (p->numscb >= p->maxscb)
4647     {
4648       panic("aic7xxx_queue: couldn't find a free scb\n");
4649     }
4650     else
4651     {
4652       /*
4653        * Initialize the scb within the scb array. The
4654        * position within the array is the position on
4655        * the board that it will be loaded.
4656        */
4657       scb = &(p->scb_array[p->numscb]);
4658       memset(scb, 0, sizeof(*scb));
4659 
4660       scb->position = p->numscb;
4661       p->numscb++;
4662       scb->state = SCB_ACTIVE;
4663       scb->next_waiting = SCB_LIST_NULL;
4664       memcpy(scb->host_scb, &scb, sizeof(scb));
4665       scb->control = SCB_NEEDDMA;
4666       PAUSE_SEQUENCER(p);
4667       curscb = inb(SCBPTR(p->base));
4668       outb(scb->position, SCBPTR(p->base));
4669       aic7xxx_putscb_dma(p->base, scb);
4670       outb(curscb, SCBPTR(p->base));
4671       UNPAUSE_SEQUENCER(p);
4672       scb->control = 0;
4673     }
4674   }
4675 
4676   scb->cmd = cmd;
4677   aic7xxx_position(cmd) = scb->position;
4678 #if 0
4679   debug_scb(scb);
4680 #endif;
4681 
4682   /*
4683    * Construct the SCB beforehand, so the sequencer is
4684    * paused a minimal amount of time.
4685    */
4686   aic7xxx_buildscb(p, cmd, scb);
4687 
4688 #if 0
4689   if (scb != &p->scb_array[scb->position])
4690   {
4691     printk("aic7xxx_queue: address of scb by position does not match scb address\n");
4692   }
4693   printk("aic7xxx_queue: SCB pos=%d, cmdptr=0x%x, state=%d, freescb=0x%x\n",
4694          scb->position, (unsigned int) scb->cmd,
4695          scb->state, (unsigned int) p->free_scb);
4696 #endif
4697   /*
4698    * Pause the sequencer so we can play with its registers -
4699    * wait for it to acknowledge the pause.
4700    *
4701    * XXX - should the interrupts be left on while doing this?
4702    */
4703   PAUSE_SEQUENCER(p);
4704 
4705   /*
4706    * Save the SCB pointer and put our own pointer in - this
4707    * selects one of the four banks of SCB registers. Load
4708    * the SCB, then write its pointer into the queue in FIFO
4709    * and restore the saved SCB pointer.
4710    */
4711   aic7xxx_putscb(p->base, scb);
4712 
4713   /*
4714    * Make sure the Scsi_Cmnd pointer is saved, the struct it
4715    * points to is set up properly, and the parity error flag
4716    * is reset, then unpause the sequencer and watch the fun
4717    * begin.
4718    */
4719   cmd->scsi_done = fn;
4720   aic7xxx_error(cmd) = DID_OK;
4721   aic7xxx_status(cmd) = 0;
4722   scb->timer_status = 0x0;
4723   cmd->result = 0;
4724   memset(&cmd->sense_buffer, 0, sizeof(cmd->sense_buffer));
4725 
4726   UNPAUSE_SEQUENCER(p);
4727 #if 0
4728   printk("aic7xxx_queue: After - cmd = 0x%lx, scb->cmd = 0x%lx, pos = %d\n",
4729          (long) cmd, (long) scb->cmd, scb->position);
4730 #endif;
4731   restore_flags(flags);
4732   return (0);
4733 }
4734 
4735 /*+F*************************************************************************
4736  * Function:
4737  *   aic7xxx_abort_scb
4738  *
4739  * Description:
4740  *   Abort an scb.  If the scb has not previously been aborted, then
4741  *   we attempt to send a BUS_DEVICE_RESET message to the target.  If
4742  *   the scb has previously been unsuccessfully aborted, then we will
4743  *   reset the channel and have all devices renegotiate.
4744  *-F*************************************************************************/
4745 static void
4746 aic7xxx_abort_scb(struct aic7xxx_host *p, struct aic7xxx_scb *scb)
     /*  */
4747 {
4748   int base = p->base;
4749   int found = 0;
4750   char channel = scb->target_channel_lun & SELBUSB ? 'B': 'A';
4751 
4752   /*
4753    * Ensure that the card doesn't do anything
4754    * behind our back.
4755    */
4756   PAUSE_SEQUENCER(p);
4757 
4758   /*
4759    * First, determine if we want to do a bus reset or simply a bus device
4760    * reset.  If this is the first time that a transaction has timed out,
4761    * just schedule a bus device reset.  Otherwise, we reset the bus and
4762    * abort all pending I/Os on that bus.
4763    */
4764   if (scb->state & SCB_ABORTED)
4765   {
4766     /*
4767      * Been down this road before.  Do a full bus reset.
4768      */
4769     found = aic7xxx_reset_channel(p, channel, scb->position);
4770   }
4771   else
4772   {
4773     unsigned char active_scb, control;
4774     struct aic7xxx_scb *active_scbp;
4775 
4776     /*
4777      * Send a Bus Device Reset Message:
4778      * The target we select to send the message to may be entirely
4779      * different than the target pointed to by the scb that timed
4780      * out.  If the command is in the QINFIFO or the waiting for
4781      * selection list, its not tying up the bus and isn't responsible
4782      * for the delay so we pick off the active command which should
4783      * be the SCB selected by SCBPTR.  If its disconnected or active,
4784      * we device reset the target scbp points to.  Although it may
4785      * be that this target is not responsible for the delay, it may
4786      * may also be that we're timing out on a command that just takes
4787      * too much time, so we try the bus device reset there first.
4788      */
4789     active_scb = inb(SCBPTR(base));
4790     active_scbp = &(p->scb_array[active_scb]);
4791     control = inb(SCBARRAY(base));
4792 
4793     /*
4794      * Test to see if scbp is disconnected
4795      */
4796     outb(scb->position, SCBPTR(base));
4797     if (inb(SCBARRAY(base)) & SCB_DIS)
4798     {
4799       scb->state |= (SCB_DEVICE_RESET | SCB_ABORTED);
4800       scb->SG_segment_count = 0;
4801       memset(scb->SG_list_pointer, 0, sizeof(scb->SG_list_pointer));
4802       memset(scb->data_pointer, 0, sizeof(scb->data_pointer));
4803       memset(scb->data_count, 0, sizeof(scb->data_count));
4804       outb(SCBAUTO, SCBCNT(base));
4805       asm volatile("cld\n\t"
4806                    "rep\n\t"
4807                    "outsb"
4808                    : /* no output */
4809                    :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
4810                    :"si", "cx", "dx");
4811       outb(0, SCBCNT(base));
4812       aic7xxx_add_waiting_scb(base, scb, LIST_SECOND);
4813       aic7xxx_scb_tsleep(p, scb, 2 * HZ);  /* unpauses the sequencer */
4814     }
4815     else
4816     {
4817       /*
4818        * Is the active SCB really active?
4819        */
4820       if ((active_scbp->state & SCB_ACTIVE) && (control & SCB_NEEDDMA))
4821       {
4822         unsigned char flags = inb(HA_FLAGS(base));
4823         if (flags & ACTIVE_MSG)
4824         {
4825           /*
4826            * If we're in a message phase, tacking on another message
4827            * may confuse the target totally. The bus is probably wedged,
4828            * so reset the channel.
4829            */
4830           channel = (active_scbp->target_channel_lun & SELBUSB) ? 'B': 'A';
4831           aic7xxx_reset_channel(p, channel, scb->position);
4832         }
4833         else
4834         {
4835           /*
4836            * Load the message buffer and assert attention.
4837            */
4838           active_scbp->state |= (SCB_DEVICE_RESET | SCB_ABORTED);
4839           outb(flags | ACTIVE_MSG, HA_FLAGS(base));
4840           outb(1, HA_MSG_LEN(base));
4841           outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
4842           if (active_scbp->target_channel_lun != scb->target_channel_lun)
4843           {
4844             /*
4845              * XXX - We would like to increment the timeout on scb, but
4846              *       access to that routine is denied because it is hidden
4847              *       in scsi.c.  If we were able to do this, it would give
4848              *       scb a new lease on life.
4849              */
4850             ;
4851           }
4852           aic7xxx_scb_tsleep(p, active_scbp, 2 * HZ);
4853         }
4854       }
4855       else
4856       {
4857         /*
4858          * No active command to single out, so reset
4859          * the bus for the timed out target.
4860          */
4861         aic7xxx_reset_channel(p, channel, scb->position);
4862       }
4863     }
4864   }
4865 }
4866 
4867 /*+F*************************************************************************
4868  * Function:
4869  *   aic7xxx_abort
4870  *
4871  * Description:
4872  *   Abort the current SCSI command(s).
4873  *-F*************************************************************************/
4874 int
4875 aic7xxx_abort(Scsi_Cmnd *cmd)
     /*  */
4876 {
4877   struct aic7xxx_scb  *scb;
4878   struct aic7xxx_host *p;
4879   long flags;
4880 
4881   p = (struct aic7xxx_host *) cmd->host->hostdata;
4882   scb = &(p->scb_array[aic7xxx_position(cmd)]);
4883 
4884   save_flags(flags);
4885   cli();
4886 
4887   if (scb->state & SCB_ACTIVE)
4888   {
4889     if (scb->state & SCB_IMMED)
4890     {
4891       /*
4892        * Don't know how set the number of retries to 0.
4893        */
4894       /* cmd->retries = 0; */
4895       aic7xxx_done (p, scb);
4896     }
4897     else
4898     {
4899       /*
4900        * Abort the operation.
4901        */
4902       aic7xxx_abort_scb(p, scb);
4903     }
4904   }
4905   restore_flags(flags);
4906   return (0);
4907 }
4908 
4909 /*+F*************************************************************************
4910  * Function:
4911  *   aic7xxx_reset
4912  *
4913  * Description:
4914  *   Resetting the bus always succeeds - is has to, otherwise the
4915  *   kernel will panic! Try a surgical technique - sending a BUS
4916  *   DEVICE RESET message - on the offending target before pulling
4917  *   the SCSI bus reset line.
4918  *-F*************************************************************************/
4919 int
4920 aic7xxx_reset(Scsi_Cmnd *cmd)
     /*  */
4921 {
4922   return (aic7xxx_abort(cmd));
4923 }
4924 
4925 /*+F*************************************************************************
4926  * Function:
4927  *   aic7xxx_biosparam
4928  *
4929  * Description:
4930  *   Return the disk geometry for the given SCSI device.
4931  *-F*************************************************************************/
4932 int
4933 aic7xxx_biosparam(Disk *disk, kdev_t dev, int geom[])
     /*  */
4934 {
4935   int heads, sectors, cylinders;
4936   struct aic7xxx_host *p;
4937 
4938   p = (struct aic7xxx_host *) disk->device->host->hostdata;
4939 
4940   /*
4941    * XXX - if I could portably find the card's configuration
4942    *       information, then this could be autodetected instead
4943    *       of left to a boot-time switch.
4944    */
4945   heads = 64;
4946   sectors = 32;
4947   cylinders = disk->capacity / (heads * sectors);
4948 
4949   if (p->extended && cylinders > 1024)
4950   {
4951     heads = 255;
4952     sectors = 63;
4953     cylinders = disk->capacity / (255 * 63);
4954   }
4955 
4956   geom[0] = heads;
4957   geom[1] = sectors;
4958   geom[2] = cylinders;
4959 
4960   return (0);
4961 }
4962 
4963 #include "aic7xxx_proc.c"
4964 
4965 #ifdef MODULE
4966 /* Eventually this will go into an include file, but this will be later */
4967 Scsi_Host_Template driver_template = AIC7XXX;
4968 
4969 #include "scsi_module.c"
4970 #endif
4971 
4972 /*
4973  * Overrides for Emacs so that we almost follow Linus's tabbing style.
4974  * Emacs will notice this stuff at the end of the file and automatically
4975  * adjust the settings for this buffer only.  This must remain at the end
4976  * of the file.
4977  * ---------------------------------------------------------------------------
4978  * Local variables:
4979  * c-indent-level: 2
4980  * c-brace-imaginary-offset: 0
4981  * c-brace-offset: -2
4982  * c-argdecl-indent: 2
4983  * c-label-offset: -2
4984  * c-continued-statement-offset: 2
4985  * c-continued-brace-offset: 0
4986  * indent-tabs-mode: nil
4987  * tab-width: 8
4988  * End:
4989  */
/* */
root/drivers/scsi/aic7xxx.c

DEFINITIONS
