This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
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129 static const char *version = "ewrk3.c:v0.32 1/16/95 davies@wanton.lkg.dec.com\n";
130
131 #include <linux/module.h>
132
133 #include <stdarg.h>
134
135 #include <linux/kernel.h>
136 #include <linux/sched.h>
137 #include <linux/string.h>
138 #include <linux/ptrace.h>
139 #include <linux/errno.h>
140 #include <linux/ioport.h>
141 #include <linux/malloc.h>
142 #include <linux/interrupt.h>
143 #include <linux/netdevice.h>
144 #include <linux/etherdevice.h>
145 #include <linux/skbuff.h>
146 #include <linux/time.h>
147 #include <linux/types.h>
148 #include <linux/unistd.h>
149
150 #include <asm/bitops.h>
151 #include <asm/io.h>
152 #include <asm/dma.h>
153 #include <asm/segment.h>
154
155 #include "ewrk3.h"
156
157 #ifdef EWRK3_DEBUG
158 static int ewrk3_debug = EWRK3_DEBUG;
159 #else
160 static int ewrk3_debug = 1;
161 #endif
162
163 #ifndef PROBE_LENGTH
164 #define PROBE_LENGTH 32
165 #endif
166
167 #ifndef PROBE_SEQUENCE
168 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
169 #endif
170
171 #ifndef EWRK3_SIGNATURE
172 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
173 #define EWRK3_NAME_LENGTH 8
174 #endif
175
176 #ifndef EWRK3_RAM_BASE_ADDRESSES
177 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
178 #endif
179
180
181
182
183
184
185
186
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189
190
191
192
193
194 #define EWRK3_IO_BASE 0x100
195 #define EWRK3_IOP_INC 0x20
196 #define EWRK3_TOTAL_SIZE 0x20
197 #define EWRK3_IO_SEARCH 0x007dff7f
198 static long mem_chkd = EWRK3_IO_SEARCH;
199
200
201 #ifndef MAX_NUM_EWRK3S
202 #define MAX_NUM_EWRK3S 21
203 #endif
204
205 #ifndef EWRK3_EISA_IO_PORTS
206 #define EWRK3_EISA_IO_PORTS 0x0c00
207 #endif
208
209 #ifndef MAX_EISA_SLOTS
210 #define MAX_EISA_SLOTS 8
211 #define EISA_SLOT_INC 0x1000
212 #endif
213
214 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
215 #define CRC_POLYNOMIAL_LE 0xedb88320UL
216
217
218
219
220 #define IO_ONLY 0x00
221 #define SHMEM_2K 0x800
222 #define SHMEM_32K 0x8000
223 #define SHMEM_64K 0x10000
224
225
226
227
228 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
229
230 #define ENABLE_IRQs \
231 icr |= irq_mask;\
232 outb(icr, EWRK3_ICR)
233
234 #define DISABLE_IRQs \
235 icr = inb(EWRK3_ICR);\
236 icr &= ~irq_mask;\
237 outb(icr, EWRK3_ICR)
238
239
240
241
242 #define START_EWRK3 \
243 csr = inb(EWRK3_CSR);\
244 csr &= ~(TXD|RXD);\
245 outb(csr, EWRK3_CSR)
246
247 #define STOP_EWRK3 \
248 csr = (TXD|RXD);\
249 outb(csr, EWRK3_CSR)
250
251
252
253
254 #define EWRK3_PKT_STAT_SZ 16
255 #define EWRK3_PKT_BIN_SZ 128
256
257
258 struct ewrk3_private {
259 long shmem_base;
260 long shmem_length;
261 struct enet_statistics stats;
262 struct {
263 unsigned long bins[EWRK3_PKT_STAT_SZ];
264 unsigned long unicast;
265 unsigned long multicast;
266 unsigned long broadcast;
267 unsigned long excessive_collisions;
268 unsigned long tx_underruns;
269 unsigned long excessive_underruns;
270 } pktStats;
271 short mPage;
272 unsigned char lemac;
273 unsigned char hard_strapped;
274 unsigned char lock;
275 unsigned char txc;
276 };
277
278
279
280
281 #define FORCE_2K_MODE \
282 shmem_length = SHMEM_2K;\
283 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
284
285
286
287
288 static int ewrk3_open(struct device *dev);
289 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
290 static void ewrk3_interrupt(int irq, struct pt_regs *regs);
291 static int ewrk3_close(struct device *dev);
292 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
293 static void set_multicast_list(struct device *dev);
294 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
295
296
297
298
299 static int ewrk3_hw_init(struct device *dev, short iobase);
300 static void ewrk3_init(struct device *dev);
301 static int ewrk3_rx(struct device *dev);
302 static int ewrk3_tx(struct device *dev);
303
304 static void EthwrkSignature(char * name, char *eeprom_image);
305 static int DevicePresent(short iobase);
306 static void SetMulticastFilter(struct device *dev, int num_addr, char *multicast_table);
307
308 static int Read_EEPROM(short iobase, unsigned char eaddr);
309 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
310 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
311
312 #ifndef MODULE
313 static struct device *isa_probe(struct device *dev);
314 static struct device *eisa_probe(struct device *dev);
315 static struct device *alloc_device(struct device *dev, int iobase);
316
317 static int num_ewrk3s = 0, num_eth = 0;
318 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
319
320 #else
321 int init_module(void);
322 void cleanup_module(void);
323
324 #endif
325
326 static int autoprobed = 0;
327
328
329
330
331 #define INIT_EWRK3 {\
332 int i;\
333 outb(EEPROM_INIT, EWRK3_IOPR);\
334 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
335 }
336
337
338
339
340 int ewrk3_probe(struct device *dev)
341 {
342 int base_addr = dev->base_addr;
343 int status = -ENODEV;
344 #ifndef MODULE
345 struct device *eth0;
346 #endif
347
348 if (base_addr > 0x0ff) {
349 if (!autoprobed) {
350 if (!check_region(base_addr, EWRK3_TOTAL_SIZE)) {
351 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
352 if (DevicePresent(base_addr) == 0) {
353
354 request_region(base_addr, EWRK3_IOP_INC, "ewrk3");
355 status = ewrk3_hw_init(dev, base_addr);
356 } else {
357 printk("ewrk3_probe(): No device found\n");
358 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
359 }
360 }
361 } else {
362 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
363 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
364 }
365 } else {
366 status = ewrk3_hw_init(dev, base_addr);
367 }
368 } else if (base_addr > 0) {
369 status = -ENXIO;
370
371 #ifdef MODULE
372 } else {
373 printk("Autoprobing is not supported when loading a module based driver.\n");
374 status = -EIO;
375 #else
376 } else if (!autoprobed) {
377
378 eth0=isa_probe(dev);
379 eth0=eisa_probe(eth0);
380 if (dev->priv) status=0;
381 autoprobed = 1;
382 } else {
383 status = -ENXIO;
384 #endif
385
386 }
387
388 if (status) dev->base_addr = base_addr;
389
390 return status;
391 }
392
393 static int
394 ewrk3_hw_init(struct device *dev, short iobase)
395 {
396 struct ewrk3_private *lp;
397 int i, status=0;
398 unsigned long mem_start, shmem_length;
399 char name[EWRK3_NAME_LENGTH + 1];
400 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
401 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
402
403
404
405
406
407 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
408 INIT_EWRK3;
409
410 nicsr = inb(EWRK3_CSR);
411
412
413
414
415 DISABLE_IRQs;
416
417 if (nicsr == (TXD|RXD)) {
418
419
420
421
422 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
423 union {
424 short val;
425 char c[2];
426 } tmp;
427
428 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
429 eeprom_image[i] = tmp.c[0];
430 eeprom_image[i+1] = tmp.c[1];
431
432 chksum += eeprom_image[i] + eeprom_image[i+1];
433 }
434
435 if (chksum != 0) {
436 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
437 status = -ENXIO;
438 } else {
439
440
441
442 EthwrkSignature(name, eeprom_image);
443
444 if (*name != '\0') {
445 dev->base_addr = iobase;
446
447 if (iobase > 0x400) {
448 outb(eisa_cr, EISA_CR);
449 }
450
451 lemac = eeprom_image[EEPROM_CHIPVER];
452 cmr = inb(EWRK3_CMR);
453
454 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
455 ((lemac == LeMAC2) && !(cmr & HS))) {
456 printk("%s: %s at %#3x", dev->name, name, iobase);
457 hard_strapped = 1;
458 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
459
460 printk("%s: %s at %#3x (EISA slot %d)",
461 dev->name, name, iobase, ((iobase>>12)&0x0f));
462 } else {
463 printk("%s: %s at %#3x", dev->name, name, iobase);
464 }
465
466 if (!status) {
467 printk(", h/w address ");
468 if (lemac == LeMAC2) {
469 for (i = 0;i < ETH_ALEN - 1;i++) {
470 printk("%2.2x:", dev->dev_addr[i] =
471 eeprom_image[EEPROM_PADDR0 + i]);
472 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
473 }
474 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
475 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
476 } else {
477 DevicePresent(iobase);
478 for (i = 0; i < ETH_ALEN - 1; i++) {
479 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
480 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
481 }
482 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
483 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
484 }
485
486 if (aprom_crc(dev, eeprom_image, lemac)) {
487 printk(" which has an EEPROM CRC error.\n");
488 status = -ENXIO;
489 } else {
490 if (lemac == LeMAC2) {
491 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
492 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
493 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
494 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
495 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
496 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
497 }
498 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
499 outb(cmr, EWRK3_CMR);
500
501 cr = inb(EWRK3_CR);
502 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
503 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
504 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
505 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
506 outb(cr, EWRK3_CR);
507
508
509
510
511
512 mem_start = inb(EWRK3_MBR);
513 shmem_length = 0;
514 if (mem_start != 0) {
515 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
516 mem_start *= SHMEM_64K;
517 shmem_length = SHMEM_64K;
518 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
519 mem_start *= SHMEM_32K;
520 shmem_length = SHMEM_32K;
521 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
522 mem_start = mem_start * SHMEM_2K + 0x80000;
523 shmem_length = SHMEM_2K;
524 } else {
525 status = -ENXIO;
526 }
527 }
528
529
530
531
532
533
534
535 if (!status) {
536 if (hard_strapped) {
537 printk(" is hard strapped.\n");
538 } else if (mem_start) {
539 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
540 printk(" at 0x%.5lx", mem_start);
541 } else {
542 printk(" is in I/O only mode");
543 }
544
545
546 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
547 GFP_KERNEL);
548 if (dev->priv == NULL)
549 return -ENOMEM;
550 lp = (struct ewrk3_private *)dev->priv;
551 memset(dev->priv, 0, sizeof(struct ewrk3_private));
552 lp->shmem_base = mem_start;
553 lp->shmem_length = shmem_length;
554 lp->lemac = lemac;
555 lp->hard_strapped = hard_strapped;
556
557 lp->mPage = 64;
558 if (cmr & DRAM) lp->mPage <<= 1 ;
559
560 if (!hard_strapped) {
561
562
563
564 icr |= IE;
565 outb(icr, EWRK3_ICR);
566
567
568 dev->dma = 0;
569
570
571
572 if (dev->irq < 2) {
573 #ifndef MODULE
574 unsigned char irqnum;
575
576 autoirq_setup(0);
577
578
579
580
581 icr |=TNEM;
582 outb(1,EWRK3_TDQ);
583 outb(icr, EWRK3_ICR);
584
585 irqnum = irq[((icr & IRQ_SEL) >> 4)];
586
587 dev->irq = autoirq_report(1);
588 if ((dev->irq) && (irqnum == dev->irq)) {
589 printk(" and uses IRQ%d.\n", dev->irq);
590 } else {
591 if (!dev->irq) {
592 printk(" and failed to detect IRQ line.\n");
593 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
594 printk(" and an illegal IRQ line detected.\n");
595 } else {
596 printk(", but incorrect IRQ line detected.\n");
597 }
598 status = -ENXIO;
599 }
600
601 DISABLE_IRQs;
602
603 #endif
604 } else {
605 printk(" and requires IRQ%d.\n", dev->irq);
606 }
607 }
608 } else {
609 status = -ENXIO;
610 }
611 }
612 }
613 } else {
614 status = -ENXIO;
615 }
616 }
617
618 if (!status) {
619 if (ewrk3_debug > 0) {
620 printk(version);
621 }
622
623
624 dev->open = &ewrk3_open;
625 dev->hard_start_xmit = &ewrk3_queue_pkt;
626 dev->stop = &ewrk3_close;
627 dev->get_stats = &ewrk3_get_stats;
628 dev->set_multicast_list = &set_multicast_list;
629 dev->do_ioctl = &ewrk3_ioctl;
630
631 dev->mem_start = 0;
632
633
634 ether_setup(dev);
635 }
636 } else {
637 status = -ENXIO;
638 }
639
640 return status;
641 }
642
643
644 static int
645 ewrk3_open(struct device *dev)
646 {
647 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
648 int i, iobase = dev->base_addr;
649 int status = 0;
650 unsigned char icr, csr;
651
652
653
654
655 STOP_EWRK3;
656
657 if (!lp->hard_strapped) {
658 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
659 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
660 status = -EAGAIN;
661 } else {
662
663 irq2dev_map[dev->irq] = dev;
664
665
666
667
668 ewrk3_init(dev);
669
670 if (ewrk3_debug > 1){
671 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
672 printk("\tphysical address: ");
673 for (i=0;i<6;i++){
674 printk("%2.2x:",(short)dev->dev_addr[i]);
675 }
676 printk("\n");
677 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
678 if (lp->shmem_length == 0) {
679 printk("\tno shared memory, I/O only mode\n");
680 } else {
681 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
682 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
683 }
684 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
685 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
686 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
687 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
688 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
689 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
690 }
691
692 dev->tbusy = 0;
693 dev->start = 1;
694 dev->interrupt = UNMASK_INTERRUPTS;
695
696
697
698
699 icr = inb(EWRK3_ICR);
700 ENABLE_IRQs;
701
702 }
703 } else {
704 dev->start = 0;
705 dev->tbusy = 1;
706 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
707 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
708 }
709
710 MOD_INC_USE_COUNT;
711
712 return status;
713 }
714
715
716
717
718 static void
719 ewrk3_init(struct device *dev)
720 {
721 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
722 char csr, page;
723 short iobase = dev->base_addr;
724 int flags=dev->flags;
725
726
727
728
729
730 dev->flags|=IFF_ALLMULTI;
731 set_multicast_list(dev);
732 dev->flags=flags;
733
734
735
736
737 while (inb(EWRK3_TQ));
738 while (inb(EWRK3_TDQ));
739 while (inb(EWRK3_RQ));
740 while (inb(EWRK3_FMQ));
741
742
743
744
745 for (page=1;page<lp->mPage;page++) {
746 outb(page, EWRK3_FMQ);
747 }
748
749 lp->lock = 0;
750
751 START_EWRK3;
752 }
753
754
755
756
757 static int
758 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
759 {
760 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
761 int iobase = dev->base_addr;
762 int status = 0;
763 unsigned char icr, csr;
764
765
766 if (dev->tbusy || lp->lock) {
767 int tickssofar = jiffies - dev->trans_start;
768 if (tickssofar < 10) {
769 status = -1;
770 } else if (!lp->hard_strapped) {
771 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
772 dev->name, inb(EWRK3_CSR));
773
774
775
776
777 DISABLE_IRQs;
778
779
780
781
782 STOP_EWRK3;
783
784 ewrk3_init(dev);
785
786
787
788
789 ENABLE_IRQs;
790
791 dev->tbusy=0;
792 dev->trans_start = jiffies;
793 }
794 } else if (skb == NULL) {
795 dev_tint(dev);
796 } else if (skb->len > 0) {
797
798
799
800
801
802 if (set_bit(0, (void*)&dev->tbusy) != 0)
803 printk("%s: Transmitter access conflict.\n", dev->name);
804
805 DISABLE_IRQs;
806
807
808
809
810 if (inb(EWRK3_FMQC) > 0) {
811 unsigned char *buf;
812 unsigned char page;
813
814 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
815 buf = NULL;
816
817
818
819
820 while (set_bit(0, (void *)&lp->lock) != 0);
821 if (lp->shmem_length == IO_ONLY) {
822 outb(page, EWRK3_IOPR);
823 } else if (lp->shmem_length == SHMEM_2K) {
824 buf = (char *) lp->shmem_base;
825 outb(page, EWRK3_MPR);
826 } else if (lp->shmem_length == SHMEM_32K) {
827 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
828 outb((page >> 4), EWRK3_MPR);
829 } else if (lp->shmem_length == SHMEM_64K) {
830 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
831 outb((page >> 5), EWRK3_MPR);
832 } else {
833 status = -1;
834 printk("%s: Oops - your private data area is hosed!\n",dev->name);
835 }
836
837 if (!status) {
838
839
840
841
842
843
844 if (lp->shmem_length == IO_ONLY) {
845 int i;
846 unsigned char *p = skb->data;
847
848 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
849 outb((char)(skb->len & 0xff), EWRK3_DATA);
850 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
851 outb((char)0x04, EWRK3_DATA);
852 for (i=0; i<skb->len; i++) {
853 outb(*p++, EWRK3_DATA);
854 }
855 outb(page, EWRK3_TQ);
856 } else {
857 *buf++ = (char)(QMODE | PAD | IFC);
858 *buf++ = (char)(skb->len & 0xff);
859 if (lp->txc) {
860 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
861 *buf++ = 0x04;
862 *(buf + skb->len) = 0x00;
863 memcpy(buf, skb->data, PRELOAD);
864 outb(page, EWRK3_TQ);
865 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
866 *(buf + skb->len) = 0xff;
867 } else {
868 *buf++ = (char)((skb->len >> 8) & 0xff);
869 *buf++ = 0x04;
870 memcpy(buf, skb->data, skb->len);
871 outb(page, EWRK3_TQ);
872 }
873 }
874
875 dev->trans_start = jiffies;
876
877 dev_kfree_skb (skb, FREE_WRITE);
878
879 } else {
880 outb(page, EWRK3_FMQ);
881 }
882 lp->lock = 0;
883 } else {
884 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
885 (unsigned char) page);
886 }
887 } else {
888 printk("ewrk3_queue_pkt(): No free resources...\n");
889 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
890 }
891
892
893 if (inb(EWRK3_FMQC) > 0) {
894 dev->tbusy = 0;
895 }
896
897 ENABLE_IRQs;
898 }
899
900 return status;
901 }
902
903
904
905
906 static void
907 ewrk3_interrupt(int irq, struct pt_regs * regs)
908 {
909 struct device *dev = (struct device *)(irq2dev_map[irq]);
910 struct ewrk3_private *lp;
911 int iobase;
912 unsigned char icr, cr, csr;
913
914 if (dev == NULL) {
915 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
916 } else {
917 lp = (struct ewrk3_private *)dev->priv;
918 iobase = dev->base_addr;
919
920 if (dev->interrupt)
921 printk("%s: Re-entering the interrupt handler.\n", dev->name);
922
923 dev->interrupt = MASK_INTERRUPTS;
924
925
926 csr = inb(EWRK3_CSR);
927
928
929
930
931 DISABLE_IRQs;
932
933 cr = inb(EWRK3_CR);
934 cr |= LED;
935 outb(cr, EWRK3_CR);
936
937 if (csr & RNE)
938 ewrk3_rx(dev);
939
940 if (csr & TNE)
941 ewrk3_tx(dev);
942
943
944
945
946
947
948
949 if (inb(EWRK3_FMQC)) {
950 irq_mask |= TXDM|RXDM;
951 csr &= ~(TXD|RXD);
952 outb(csr, EWRK3_CSR);
953 dev->tbusy = 0;
954 mark_bh(NET_BH);
955 } else {
956 irq_mask &= ~(TXDM|RXDM);
957 }
958
959
960 cr &= ~LED;
961 outb(cr, EWRK3_CR);
962
963 dev->interrupt = UNMASK_INTERRUPTS;
964
965 ENABLE_IRQs;
966 }
967
968 return;
969 }
970
971 static int
972 ewrk3_rx(struct device *dev)
973 {
974 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
975 int i, iobase = dev->base_addr;
976 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
977 int status = 0;
978
979 while (inb(EWRK3_RQC) && !status) {
980 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
981 buf = NULL;
982
983
984
985
986
987 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
988 if (lp->shmem_length == IO_ONLY) {
989 tmpPage = inb(EWRK3_IOPR);
990 } else {
991 tmpPage = inb(EWRK3_MPR);
992 }
993 }
994
995
996
997
998 if (lp->shmem_length == IO_ONLY) {
999 outb(page, EWRK3_IOPR);
1000 } else if (lp->shmem_length == SHMEM_2K) {
1001 buf = (char *) lp->shmem_base;
1002 outb(page, EWRK3_MPR);
1003 } else if (lp->shmem_length == SHMEM_32K) {
1004 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1005 outb((page >> 4), EWRK3_MPR);
1006 } else if (lp->shmem_length == SHMEM_64K) {
1007 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1008 outb((page >> 5), EWRK3_MPR);
1009 } else {
1010 status = -1;
1011 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1012 }
1013
1014 if (!status) {
1015 char rx_status;
1016 int pkt_len;
1017
1018 if (lp->shmem_length == IO_ONLY) {
1019 rx_status = inb(EWRK3_DATA);
1020 pkt_len = inb(EWRK3_DATA);
1021 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1022 } else {
1023 rx_status = (char)(*buf++);
1024 pkt_len = (short)(*buf+((*(buf+1))<<8));
1025 buf+=3;
1026 }
1027
1028 if (!(rx_status & ROK)) {
1029 lp->stats.rx_errors++;
1030 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1031 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1032 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1033 } else {
1034 struct sk_buff *skb;
1035
1036 if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1037 unsigned char *p;
1038 skb->dev = dev;
1039 skb_reserve(skb,2);
1040 p = skb_put(skb,pkt_len);
1041
1042 if (lp->shmem_length == IO_ONLY) {
1043 *p = inb(EWRK3_DATA);
1044 for (i=0; i<pkt_len; i++) {
1045 *p++ = inb(EWRK3_DATA);
1046 }
1047 } else {
1048 memcpy(p, buf, pkt_len);
1049 }
1050
1051
1052
1053
1054
1055
1056 skb->protocol=eth_type_trans(skb,dev);
1057 netif_rx(skb);
1058
1059
1060
1061
1062 lp->stats.rx_packets++;
1063 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1064 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1065 lp->pktStats.bins[i]++;
1066 i = EWRK3_PKT_STAT_SZ;
1067 }
1068 }
1069 buf = skb->data;
1070 if (buf[0] & 0x01) {
1071 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1072 lp->pktStats.broadcast++;
1073 } else {
1074 lp->pktStats.multicast++;
1075 }
1076 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1077 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1078 lp->pktStats.unicast++;
1079 }
1080
1081 lp->pktStats.bins[0]++;
1082 if (lp->pktStats.bins[0] == 0) {
1083 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1084 }
1085 } else {
1086 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1087 lp->stats.rx_dropped++;
1088 break;
1089 }
1090 }
1091 }
1092
1093
1094
1095 outb(page, EWRK3_FMQ);
1096
1097 if (tmpLock) {
1098 if (lp->shmem_length == IO_ONLY) {
1099 outb(tmpPage, EWRK3_IOPR);
1100 } else {
1101 outb(tmpPage, EWRK3_MPR);
1102 }
1103 }
1104 lp->lock = 0;
1105 } else {
1106 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1107 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1108 }
1109 }
1110 return status;
1111 }
1112
1113
1114
1115
1116 static int
1117 ewrk3_tx(struct device *dev)
1118 {
1119 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1120 int iobase = dev->base_addr;
1121 unsigned char tx_status;
1122
1123 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1124 if (tx_status & VSTS) {
1125 if (tx_status & MAC_TXE) {
1126 lp->stats.tx_errors++;
1127 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1128 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1129 if (tx_status & MAC_CTU) {
1130 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1131 lp->pktStats.tx_underruns++;
1132 } else {
1133 lp->pktStats.excessive_underruns++;
1134 }
1135 } else if (tx_status & MAC_COLL) {
1136 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1137 lp->stats.collisions++;
1138 } else {
1139 lp->pktStats.excessive_collisions++;
1140 }
1141 }
1142 } else {
1143 lp->stats.tx_packets++;
1144 }
1145 }
1146 }
1147
1148 return 0;
1149 }
1150
1151 static int
1152 ewrk3_close(struct device *dev)
1153 {
1154 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1155 int iobase = dev->base_addr;
1156 unsigned char icr, csr;
1157
1158 dev->start = 0;
1159 dev->tbusy = 1;
1160
1161 if (ewrk3_debug > 1) {
1162 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1163 dev->name, inb(EWRK3_CSR));
1164 }
1165
1166
1167
1168
1169 DISABLE_IRQs;
1170
1171 STOP_EWRK3;
1172
1173
1174
1175
1176
1177
1178
1179 while (inb(EWRK3_TQ));
1180 while (inb(EWRK3_TDQ));
1181 while (inb(EWRK3_RQ));
1182
1183 if (!lp->hard_strapped) {
1184 free_irq(dev->irq);
1185
1186 irq2dev_map[dev->irq] = 0;
1187 }
1188
1189 MOD_DEC_USE_COUNT;
1190
1191 return 0;
1192 }
1193
1194 static struct enet_statistics *
1195 ewrk3_get_stats(struct device *dev)
1196 {
1197 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1198
1199
1200
1201 return &lp->stats;
1202 }
1203
1204
1205
1206
1207
1208
1209
1210
1211 static void
1212 set_multicast_list(struct device *dev)
1213 {
1214 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1215 int iobase = dev->base_addr;
1216 char *multicast_table;
1217 unsigned char csr;
1218
1219 csr = inb(EWRK3_CSR);
1220
1221 if (lp->shmem_length == IO_ONLY)
1222 {
1223 multicast_table = (char *) PAGE0_HTE;
1224 } else {
1225 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1226 }
1227
1228 if (dev->flags&(IFF_ALLMULTI|IFF_PROMISC))
1229 {
1230 csr |= PME;
1231 csr &= ~MCE;
1232 outb(csr, EWRK3_CSR);
1233 dev->flags|=IFF_PROMISC;
1234 } else {
1235 SetMulticastFilter(dev, dev->mc_count, multicast_table);
1236 csr &= ~PME;
1237 csr |= MCE;
1238 outb(csr, EWRK3_CSR);
1239 }
1240 }
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250 static void SetMulticastFilter(struct device *dev, int num_addrs, char *multicast_table)
1251 {
1252 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1253 char *addrs;
1254 struct dev_mc_list *dmi=dev->mc_list;
1255 int i, iobase = dev->base_addr;
1256 char j, bit, byte;
1257 short *p = (short *) multicast_table;
1258 u_short hashcode;
1259 u_long crc, poly = CRC_POLYNOMIAL_LE;
1260
1261 while (set_bit(0, (void *)&lp->lock) != 0);
1262
1263 if (lp->shmem_length == IO_ONLY)
1264 {
1265 outb(0, EWRK3_IOPR);
1266 outw((short)((long)multicast_table), EWRK3_PIR1);
1267 }
1268 else
1269 {
1270 outb(0, EWRK3_MPR);
1271 }
1272
1273 if (num_addrs >= HASH_TABLE_LEN)
1274 {
1275 for (i=0; i<(HASH_TABLE_LEN >> 3); i++)
1276 {
1277 if (lp->shmem_length == IO_ONLY)
1278 {
1279 outb(0xff, EWRK3_DATA);
1280 }
1281 else
1282 {
1283 *p++ = 0xffff;
1284 i++;
1285 }
1286 }
1287 }
1288 else
1289 {
1290
1291 if (lp->shmem_length == IO_ONLY)
1292 {
1293 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++)
1294 {
1295 outb(0x00, EWRK3_DATA);
1296 }
1297 outb(0x80, EWRK3_DATA); i++;
1298 for (; i<(HASH_TABLE_LEN >> 3); i++)
1299 {
1300 outb(0x00, EWRK3_DATA);
1301 }
1302 }
1303 else
1304 {
1305 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1306 *(multicast_table + (HASH_TABLE_LEN >> 4) - 1) = 0x80;
1307 }
1308
1309
1310
1311 for (i=0;i<dev->mc_count;i++)
1312 {
1313
1314 addrs=dmi->dmi_addr;
1315 dmi=dmi->next;
1316
1317 if ((*addrs & 0x01) == 1)
1318 {
1319 crc = 0xffffffff;
1320 for (byte=0;byte<ETH_ALEN;byte++)
1321 {
1322
1323 for (bit = *addrs++,j=0;j<8;j++, bit>>=1)
1324 {
1325 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1326 }
1327 }
1328 hashcode = crc & ((1 << 9) - 1);
1329
1330 byte = hashcode >> 3;
1331 bit = 1 << (hashcode & 0x07);
1332
1333 if (lp->shmem_length == IO_ONLY)
1334 {
1335 unsigned char tmp;
1336
1337 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1338 tmp = inb(EWRK3_DATA);
1339 tmp |= bit;
1340 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1341 outb(tmp, EWRK3_DATA);
1342 }
1343 else
1344 {
1345 multicast_table[byte] |= bit;
1346 }
1347 }
1348 }
1349 }
1350
1351 lp->lock = 0;
1352
1353 return;
1354 }
1355
1356 #ifndef MODULE
1357
1358
1359
1360 static struct device *isa_probe(struct device *dev)
1361 {
1362 int i, iobase, status;
1363 unsigned long int tmp = mem_chkd;
1364
1365 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1366 i < 24;
1367 iobase += EWRK3_IOP_INC, i++) {
1368 if (tmp & 0x01) {
1369
1370 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1371 if (DevicePresent(iobase) == 0) {
1372
1373
1374
1375
1376 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1377 if (num_ewrk3s > 0) {
1378 dev = alloc_device(dev, iobase);
1379 } else {
1380 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1381 num_ewrk3s++;
1382 }
1383 }
1384 num_eth++;
1385 } else {
1386 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1387 }
1388 } else {
1389 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1390 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1391 }
1392 }
1393 tmp >>= 1;
1394 }
1395
1396 return dev;
1397 }
1398
1399
1400
1401
1402
1403 static struct device *eisa_probe(struct device *dev)
1404 {
1405 int i, iobase = EWRK3_EISA_IO_PORTS;
1406 int status;
1407
1408 iobase+=EISA_SLOT_INC;
1409 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1410
1411
1412 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1413 if (DevicePresent(iobase) == 0) {
1414
1415
1416
1417
1418 mem_chkd |= (0x01 << (i + 24));
1419 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1420 if (num_ewrk3s > 0) {
1421 dev = alloc_device(dev, iobase);
1422 } else {
1423 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1424 num_ewrk3s++;
1425 }
1426 }
1427 num_eth++;
1428 }
1429 }
1430 }
1431 return dev;
1432 }
1433
1434
1435
1436
1437
1438 static struct device *alloc_device(struct device *dev, int iobase)
1439 {
1440
1441
1442
1443 while (dev->next != NULL) {
1444 if (dev->next->base_addr == 0xffe0) break;
1445 dev = dev->next;
1446 num_eth++;
1447 }
1448
1449
1450
1451
1452
1453 if (dev->next == NULL) {
1454 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1455 GFP_KERNEL);
1456 if (dev->next == NULL) {
1457 printk("eth%d: Device not initialised, insufficient memory\n",
1458 num_eth);
1459 }
1460 }
1461
1462
1463
1464
1465
1466
1467 if ((dev->next != NULL) &&
1468 (num_eth > 0) && (num_eth < 9999)) {
1469 dev = dev->next;
1470 dev->name = (char *)(dev + sizeof(struct device));
1471 sprintf(dev->name,"eth%d", num_eth);
1472 dev->base_addr = iobase;
1473 dev->next = NULL;
1474 dev->init = &ewrk3_probe;
1475 num_ewrk3s++;
1476 }
1477
1478 return dev;
1479 }
1480 #endif
1481
1482
1483
1484
1485 static int Read_EEPROM(short iobase, unsigned char eaddr)
1486 {
1487 int i;
1488
1489 outb((eaddr & 0x3f), EWRK3_PIR1);
1490 outb(EEPROM_RD, EWRK3_IOPR);
1491 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1492
1493 return inw(EWRK3_EPROM1);
1494 }
1495
1496
1497
1498
1499 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1500 {
1501 int i;
1502
1503 outb(EEPROM_WR_EN, EWRK3_IOPR);
1504 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1505 outw(data, EWRK3_EPROM1);
1506 outb((eaddr & 0x3f), EWRK3_PIR1);
1507 outb(EEPROM_WR, EWRK3_IOPR);
1508 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1509 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1510 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1511
1512 return 0;
1513 }
1514
1515
1516
1517
1518 static void EthwrkSignature(char *name, char *eeprom_image)
1519 {
1520 unsigned long i,j,k;
1521 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1522
1523 strcpy(name, "");
1524 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1525 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1526 if (signatures[i][k] == eeprom_image[j]) {
1527 k++;
1528 } else {
1529 k=0;
1530 }
1531 }
1532 if (k == strlen(signatures[i])) {
1533 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1534 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1535 name[EWRK3_NAME_LENGTH] = '\0';
1536 }
1537 }
1538 }
1539
1540 return;
1541 }
1542
1543
1544
1545
1546
1547
1548 static int DevicePresent(short iobase)
1549 {
1550 static short fp=1,sigLength=0;
1551 static char devSig[] = PROBE_SEQUENCE;
1552 char data;
1553 int i, j, status = 0;
1554 static char asc2hex(char value);
1555
1556
1557
1558
1559 if (fp) {
1560 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1561 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1562 devSig[i]<<=4;
1563 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1564 devSig[j]=devSig[i]+devSig[i+1];
1565 } else {
1566 status= -1;
1567 }
1568 } else {
1569 status= -1;
1570 }
1571 }
1572 sigLength=j;
1573 fp = 0;
1574 }
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584 if (!status) {
1585 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1586 data = inb(EWRK3_APROM);
1587 if (devSig[j] == data) {
1588 j++;
1589 } else {
1590 j=0;
1591 }
1592 }
1593
1594 if (j!=sigLength) {
1595 status = -ENODEV;
1596 }
1597 }
1598
1599 return status;
1600 }
1601
1602 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1603 {
1604 long k;
1605 unsigned short j,chksum;
1606 unsigned char crc, lfsr, sd, status = 0;
1607 int iobase = dev->base_addr;
1608
1609 if (chipType == LeMAC2) {
1610 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1611 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1612 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1613 crc = (crc >> 1) + lfsr;
1614 }
1615 }
1616 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1617 } else {
1618 for (k=0,j=0;j<3;j++) {
1619 k <<= 1 ;
1620 if (k > 0xffff) k-=0xffff;
1621 k += inw(EWRK3_PAR0 + (j<<1));
1622 if (k > 0xffff) k-=0xffff;
1623 }
1624 if (k == 0xffff) k=0;
1625 chksum = inb(EWRK3_APROM);
1626 chksum |= (inb(EWRK3_APROM)<<8);
1627 if (k != chksum) status = -1;
1628 }
1629
1630 return status;
1631 }
1632
1633
1634
1635
1636
1637 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1638 {
1639 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1640 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1641 int i, j, iobase = dev->base_addr, status = 0;
1642 unsigned char csr;
1643 union {
1644 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1645 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1646 } tmp;
1647 int err;
1648
1649 switch(ioc->cmd) {
1650 case EWRK3_GET_HWADDR:
1651 for (i=0; i<ETH_ALEN; i++) {
1652 tmp.addr[i] = dev->dev_addr[i];
1653 }
1654 ioc->len = ETH_ALEN;
1655
1656 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ETH_ALEN);
1657 if (err) return err;
1658 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1659
1660 break;
1661 case EWRK3_SET_HWADDR:
1662 if (suser()) {
1663 csr = inb(EWRK3_CSR);
1664 csr |= (TXD|RXD);
1665 outb(csr, EWRK3_CSR);
1666
1667 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
1668 if (err) return err;
1669 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1670 for (i=0; i<ETH_ALEN; i++) {
1671 dev->dev_addr[i] = tmp.addr[i];
1672 outb(tmp.addr[i], EWRK3_PAR0 + i);
1673 }
1674
1675 csr &= ~(TXD|RXD);
1676 outb(csr, EWRK3_CSR);
1677 } else {
1678 status = -EPERM;
1679 }
1680
1681 break;
1682 case EWRK3_SET_PROM:
1683 if (suser()) {
1684 csr = inb(EWRK3_CSR);
1685 csr |= PME;
1686 csr &= ~MCE;
1687 outb(csr, EWRK3_CSR);
1688 } else {
1689 status = -EPERM;
1690 }
1691
1692 break;
1693 case EWRK3_CLR_PROM:
1694 if (suser()) {
1695 csr = inb(EWRK3_CSR);
1696 csr &= ~PME;
1697 outb(csr, EWRK3_CSR);
1698 } else {
1699 status = -EPERM;
1700 }
1701
1702 break;
1703 case EWRK3_SAY_BOO:
1704 if(suser())
1705 printk("%s: Boo!\n", dev->name);
1706
1707 break;
1708 case EWRK3_GET_MCA:
1709 err = verify_area(VERIFY_WRITE, (void *)ioc->data, HASH_TABLE_LEN >> 3);
1710 if (err) return err;
1711
1712 while (set_bit(0, (void *)&lp->lock) != 0);
1713 if (lp->shmem_length == IO_ONLY) {
1714 outb(0, EWRK3_IOPR);
1715 outw(PAGE0_HTE, EWRK3_PIR1);
1716 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1717 tmp.addr[i] = inb(EWRK3_DATA);
1718 }
1719 } else {
1720 outb(0, EWRK3_MPR);
1721 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1722 }
1723 ioc->len = (HASH_TABLE_LEN >> 3);
1724 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1725 lp->lock = 0;
1726
1727 break;
1728
1729 #if 0
1730 case EWRK3_SET_MCA:
1731 if (suser()) {
1732 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN * ioc->len);
1733 if (err) return err;
1734
1735 if (ioc->len != HASH_TABLE_LEN) {
1736 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1737 }
1738 set_multicast_list(dev, ioc->len, tmp.addr);
1739 } else {
1740 status = -EPERM;
1741 }
1742
1743 break;
1744 case EWRK3_CLR_MCA:
1745 if (suser()) {
1746 set_multicast_list(dev, 0, NULL);
1747 } else {
1748 status = -EPERM;
1749 }
1750
1751 break;
1752 case EWRK3_MCA_EN:
1753 if (suser()) {
1754 csr = inb(EWRK3_CSR);
1755 csr |= MCE;
1756 csr &= ~PME;
1757 outb(csr, EWRK3_CSR);
1758 } else {
1759 status = -EPERM;
1760 }
1761
1762 break;
1763 #endif
1764 case EWRK3_GET_STATS:
1765 err = verify_area(VERIFY_WRITE, (void *)ioc->data, sizeof(lp->pktStats));
1766 if (err) return err;
1767
1768 cli();
1769 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1770 ioc->len = EWRK3_PKT_STAT_SZ;
1771 sti();
1772
1773 break;
1774 case EWRK3_CLR_STATS:
1775 if (suser()) {
1776 cli();
1777 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1778 sti();
1779 } else {
1780 status = -EPERM;
1781 }
1782
1783 break;
1784 case EWRK3_GET_CSR:
1785 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1786 if (err) return err;
1787
1788 tmp.addr[0] = inb(EWRK3_CSR);
1789 memcpy_tofs(ioc->data, tmp.addr, 1);
1790
1791 break;
1792 case EWRK3_SET_CSR:
1793 err = verify_area(VERIFY_READ, (void *)ioc->data, 1);
1794 if (err) return err;
1795
1796 if (suser()) {
1797 memcpy_fromfs(tmp.addr, ioc->data, 1);
1798 outb(tmp.addr[0], EWRK3_CSR);
1799 } else {
1800 status = -EPERM;
1801 }
1802
1803 break;
1804 case EWRK3_GET_EEPROM:
1805 if (suser()) {
1806 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
1807 if (err) return err;
1808
1809 for (i=0; i<(EEPROM_MAX>>1); i++) {
1810 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1811 }
1812 i = EEPROM_MAX;
1813 tmp.addr[i++] = inb(EWRK3_CMR);
1814 for (j=0;j<ETH_ALEN;j++) {
1815 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1816 }
1817 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1818 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1819 } else {
1820 status = -EPERM;
1821 }
1822
1823 break;
1824 case EWRK3_SET_EEPROM:
1825 if (suser()) {
1826 err = verify_area(VERIFY_READ, (void *)ioc->data, EEPROM_MAX);
1827 if (err) return err;
1828
1829 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1830 for (i=0; i<(EEPROM_MAX>>1); i++) {
1831 Write_EEPROM(tmp.val[i], iobase, i);
1832 }
1833 } else {
1834 status = -EPERM;
1835 }
1836
1837 break;
1838 case EWRK3_GET_CMR:
1839 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1840 if (err) return err;
1841
1842 tmp.addr[0] = inb(EWRK3_CMR);
1843 memcpy_tofs(ioc->data, tmp.addr, 1);
1844
1845 break;
1846 case EWRK3_SET_TX_CUT_THRU:
1847 if (suser()) {
1848 lp->txc = 1;
1849 } else {
1850 status = -EPERM;
1851 }
1852
1853 break;
1854 case EWRK3_CLR_TX_CUT_THRU:
1855 if (suser()) {
1856 lp->txc = 0;
1857 } else {
1858 status = -EPERM;
1859 }
1860
1861 break;
1862 default:
1863 status = -EOPNOTSUPP;
1864 }
1865
1866 return status;
1867 }
1868
1869 static char asc2hex(char value)
1870 {
1871 value -= 0x30;
1872 if (value >= 0) {
1873 if (value > 9) {
1874 value &= 0x1f;
1875 value -= 0x07;
1876 if ((value < 0x0a) || (value > 0x0f)) {
1877 value = -1;
1878 }
1879 }
1880 } else {
1881 value = -1;
1882 }
1883 return value;
1884 }
1885
1886 #ifdef MODULE
1887 static char devicename[9] = { 0, };
1888 static struct device thisEthwrk = {
1889 devicename,
1890 0, 0, 0, 0,
1891 0x300, 5,
1892 0, 0, 0, NULL, ewrk3_probe };
1893
1894 static int io=0x300;
1895 static int irq=5;
1896
1897 int
1898 init_module(void)
1899 {
1900 thisEthwrk.base_addr=io;
1901 thisEthwrk.irq=irq;
1902 if (register_netdev(&thisEthwrk) != 0)
1903 return -EIO;
1904 return 0;
1905 }
1906
1907 void
1908 cleanup_module(void)
1909 {
1910 release_region(thisEthwrk.base_addr, EWRK3_TOTAL_SIZE);
1911 unregister_netdev(&thisEthwrk);
1912 kfree(thisEthwrk.priv);
1913 thisEthwrk.priv = NULL;
1914 }
1915 #endif
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927