include/asm-alpha/apecs.h

/* */
This source file includes following definitions.
virt_to_bus
bus_to_virt
__inb
__outb
__inw
__outw
__inl
__outl
__readb
__readw
__readl
__writeb
__writew
__writel
   1 #ifndef __ALPHA_APECS__H__
   2 #define __ALPHA_APECS__H__
   3 
   4 #include <linux/types.h>
   5 
   6 /*
   7  * APECS is the internal name for the 2107x chipset which provides
   8  * memory controller and PCI access for the 21064 chip based systems.
   9  *
  10  * This file is based on:
  11  *
  12  * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
  13  * Data Sheet
  14  *
  15  * EC-N0648-72
  16  *
  17  *
  18  * david.rusling@reo.mts.dec.com Initial Version.
  19  *
  20  */
  21 
  22 #define APECS_DMA_WIN_BASE      (1024*1024*1024)
  23 #define APECS_DMA_WIN_SIZE      (1024*1024*1024)
  24 
  25 /*
  26  * 21071-DA Control and Status registers.
  27  * These are used for PCI memory access.
  28  */
  29 #define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
  30 #define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
  31 #define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
  32 #define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
  33 #define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
  34 #define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
  35 
  36 #define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
  37 #define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
  38 
  39 #define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
  40 #define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
  41 
  42 #define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
  43 #define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
  44 
  45 #define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
  46 #define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
  47 #define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
  48 
  49 #define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
  50 
  51 #define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
  52 #define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
  53 #define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
  54 #define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
  55 #define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
  56 #define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
  57 #define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
  58 #define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
  59 
  60 #define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
  61 #define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
  62 #define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
  63 #define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
  64 #define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
  65 #define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
  66 #define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
  67 #define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
  68 
  69 #define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
  70 
  71 
  72 /*
  73  * 21071-CA Control and Status registers.
  74  * These are used to program memory timing,
  75  *  configure memory and initialise the B-Cache.
  76  */
  77 #define APECS_IOC_GCR                   (IDENT_ADDR + 0x180000000UL)
  78 #define APECS_IOC_EDSR                  (IDENT_ADDR + 0x180000040UL)
  79 #define APECS_IOC_TAR                   (IDENT_ADDR + 0x180000060UL)
  80 #define APECS_IOC_ELAR                  (IDENT_ADDR + 0x180000080UL)
  81 #define APECS_IOC_EHAR                  (IDENT_ADDR + 0x1800000a0UL)
  82 #define APECS_IOC_SFT_RST               (IDENT_ADDR + 0x1800000c0UL)
  83 #define APECS_IOC_LDxLAR                (IDENT_ADDR + 0x1800000e0UL)
  84 #define APECS_IOC_LDxHAR                (IDENT_ADDR + 0x180000100UL)
  85 #define APECS_IOC_GTR                   (IDENT_ADDR + 0x180000200UL)
  86 #define APECS_IOC_RTR                   (IDENT_ADDR + 0x180000220UL)
  87 #define APECS_IOC_VFPR                  (IDENT_ADDR + 0x180000240UL)
  88 #define APECS_IOC_PDLDR                 (IDENT_ADDR + 0x180000260UL)
  89 #define APECS_IOC_PDhDR                 (IDENT_ADDR + 0x180000280UL)
  90 
  91 /* Bank x Base Address Register */
  92 #define APECS_IOC_B0BAR                 (IDENT_ADDR + 0x180000800UL)
  93 #define APECS_IOC_B1BAR                 (IDENT_ADDR + 0x180000820UL)
  94 #define APECS_IOC_B2BAR                 (IDENT_ADDR + 0x180000840UL)
  95 #define APECS_IOC_B3BAR                 (IDENT_ADDR + 0x180000860UL)
  96 #define APECS_IOC_B4BAR                 (IDENT_ADDR + 0x180000880UL)
  97 #define APECS_IOC_B5BAR                 (IDENT_ADDR + 0x1800008A0UL)
  98 #define APECS_IOC_B6BAR                 (IDENT_ADDR + 0x1800008C0UL)
  99 #define APECS_IOC_B7BAR                 (IDENT_ADDR + 0x1800008E0UL)
 100 #define APECS_IOC_B8BAR                 (IDENT_ADDR + 0x180000900UL)
 101 
 102 /* Bank x Configuration Register */
 103 #define APECS_IOC_B0BCR                 (IDENT_ADDR + 0x180000A00UL)
 104 #define APECS_IOC_B1BCR                 (IDENT_ADDR + 0x180000A20UL)
 105 #define APECS_IOC_B2BCR                 (IDENT_ADDR + 0x180000A40UL)
 106 #define APECS_IOC_B3BCR                 (IDENT_ADDR + 0x180000A60UL)
 107 #define APECS_IOC_B4BCR                 (IDENT_ADDR + 0x180000A80UL)
 108 #define APECS_IOC_B5BCR                 (IDENT_ADDR + 0x180000AA0UL)
 109 #define APECS_IOC_B6BCR                 (IDENT_ADDR + 0x180000AC0UL)
 110 #define APECS_IOC_B7BCR                 (IDENT_ADDR + 0x180000AE0UL)
 111 #define APECS_IOC_B8BCR                 (IDENT_ADDR + 0x180000B00UL)
 112 
 113 /* Bank x Timing Register A */
 114 #define APECS_IOC_B0TRA                 (IDENT_ADDR + 0x180000C00UL)
 115 #define APECS_IOC_B1TRA                 (IDENT_ADDR + 0x180000C20UL)
 116 #define APECS_IOC_B2TRA                 (IDENT_ADDR + 0x180000C40UL)
 117 #define APECS_IOC_B3TRA                 (IDENT_ADDR + 0x180000C60UL)
 118 #define APECS_IOC_B4TRA                 (IDENT_ADDR + 0x180000C80UL)
 119 #define APECS_IOC_B5TRA                 (IDENT_ADDR + 0x180000CA0UL)
 120 #define APECS_IOC_B6TRA                 (IDENT_ADDR + 0x180000CC0UL)
 121 #define APECS_IOC_B7TRA                 (IDENT_ADDR + 0x180000CE0UL)
 122 #define APECS_IOC_B8TRA                 (IDENT_ADDR + 0x180000D00UL)
 123 
 124 /* Bank x Timing Register B */
 125 #define APECS_IOC_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
 126 #define APECS_IOC_B1TRB                 (IDENT_ADDR + 0x180000E20UL)
 127 #define APECS_IOC_B2TRB                 (IDENT_ADDR + 0x180000E40UL)
 128 #define APECS_IOC_B3TRB                 (IDENT_ADDR + 0x180000E60UL)
 129 #define APECS_IOC_B4TRB                 (IDENT_ADDR + 0x180000E80UL)
 130 #define APECS_IOC_B5TRB                 (IDENT_ADDR + 0x180000EA0UL)
 131 #define APECS_IOC_B6TRB                 (IDENT_ADDR + 0x180000EC0UL)
 132 #define APECS_IOC_B7TRB                 (IDENT_ADDR + 0x180000EE0UL)
 133 #define APECS_IOC_B8TRB                 (IDENT_ADDR + 0x180000F00UL)
 134 
 135 
 136 /*
 137  * Memory spaces:
 138  */
 139 #define APECS_IACK_SC                   (IDENT_ADDR + 0x1b0000000UL)
 140 #define APECS_CONF                      (IDENT_ADDR + 0x1e0000000UL)
 141 #define APECS_IO                        (IDENT_ADDR + 0x1c0000000UL)
 142 #define APECS_SPARSE_MEM                (IDENT_ADDR + 0x200000000UL)
 143 #define APECS_DENSE_MEM                 (IDENT_ADDR + 0x300000000UL)
 144 
 145 /*
 146  * Bit definitions for I/O Controller status register 0:
 147  */
 148 #define APECS_IOC_STAT0_CMD             0xf
 149 #define APECS_IOC_STAT0_ERR             (1<<4)
 150 #define APECS_IOC_STAT0_LOST            (1<<5)
 151 #define APECS_IOC_STAT0_THIT            (1<<6)
 152 #define APECS_IOC_STAT0_TREF            (1<<7)
 153 #define APECS_IOC_STAT0_CODE_SHIFT      8
 154 #define APECS_IOC_STAT0_CODE_MASK       0x7
 155 #define APECS_IOC_STAT0_P_NBR_SHIFT     13
 156 #define APECS_IOC_STAT0_P_NBR_MASK      0x7ffff
 157 
 158 #define HAE_ADDRESS     APECS_IOC_HAXR1
 159 
 160 #ifdef __KERNEL__
 161 
 162 /*
 163  * Translate physical memory address as seen on (PCI) bus into
 164  * a kernel virtual address and vv.
 165  */
 166 extern inline unsigned long virt_to_bus(void * address)
     /*  */
 167 {
 168         return virt_to_phys(address) + APECS_DMA_WIN_BASE;
 169 }
 170 
 171 extern inline void * bus_to_virt(unsigned long address)
     /*  */
 172 {
 173         /*
 174          * This check is a sanity check but also ensures that bus
 175          * address 0 maps to virtual address 0 which is useful to
 176          * detect null "pointers" (the NCR driver is much simpler if
 177          * NULL pointers are preserved).
 178          */
 179         if (address < APECS_DMA_WIN_BASE)
 180                 return 0;
 181         return phys_to_virt(address - APECS_DMA_WIN_BASE);
 182 }
 183 
 184 /*
 185  * I/O functions:
 186  *
 187  * Unlike Jensen, the APECS machines have no concept of local
 188  * I/O---everything goes over the PCI bus.
 189  *
 190  * There is plenty room for optimization here.  In particular,
 191  * the Alpha's insb/insw/extb/extw should be useful in moving
 192  * data to/from the right byte-lanes.
 193  */
 194 
 195 #define vuip    volatile unsigned int *
 196 
 197 extern inline unsigned int __inb(unsigned long addr)
     /*  */
 198 {
 199         long result = *(vuip) ((addr << 5) + APECS_IO + 0x00);
 200         result >>= (addr & 3) * 8;
 201         return 0xffUL & result;
 202 }
 203 
 204 extern inline void __outb(unsigned char b, unsigned long addr)
     /*  */
 205 {
 206         unsigned int w;
 207 
 208         asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 209         *(vuip) ((addr << 5) + APECS_IO + 0x00) = w;
 210         mb();
 211 }
 212 
 213 extern inline unsigned int __inw(unsigned long addr)
     /*  */
 214 {
 215         long result = *(vuip) ((addr << 5) + APECS_IO + 0x08);
 216         result >>= (addr & 3) * 8;
 217         return 0xffffUL & result;
 218 }
 219 
 220 extern inline void __outw(unsigned short b, unsigned long addr)
     /*  */
 221 {
 222         unsigned int w;
 223 
 224         asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 225         *(vuip) ((addr << 5) + APECS_IO + 0x08) = w;
 226         mb();
 227 }
 228 
 229 extern inline unsigned int __inl(unsigned long addr)
     /*  */
 230 {
 231         return *(vuip) ((addr << 5) + APECS_IO + 0x18);
 232 }
 233 
 234 extern inline void __outl(unsigned int b, unsigned long addr)
     /*  */
 235 {
 236         *(vuip) ((addr << 5) + APECS_IO + 0x18) = b;
 237         mb();
 238 }
 239 
 240 
 241 /*
 242  * Memory functions.  64-bit and 32-bit accesses are done through
 243  * dense memory space, everything else through sparse space.
 244  */
 245 extern inline unsigned long __readb(unsigned long addr)
     /*  */
 246 {
 247         unsigned long result, shift, msb;
 248 
 249         shift = (addr & 0x3) * 8;
 250         if (addr >= (1UL << 24)) {
 251                 msb = addr & 0xf8000000;
 252                 addr -= msb;
 253                 if (msb != hae.cache) {
 254                         set_hae(msb);
 255                 }
 256         }
 257         result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00);
 258         result >>= shift;
 259         return 0xffUL & result;
 260 }
 261 
 262 extern inline unsigned long __readw(unsigned long addr)
     /*  */
 263 {
 264         unsigned long result, shift, msb;
 265 
 266         shift = (addr & 0x3) * 8;
 267         if (addr >= (1UL << 24)) {
 268                 msb = addr & 0xf8000000;
 269                 addr -= msb;
 270                 if (msb != hae.cache) {
 271                         set_hae(msb);
 272                 }
 273         }
 274         result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08);
 275         result >>= shift;
 276         return 0xffffUL & result;
 277 }
 278 
 279 extern inline unsigned long __readl(unsigned long addr)
     /*  */
 280 {
 281         return *(vuip) (addr + APECS_DENSE_MEM);
 282 }
 283 
 284 extern inline void __writeb(unsigned char b, unsigned long addr)
     /*  */
 285 {
 286         unsigned long msb;
 287 
 288         if (addr >= (1UL << 24)) {
 289                 msb = addr & 0xf8000000;
 290                 addr -= msb;
 291                 if (msb != hae.cache) {
 292                         set_hae(msb);
 293                 }
 294         }
 295         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101;
 296 }
 297 
 298 extern inline void __writew(unsigned short b, unsigned long addr)
     /*  */
 299 {
 300         unsigned long msb;
 301 
 302         if (addr >= (1UL << 24)) {
 303                 msb = addr & 0xf8000000;
 304                 addr -= msb;
 305                 if (msb != hae.cache) {
 306                         set_hae(msb);
 307                 }
 308         }
 309         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001;
 310 }
 311 
 312 extern inline void __writel(unsigned int b, unsigned long addr)
     /*  */
 313 {
 314         *(vuip) (addr + APECS_DENSE_MEM) = b;
 315 }
 316 
 317 #define inb(port) \
 318 (__builtin_constant_p((port))?__inb(port):_inb(port))
 319 
 320 #define outb(x, port) \
 321 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 322 
 323 #define readl(a)        __readl((unsigned long)(a))
 324 #define writel(v,a)     __writel((v),(unsigned long)(a))
 325 
 326 #undef vuip
 327 
 328 extern unsigned long apecs_init (unsigned long mem_start,
 329                                  unsigned long mem_end);
 330 
 331 #endif /* __KERNEL__ */
 332 
 333 /*
 334  * Data structure for handling APECS machine checks:
 335  */
 336 struct el_apecs_sysdata_mcheck {
 337     u_long      coma_gcr;                       
 338     u_long      coma_edsr;                      
 339     u_long      coma_ter;                       
 340     u_long      coma_elar;                      
 341     u_long      coma_ehar;                      
 342     u_long      coma_ldlr;                      
 343     u_long      coma_ldhr;                      
 344     u_long      coma_base0;                     
 345     u_long      coma_base1;                     
 346     u_long      coma_base2;                     
 347     u_long      coma_cnfg0;                     
 348     u_long      coma_cnfg1;                     
 349     u_long      coma_cnfg2;                     
 350     u_long      epic_dcsr;                      
 351     u_long      epic_pear;                      
 352     u_long      epic_sear;                      
 353     u_long      epic_tbr1;                      
 354     u_long      epic_tbr2;                      
 355     u_long      epic_pbr1;                      
 356     u_long      epic_pbr2;                      
 357     u_long      epic_pmr1;                      
 358     u_long      epic_pmr2;                      
 359     u_long      epic_harx1;                     
 360     u_long      epic_harx2;                     
 361     u_long      epic_pmlt;                      
 362     u_long      epic_tag0;                      
 363     u_long      epic_tag1;                      
 364     u_long      epic_tag2;                      
 365     u_long      epic_tag3;                      
 366     u_long      epic_tag4;                      
 367     u_long      epic_tag5;                      
 368     u_long      epic_tag6;                      
 369     u_long      epic_tag7;                      
 370     u_long      epic_data0;                     
 371     u_long      epic_data1;                     
 372     u_long      epic_data2;                     
 373     u_long      epic_data3;                     
 374     u_long      epic_data4;                     
 375     u_long      epic_data5;                     
 376     u_long      epic_data6;                     
 377     u_long      epic_data7;                     
 378 };
 379 
 380 #define RTC_PORT(x)     (0x70 + (x))
 381 #define RTC_ADDR(x)     (0x80 | (x))
 382 #define RTC_ALWAYS_BCD  0
 383 
 384 #endif /* __ALPHA_APECS__H__ */
/* */
root/include/asm-alpha/apecs.h

INCLUDED FROM

DEFINITIONS
