1 /* 2 * include/asm-mips/cachectl.h 3 * 4 * Written by Ralf Baechle, 5 * Copyright (C) 1994 by Waldorf GMBH 6 */ 7 #ifndef __ASM_MIPS_CACHECTL 8 #define __ASM_MIPS_CACHECTL 9 10 /* 11 * cachectl.h -- defines for MIPS cache control system calls 12 */ 13 14 /* 15 * Options for cacheflush system call 16 */ 17 #define ICACHE (1<<0) /* flush instruction cache */ 18 #define DCACHE (1<<1) /* writeback and flush data cache */ 19 #define BCACHE (ICACHE|DCACHE) /* flush both caches */ 20 21 #ifdef __KERNEL__ 22 #define CACHELINES 512 /* number of cachelines (kludgy) */ 23 24 /* 25 * Cache Operations - for use by assembler code 26 */ 27 #define Index_Invalidate_I 0x00 28 #define Index_Writeback_Inv_D 0x01 29 #define Index_Load_Tag_D 0x05 30 31 #ifndef __LANGUAGE_ASSEMBLY__ 32 33 extern int sys_cacheflush(void *addr, int nbytes, int cache); 34 35 #endif /* !__LANGUAGE_ASSEMBLY__ */ 36 #endif /* __KERNEL__ */ 37 #endif /* __ASM_MIPS_CACHECTL */