include/asm-mips/jazz.h

/* */
This source file includes following definitions.
pica_set_led
r4030_read_reg16
r4030_read_reg32
r4030_write_reg16
r4030_write_reg32
   1 /*
   2  * Hardware info about Mips JAZZ and similar systems
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995 by Andreas Busse and Ralf Baechle
   9  *
  10  * This file is a mess. It really needs some reorganisation!
  11  */
  12 
  13 #ifndef __ASM_MIPS_JAZZ_H 
  14 #define __ASM_MIPS_JAZZ_H 
  15 
  16 /*
  17  * The addresses below are virtual address. The mappings are
  18  * created on startup via wired entries in the tlb. The Mips
  19  * Magnum R3000 and R4000 machines are similar in many aspects,
  20  * but many hardware register are accessible at 0xb9000000 in
  21  * instead of 0xe0000000.
  22  */
  23 
  24 #define JAZZ_LOCAL_IO_SPACE     0xe0000000
  25 
  26 /*
  27  * Revision numbers in PICA_ASIC_REVISION
  28  *
  29  * 0xf0000000 - Rev1
  30  * 0xf0000001 - Rev2
  31  * 0xf0000002 - Rev3
  32  */
  33 #define PICA_ASIC_REVISION      0xe0000008
  34 
  35 /*
  36  * The segments of the seven segment LED are mapped
  37  * to the control bits as follows:
  38  *
  39  *         (7)
  40  *      ---------
  41  *      |       |
  42  *  (2) |       | (6)
  43  *      |  (1)  |
  44  *      ---------
  45  *      |       |
  46  *  (3) |       | (5)
  47  *      |  (4)  |
  48  *      --------- . (0)
  49  */
  50 #define PICA_LED                0xe000f000
  51 
  52 /*
  53  * Some characters for the LED control registers
  54  * The original Mips machines seem to have a LED display
  55  * with integrated decoder while the Acer machines can
  56  * control each of the seven segments and the dot independend.
  57  * It's only a toy, anyway...
  58  */
  59 #define LED_DOT                 0x01
  60 #define LED_SPACE               0x00
  61 #define LED_0                   0xfc
  62 #define LED_1                   0x60
  63 #define LED_2                   0xda
  64 #define LED_3                   0xf2
  65 #define LED_4                   0x66
  66 #define LED_5                   0xb6
  67 #define LED_6                   0xbe
  68 #define LED_7                   0xe0
  69 #define LED_8                   0xfe
  70 #define LED_9                   0xf6
  71 #define LED_A                   0xee
  72 #define LED_b                   0x3e
  73 #define LED_C                   0x9c
  74 #define LED_d                   0x7a
  75 #define LED_E                   0x9e
  76 #define LED_F                   0x8e
  77 
  78 #ifndef __LANGUAGE_ASSEMBLY__
  79 
  80 extern __inline__ void pica_set_led(unsigned int bits)
     /*  */
  81 {
  82         volatile unsigned int *led_register = (unsigned int *) PICA_LED;
  83 
  84         *led_register = bits;
  85 }
  86 
  87 #endif
  88 
  89 /*
  90  * i8042 keyboard controller for JAZZ and PICA chipsets.
  91  * This address is just a guess and seems to differ from
  92  * other mips machines such as RC3xxx...
  93  */
  94 #define JAZZ_KEYBOARD_ADDRESS   0xe0005000
  95 #define JAZZ_KEYBOARD_DATA      0xe0005000
  96 #define JAZZ_KEYBOARD_COMMAND   0xe0005001
  97 
  98 #ifndef __LANGUAGE_ASSEMBLY__
  99 
 100 typedef struct {
 101         unsigned char data;
 102         unsigned char command;
 103 } jazz_keyboard_hardware;
 104 
 105 typedef struct {
 106         unsigned char pad0[3];
 107         unsigned char data;
 108         unsigned char pad1[3];
 109         unsigned char command;
 110 } mips_keyboard_hardware;
 111 
 112 /*
 113  * For now. Needs to be changed for RC3xxx support. See below.
 114  */
 115 #define keyboard_hardware       jazz_keyboard_hardware
 116 
 117 #endif
 118 
 119 /*
 120  * i8042 keyboard controller for most other Mips machines.
 121  */
 122 #define MIPS_KEYBOARD_ADDRESS   0xb9005000
 123 #define MIPS_KEYBOARD_DATA      0xb9005003
 124 #define MIPS_KEYBOARD_COMMAND   0xb9005007
 125 
 126 /*
 127  * Serial and parallel ports (WD 16C552) on the Mips JAZZ
 128  */
 129 #define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
 130 #define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
 131 #define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
 132 
 133 /*
 134  * Dummy Device Address. Used in jazzdma.c
 135  */
 136 #define JAZZ_DUMMY_DEVICE       0xe000d000
 137      
 138 /*
 139  * JAZZ timer registers and interrupt no.
 140  * Note that the hardware timer interrupt is actually on
 141  * cpu level 6, but to keep compatibility with PC stuff
 142  * it is remapped to vector 0. See arch/mips/kernel/entry.S.
 143  */
 144 #define JAZZ_TIMER_INTERVAL     0xe0000228
 145 #define JAZZ_TIMER_REGISTER     0xe0000230
 146 
 147 /*
 148  * DRAM configuration register
 149  */
 150 #ifndef __LANGUAGE_ASSEMBLY__
 151 #ifdef __MIPSEL__
 152 typedef struct {
 153         unsigned int bank2 : 3;
 154         unsigned int bank1 : 3;
 155         unsigned int mem_bus_width : 1;
 156         unsigned int reserved2 : 1;
 157         unsigned int page_mode : 1;
 158         unsigned int reserved1 : 23;
 159 } dram_configuration;
 160 #else /* defined (__MIPSEB__) */
 161 typedef struct {
 162         unsigned int reserved1 : 23;
 163         unsigned int page_mode : 1;
 164         unsigned int reserved2 : 1;
 165         unsigned int mem_bus_width : 1;
 166         unsigned int bank1 : 3;
 167         unsigned int bank2 : 3;
 168 } dram_configuration;
 169 #endif
 170 #endif /* __LANGUAGE_ASSEMBLY__ */
 171 
 172 #define PICA_DRAM_CONFIG        0xe00fffe0
 173 
 174 /*
 175  * JAZZ interrupt control registers
 176  */
 177 #define JAZZ_IO_IRQ_SOURCE      0xe0100000
 178 #define JAZZ_IO_IRQ_ENABLE      0xe0100002
 179 
 180 /*
 181  * JAZZ interrupt enable bits
 182  */
 183 #define JAZZ_IE_PARALLEL            (1 << 0)
 184 #define JAZZ_IE_FLOPPY              (1 << 1)
 185 #define JAZZ_IE_SOUND               (1 << 2)
 186 #define JAZZ_IE_VIDEO               (1 << 3)
 187 #define JAZZ_IE_ETHERNET            (1 << 4)
 188 #define JAZZ_IE_SCSI                (1 << 5)
 189 #define JAZZ_IE_KEYBOARD            (1 << 6)
 190 #define JAZZ_IE_MOUSE               (1 << 7)
 191 #define JAZZ_IE_SERIAL1             (1 << 8)
 192 #define JAZZ_IE_SERIAL2             (1 << 9)
 193 
 194 /*
 195  * JAZZ Interrupt Level definitions
 196  */
 197 #define JAZZ_TIMER_IRQ          0
 198 #define JAZZ_KEYBOARD_IRQ       1
 199 #define JAZZ_ETHERNET_IRQ       2 /* 15 */
 200 #define JAZZ_SERIAL1_IRQ        3
 201 #define JAZZ_SERIAL2_IRQ        4
 202 #define JAZZ_PARALLEL_IRQ       5
 203 #define JAZZ_FLOPPY_IRQ         6 /* needs to be consistent with floppy driver! */
 204 
 205 
 206 /*
 207  * JAZZ DMA Channels
 208  * Note: Channels 4...7 are not used with respect to the Acer PICA-61
 209  * chipset which does not provide these DMA channels.
 210  */
 211 #define JAZZ_SCSI_DMA           0              /* SCSI */
 212 #define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
 213 #define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
 214 #define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
 215 
 216 /*
 217  * JAZZ R4030 MCT_ADR chip (DMA controller)
 218  * Note: Virtual Addresses !
 219  */
 220 #define JAZZ_R4030_CONFIG       0xE0000000      /* R4030 config register */
 221 #define JAZZ_R4030_REVISION     0xE0000008      /* same as PICA_ASIC_REVISION */
 222 #define JAZZ_R4030_INV_ADDR     0xE0000010      /* Invalid Address register */
 223 
 224 #define JAZZ_R4030_TRSTBL_BASE  0xE0000018      /* Translation Table Base */
 225 #define JAZZ_R4030_TRSTBL_LIM   0xE0000020      /* Translation Table Limit */
 226 #define JAZZ_R4030_TRSTBL_INV   0xE0000028      /* Translation Table Invalidate */
 227 
 228 #define JAZZ_R4030_CACHE_MTNC   0xE0000030      /* Cache Maintenance */
 229 #define JAZZ_R4030_R_FAIL_ADDR  0xE0000038      /* Remote Failed Address */
 230 #define JAZZ_R4030_M_FAIL_ADDR  0xE0000040      /* Memory Failed Adresss */
 231 
 232 #define JAZZ_R4030_CACHE_PTAG   0xE0000048      /* I/O Cache Physical Tag */
 233 #define JAZZ_R4030_CACHE_LTAG   0xE0000050      /* I/O Cache Logical Tag */
 234 #define JAZZ_R4030_CACHE_BMASK  0xE0000058      /* I/O Cache Byte Mask */
 235 #define JAZZ_R4030_CACHE_BWIN   0xE0000060      /* I/O Cache Buffer Window */
 236 
 237 /*
 238  * Remote Speed Registers. 
 239  *
 240  *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
 241  *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
 242  *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
 243  * 12: reserved, 13: free,     14: 7seg LED, 15: ???
 244  */
 245 #define JAZZ_R4030_REM_SPEED    0xE0000070      /* 16 Remote Speed Registers */
 246                                                 /* 0xE0000070,78,80... 0xE00000E8 */
 247 #define JAZZ_R4030_IRQ_ENABLE   0xE00000E8      /* Internal Interrupt Enable */
 248 
 249 #define JAZZ_R4030_IRQ_SOURCE   0xE0000200      /* Interrupt Source Reg */
 250 #define JAZZ_R4030_I386_ERROR   0xE0000208      /* i386/EISA Bus Error */
 251 
 252 
 253 /*
 254  * Access the R4030 DMA and I/O Controller
 255  */
 256 #ifndef __LANGUAGE_ASSEMBLY__
 257 
 258 extern inline unsigned short r4030_read_reg16(unsigned addr) {
     /*  */
 259         unsigned short ret = *((volatile unsigned short *)addr);
 260         __asm__ __volatile__(
 261                 ".set\tnoreorder\n\t"
 262                 "nop\n\t"
 263                 "nop\n\t"
 264                 "nop\n\t"
 265                 "nop\n\t"
 266                 ".set\treorder");
 267         return ret;
 268 }
 269 
 270 extern inline unsigned int r4030_read_reg32(unsigned addr) {
     /*  */
 271         unsigned int ret = *((volatile unsigned int *)addr);
 272         __asm__ __volatile__(
 273                 ".set\tnoreorder\n\t"
 274                 "nop\n\t"
 275                 "nop\n\t"
 276                 "nop\n\t"
 277                 "nop\n\t"
 278                 ".set\treorder");
 279         return ret;
 280 }
 281 
 282 extern inline void r4030_write_reg16(unsigned addr, unsigned val) {
     /*  */
 283         *((volatile unsigned short *)addr) = val;
 284         __asm__ __volatile__(
 285                 ".set\tnoreorder\n\t"
 286                 "nop\n\t"
 287                 "nop\n\t"
 288                 "nop\n\t"
 289                 "nop\n\t"
 290                 ".set\treorder");
 291 }
 292 
 293 extern inline unsigned int r4030_write_reg32(unsigned addr, unsigned val) {
     /*  */
 294         *((volatile unsigned int *)addr) = val;
 295         __asm__ __volatile__(
 296                 ".set\tnoreorder\n\t"
 297                 "nop\n\t"
 298                 "nop\n\t"
 299                 "nop\n\t"
 300                 "nop\n\t"
 301                 ".set\treorder");
 302 }
 303 
 304 #endif /* !LANGUAGE_ASSEMBLY__ */
 305 
 306 #define JAZZ_FDC_BASE 0xe0003000
 307 
 308 #define JAZZ_RTC_BASE 0xe0004000
 309 
 310 #endif /* __ASM_MIPS_JAZZ_H */
/* */
root/include/asm-mips/jazz.h

INCLUDED FROM

DEFINITIONS
