This source file includes following definitions.
- xchg_u32
- xchg_u64
- __xchg
1 #ifndef __ALPHA_SYSTEM_H
2 #define __ALPHA_SYSTEM_H
3
4 #include <asm/pal.h>
5
6
7
8
9
10
11
12
13
14
15
16
17
18 #define BOOT_PCB 0x20000000
19 #define BOOT_ADDR 0x20000000
20 #define BOOT_SIZE (16*1024)
21
22 #define KERNEL_START 0xfffffc0000300000
23 #define SWAPPER_PGD 0xfffffc0000300000
24 #define INIT_STACK 0xfffffc0000302000
25 #define EMPTY_PGT 0xfffffc0000304000
26 #define EMPTY_PGE 0xfffffc0000308000
27 #define ZERO_PGE 0xfffffc000030A000
28
29 #define START_ADDR 0xfffffc0000310000
30 #define START_SIZE (2*1024*1024)
31
32 #ifndef __ASSEMBLY__
33
34
35
36
37
38 struct el_common {
39 unsigned int size;
40 int sbz1 : 31;
41 char retry : 1;
42 unsigned int proc_offset;
43 unsigned int sys_offset;
44 };
45
46 extern void wrent(void *, unsigned long);
47 extern void wrkgp(unsigned long);
48 extern void wrusp(unsigned long);
49 extern unsigned long rdusp(void);
50 extern unsigned long rdmces (void);
51 extern void wrmces (unsigned long);
52
53 #define halt() __asm__ __volatile__(".long 0");
54
55 extern void alpha_switch_to(unsigned long pctxp);
56
57 #define switch_to(p) do { \
58 current_set[0] = p; \
59 alpha_switch_to((unsigned long) &(p)->tss - 0xfffffc0000000000); \
60 } while (0)
61
62 #define mb() \
63 __asm__ __volatile__("mb": : :"memory")
64
65 #define draina() \
66 __asm__ __volatile__ ("call_pal %0" : : "i" (PAL_draina) : "memory")
67
68 #define getipl() \
69 ({ unsigned long __old_ipl; \
70 __asm__ __volatile__( \
71 "call_pal 54\n\t" \
72 "bis $0,$0,%0" \
73 : "=r" (__old_ipl) \
74 : : "$0", "$1", "$16", "$22", "$23", "$24", "$25"); \
75 __old_ipl; })
76
77 #define setipl(__new_ipl) \
78 __asm__ __volatile__( \
79 "bis %0,%0,$16\n\t" \
80 "call_pal 53" \
81 : : "r" (__new_ipl) \
82 : "$0", "$1", "$16", "$22", "$23", "$24", "$25", "memory")
83
84 #define swpipl(__new_ipl) \
85 ({ unsigned long __old_ipl; \
86 __asm__ __volatile__( \
87 "bis %1,%1,$16\n\t" \
88 "call_pal 53\n\t" \
89 "bis $0,$0,%0" \
90 : "=r" (__old_ipl) \
91 : "r" (__new_ipl) \
92 : "$0", "$1", "$16", "$22", "$23", "$24", "$25", "memory"); \
93 __old_ipl; })
94
95 #define cli() setipl(7)
96 #define sti() setipl(0)
97 #define save_flags(flags) do { flags = getipl(); } while (0)
98 #define restore_flags(flags) setipl(flags)
99
100
101
102
103 extern inline unsigned long xchg_u32 (volatile int * m, unsigned long val);
104 extern inline unsigned long xchg_u64 (volatile long * m, unsigned long val);
105
106 extern inline unsigned long xchg_u32(volatile int * m, unsigned long val)
107 {
108 unsigned long dummy, dummy2;
109
110 __asm__ __volatile__(
111 "\n1:\t"
112 "ldl_l %0,0(%1)\n\t"
113 "bis %2,%2,%3\n\t"
114 "stl_c %3,0(%1)\n\t"
115 "beq %3,1b\n"
116 : "=r" (val), "=r" (m), "=r" (dummy), "=r" (dummy2)
117 : "1" (m), "2" (val)
118 : "memory");
119 return val;
120 }
121
122 extern inline unsigned long xchg_u64(volatile long * m, unsigned long val)
123 {
124 unsigned long dummy, dummy2;
125
126 __asm__ __volatile__(
127 "\n1:\t"
128 "ldq_l %0,0(%1)\n\t"
129 "bis %2,%2,%3\n\t"
130 "stq_c %3,0(%1)\n\t"
131 "beq %3,1b\n"
132 : "=r" (val), "=r" (m), "=r" (dummy), "=r" (dummy2)
133 : "1" (m), "2" (val)
134 : "memory");
135 return val;
136 }
137
138 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
139 #define tas(ptr) (xchg((ptr),1))
140
141
142
143
144
145
146
147
148
149 extern void __xchg_called_with_bad_pointer(void);
150
151 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
152 {
153 switch (size) {
154 case 4:
155 return xchg_u32(ptr, x);
156 case 8:
157 return xchg_u64(ptr, x);
158 }
159 __xchg_called_with_bad_pointer();
160 return x;
161 }
162
163 #endif
164
165 #endif