include/asm-sparc/irq.h

/* */
   1 /* $Id: irq.h,v 1.8 1995/11/25 02:31:54 davem Exp $
   2  * irq.h: IRQ registers on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _SPARC_IRQ_H
   8 #define _SPARC_IRQ_H
   9 
  10 #include <linux/linkage.h>
  11 
  12 #include <asm/system.h>     /* For NCPUS */
  13 
  14 #define NR_IRQS    15
  15 
  16 extern void disable_irq(unsigned int);
  17 extern void enable_irq(unsigned int);
  18 
  19 extern int request_fast_irq(unsigned int irq, void (*handler)(int, struct pt_regs *), unsigned long flags, const char *devname);
  20 
  21 /* On the sun4m, just like the timers, we have both per-cpu and master
  22  * interrupt registers.
  23  */
  24 
  25 /* These registers are used for sending/receiving irqs from/to
  26  * different cpu's.   
  27  */
  28 struct sun4m_intreg_percpu {
  29         unsigned int tbt;        /* Interrupts still pending for this cpu. */
  30 
  31         /* These next two registers are WRITE-ONLY and are only
  32          * "on bit" sensitive, "off bits" written have NO affect.
  33          */
  34         unsigned int clear;  /* Clear this cpus irqs here. */
  35         unsigned int set;    /* Set this cpus irqs here. */
  36         unsigned char space[PAGE_SIZE - 12];
  37 };
  38 
  39 struct sun4m_intregs {
  40         struct sun4m_intreg_percpu cpu_intregs[NCPUS];
  41         unsigned int tbt;                /* IRQ's that are still pending. */
  42         unsigned int irqs;               /* Master IRQ bits. */
  43 
  44         /* Again, like the above, two these registers are WRITE-ONLY. */
  45         unsigned int clear;              /* Clear master IRQ's by setting bits here. */
  46         unsigned int set;                /* Set master IRQ's by setting bits here. */
  47 
  48         /* This register is both READ and WRITE. */
  49         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
  50 };
  51 
  52 extern struct sun4m_intregs *sun4m_interrupts;
  53 
  54 /* Bit field defines for the interrupt registers on various
  55  * Sparc machines.
  56  */
  57 
  58 /* The sun4c interrupt register. */
  59 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  60 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  61 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  62 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  63 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  64 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  65 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  66 
  67 /* The sun4m interrupt registers.  MUST RESEARCH THESE SOME MORE XXX */
  68 #define SUN4M_INT_ENABLE  0x80000000
  69 #define SUN4M_INT_E14     0x00000080
  70 #define SUN4M_INT_E10     0x00080000
  71 
  72 #endif
/* */
root/include/asm-sparc/irq.h

INCLUDED FROM
