root/drivers/net/ibmtr.h

/* */

INCLUDED FROM

   1 /* Definitions for an IBM Token Ring card. */
   2 /* This file is distributed under the GNU GPL   */
   3 
   4 #define TR_RETRY_INTERVAL 500
   5 #define TR_ISA 1
   6 #define TR_MCA 2
   7 #define TR_ISAPNP 3
   8 #define NOTOK 0
   9 #define TOKDEBUG 1
  10 
  11 #ifndef IBMTR_SHARED_RAM_BASE
  12 #define IBMTR_SHARED_RAM_BASE 0xD0
  13 #define IBMTR_SHARED_RAM_SIZE 0x10
  14 #endif
  15 
  16 #define CHANNEL_ID      0X1F30
  17 #define AIP             0X1F00
  18 #define AIPCHKSUM1      0X1F60
  19 #define AIPCHKSUM2      0X1FF0
  20 #define AIPADAPTYPE     0X1FA0
  21 #define AIPDATARATE     0X1FA2
  22 #define AIPEARLYTOKEN   0X1FA4
  23 #define AIPAVAILSHRAM   0X1FA6
  24 #define AIPSHRAMPAGE    0X1FA8
  25 #define AIP4MBDHB       0X1FAA
  26 #define AIP16MBDHB      0X1FAC
  27 #define AIPFID          0X1FBA
  28 
  29 /* Note, 0xA20 == 0x220 since motherboard decodes 10 bits.  I left everything
  30    the way my documentation had it, ie: 0x0A20.     */
  31 #define ADAPTINTCNTRL   0x02f0  /* Adapter interrupt control */
  32 #define ADAPTRESET      0x1     /* Control Adapter reset (add to base) */
  33 #define ADAPTRESETREL   0x2     /* Release Adapter from reset ( """)  */
  34 #define ADAPTINTREL     0x3     /* Adapter interrupt release */
  35 
  36 #define MMIOStartLocP   0x0a20  /* Primary adapter's starting MMIO area */
  37 #define MMIOStartLocA   0x0a24  /* Alternate adapter's starting MMIO area */
  38 
  39 #define TR_IO_EXTENT    4       /* size of used IO range */
  40 
  41 #define GLOBAL_INT_ENABLE 0x02f0
  42 
  43 /* MMIO bits 0-4 select register */
  44 #define RRR_EVEN        0x00    /* Shared RAM relocation registers - even and odd */
  45 /* Used to set the starting address of shared RAM  */
  46 /* Bits 1 through 7 of this register map to bits 13 through 19 of the shared RAM address.*/
  47 /* ie: 0x02 sets RAM address to ...ato!  issy su wazzoo !! GODZILLA!!! */
  48 #define RRR_ODD         0x01
  49 /* Bits 2 and 3 of this register can be read to determine shared RAM size */
  50 /* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k  */
  51 #define WRBR_EVEN       0x02    /* Write region base registers - even and odd */
  52 #define WRBR_ODD        0x03
  53 #define WWCR_EVEN       0x04    /* Write window close registers - even and odd */
  54 #define WWCR_ODD        0x05
  55 #define WWOR_EVEN       0x06    /* Write window open registers - even and odd */
  56 #define WWOR_ODD        0x07
  57 
  58 /* Interrupt status registers - PC system  - even and odd */
  59 #define ISRP_EVEN       0x08
  60 
  61 #define TCR_INT 0x10    /* Bit 4 - Timer interrupt.  The TVR_EVEN timer has
  62                                                                    expired. */
  63 #define ERR_INT 0x08    /* Bit 3 - Error interrupt.  The adapter has had an
  64                                                                    internal error. */
  65 #define ACCESS_INT 0x04    /* Bit 2 - Access interrupt.  You have attempted to
  66                                                            write to an invalid area of shared RAM or an invalid
  67                                                                    register within the MMIO. */
  68 /*      In addition, the following bits within ISRP_EVEN can be turned on or off by you */
  69 /*      to control the interrupt processing:   */
  70 #define INT_IRQ 0x80    /* Bit 7 - If 0 the adapter will issue a CHCK, if 1 and
  71                                                               IRQ.  This should normally be set (by you) to 1.  */
  72 #define INT_ENABLE 0x40 /* Bit 6 - Interrupt enable.  If 0, no interrupts will
  73                                                                    occur.  If 1, interrupts will occur normally.
  74                                                                    Normally set to 1.  */
  75 /* Bit 0 - Primary or alternate adapter.  Set to zero if this adapter is the primary adapter,*/
  76 /*         1 if this adapter is the alternate adapter. */
  77 
  78 
  79 #define ISRP_ODD        0x09
  80 
  81 #define ADAP_CHK_INT 0x40 /* Bit 6 - Adapter check.  the adapter has
  82                              encountered a serious problem and has closed
  83                              itself.  Whoa.  */
  84 #define SRB_RESP_INT 0x20 /* Bit 5 - SRB response.  The adapter has accepted
  85                              an SRB request and set the return code withing
  86                              the SRB. */
  87 #define ASB_FREE_INT 0x10 /* Bit 4 - ASB free.  The adapter has read the ASB
  88                                                                           and this area can be safely reused. This interrupt
  89                                                                           is only used if your application has set the ASB
  90                                                                           free request bit in ISRA_ODD or if an error was
  91                                                                 detected in your response. */
  92 #define ARB_CMD_INT  0x08 /* Bit 3 - ARB command.  The adapter has given you a
  93                                                                           command for action.  The command is located in the
  94                                                                           ARB area of shared memory. */
  95 #define SSB_RESP_INT 0x04 /* Bit 2 - SSB response.  The adapter has posted a
  96                                                                           response to your SRB (the response is located in
  97                                                                           the SSB area of shared memory). */
  98 /* Bit 1 - Bridge frame forward complete. */
  99 
 100 
 101 
 102 #define ISRA_EVEN       0x0A    /* Interrupt status registers - adapter  - even and odd */
 103 /* Bit 7 - Internal parity error (on adapter's internal bus) */
 104 /* Bit 6 - Timer interrupt pending */
 105 /* Bit 5 - Access interrupt (attempt by adapter to access illegal address) */
 106 /* Bit 4 - Adapter microcode problem (microcode dead-man timer expired) */
 107 /* Bit 3 - Adapter processor check status */
 108 /* Bit 2 - Reserved */
 109 /* Bit 1 - Adapter hardware interrupt mask (prevents internal interrupts) */
 110 /* Bit 0 - Adapter software interrupt mask (prevents internal software interrupts) */
 111 
 112 #define ISRA_ODD        0x0B
 113 #define CMD_IN_SRB 0x20 /* Bit 5  - Indicates that you have placed a new
 114                            command in the SRB and are ready for the adapter to
 115                            process the command. */
 116 #define RESP_IN_ASB 0x10 /* Bit 4 - Indicates that you have placed a response
 117                                                                     (an ASB) in the shared RAM which is available for
 118                                                                          the adapter's use. */
 119 /* Bit 3 - Indicates that you are ready to ut an SRB in the shared RAM, but that a previous */
 120 /*         command is still pending.  The adapter will then interrupt you when the previous */
 121 /*         command is completed */
 122 /* Bit 2 - Indicates that you are ready to put an ASB in the shared RAM, but that a previous */
 123 /*         ASB is still pending.  The adapter will then interrupt you when the previous ASB */
 124 /*         is copied.  */
 125 #define ARB_FREE 0x2
 126 #define SSB_FREE 0x1
 127 
 128 #define TCR_EVEN        0x0C    /* Timer control registers - even and odd */
 129 #define TCR_ODD         0x0D
 130 #define TVR_EVEN        0x0E    /* Timer value registers - even and odd */
 131 #define TVR_ODD         0x0F
 132 #define SRPR_EVEN       0x10    /* Shared RAM paging registers - even and odd */
 133 #define SRPR_ENABLE_PAGING 0xc0
 134 #define SRPR_ODD        0x11 /* Not used. */
 135 #define TOKREAD         0x60
 136 #define TOKOR           0x40
 137 #define TOKAND          0x20
 138 #define TOKWRITE        0x00
 139 
 140 /* MMIO bits 5-6 select operation */
 141 /* 00 is used to write to a register */
 142 /* 01 is used to bitwise AND a byte with a register */
 143 /* 10 is used to bitwise OR a byte with a register  */
 144 /* 11 is used to read from a register */
 145 
 146 /* MMIO bits 7-8 select area of interest.. see below */
 147 /* 00 selects attachment control area. */
 148 /* 01 is reserved. */
 149 /* 10 selects adapter identification area A containing the adapter encoded address. */
 150 /* 11 selects the adapter identification area B containing test patterns. */
 151 
 152 #define PCCHANNELID 5049434F3631313039393020
 153 #define MCCHANNELID 4D4152533633583435313820
 154 
 155 #define ACA_OFFSET 0x1e00
 156 #define ACA_SET 0x40
 157 #define ACA_RESET 0x20
 158 #define ACA_RW 0x00
 159 
 160 #ifdef ENABLE_PAGING
 161 #define SET_PAGE(x) (*(unsigned char *) \
 162                          (ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN)\
 163                                                 = (x>>8)&ti.page_mask)
 164 #else
 165 #define SET_PAGE(x)
 166 #endif
 167 
 168 typedef enum { IN_PROGRESS, SUCCES, FAILURE, CLOSED } open_state;
 169 
 170 struct tok_info {
 171         unsigned char irq;
 172         unsigned char *mmio;
 173         unsigned char hw_address[32];
 174         unsigned char adapter_type;
 175         unsigned char data_rate;
 176         unsigned char token_release;
 177         unsigned char avail_shared_ram;
 178         unsigned char shared_ram_paging;
 179         unsigned char dhb_size4mb;
 180         unsigned char dhb_size16mb;
 181 /* Additions by David Morris       */
 182         unsigned char do_tok_int;
 183 #define FIRST_INT 1
 184 #define NOT_FIRST 2
 185         struct wait_queue *wait_for_tok_int;
 186         struct wait_queue *wait_for_reset;
 187         unsigned char sram_base;
 188 /* Additions by Peter De Schrijver */
 189         unsigned char page_mask;     /* mask to select RAM page to Map*/
 190         unsigned char mapped_ram_size;  /* size of RAM page */
 191         unsigned char *sram; /* Shared memory base address */
 192         unsigned char *init_srb;  /* Initial System Request Block address */
 193         unsigned char *srb;  /* System Request Block address */
 194         unsigned char *ssb;  /* System Status Block address */
 195         unsigned char *arb;  /* Adapter Request Block address */
 196         unsigned char *asb;  /* Adapter Status Block address */
 197         unsigned short exsap_station_id;
 198         unsigned short global_int_enable;
 199         struct sk_buff *current_skb;
 200         struct tr_statistics tr_stats;
 201         unsigned char auto_ringspeedsave;
 202         open_state open_status;
 203         
 204 };
 205 
 206 struct srb_init_response {
 207         unsigned char command;
 208         unsigned char init_status;
 209         unsigned char init_status_2;
 210         unsigned char reserved[3];
 211         unsigned short bring_up_code;
 212         unsigned short encoded_address;
 213         unsigned short level_address;
 214         unsigned short adapter_address;
 215         unsigned short parms_address;
 216         unsigned short mac_address;
 217 };
 218 
 219 #define DIR_OPEN_ADAPTER 0x03
 220 
 221 struct dir_open_adapter {
 222         unsigned char command;
 223         char reserved[7];
 224         unsigned short open_options;
 225         unsigned char node_address[6];
 226         unsigned char group_address[4];
 227         unsigned char funct_address[4];
 228         unsigned short num_rcv_buf;
 229         unsigned short rcv_buf_len;
 230         unsigned short dhb_length;
 231         unsigned char num_dhb;
 232         char reserved2;
 233         unsigned char dlc_max_sap;
 234         unsigned char dlc_max_sta;
 235         unsigned char dlc_max_gsap;
 236         unsigned char dlc_max_gmem;
 237         unsigned char dlc_t1_tick_1;
 238         unsigned char dlc_t2_tick_1;
 239         unsigned char dlc_ti_tick_1;
 240         unsigned char dlc_t1_tick_2;
 241         unsigned char dlc_t2_tick_2;
 242         unsigned char dlc_ti_tick_2;
 243         unsigned char product_id[18];
 244 };
 245 
 246 struct srb_open_response {
 247         unsigned char command;
 248         unsigned char reserved1;
 249         unsigned char ret_code;
 250         unsigned char reserved2[3];
 251         unsigned short error_code;
 252         unsigned short asb_addr;
 253         unsigned short srb_addr;
 254         unsigned short arb_addr;
 255         unsigned short ssb_addr;
 256 };
 257 
 258 /* DIR_OPEN_ADAPTER options */
 259 
 260 #define OPEN_PASS_BCON_MAC 0x0100
 261 #define NUM_RCV_BUF 16
 262 #define RCV_BUF_LEN 136
 263 #define DHB_LENGTH 2048
 264 #define NUM_DHB 2
 265 #define DLC_MAX_SAP 2
 266 #define DLC_MAX_STA 1
 267 
 268 #define DLC_OPEN_SAP 0x15
 269 
 270 struct dlc_open_sap {
 271         unsigned char command;
 272         unsigned char reserved1;
 273         unsigned char ret_code;
 274         unsigned char reserved2;
 275         unsigned short station_id;
 276         unsigned char timer_t1;
 277         unsigned char timer_t2;
 278         unsigned char timer_ti;
 279         unsigned char maxout;
 280         unsigned char maxin;
 281         unsigned char maxout_incr;
 282         unsigned char max_retry_count;
 283         unsigned char gsap_max_mem;
 284         unsigned short max_i_field;
 285         unsigned char sap_value;
 286         unsigned char sap_options;
 287         unsigned char station_count;
 288         unsigned char sap_gsap_mem;
 289         unsigned char gsap[0];
 290 };
 291 
 292 /* DLC_OPEN_SAP options */
 293 
 294 #define MAX_I_FIELD 0x0088
 295 #define SAP_OPEN_IND_SAP 0x04
 296 #define SAP_OPEN_PRIORITY 0x20
 297 #define SAP_OPEN_STATION_CNT 0x1
 298 
 299 #define XMIT_DIR_FRAME 0x0a
 300 #define XMIT_UI_FRAME  0x0d
 301 #define XMIT_XID_CMD   0x0e
 302 #define XMIT_TEST_CMD  0x11
 303 
 304 struct srb_xmit {
 305         unsigned char command;
 306         unsigned char cmd_corr;
 307         unsigned char ret_code;
 308         unsigned char reserved1;
 309         unsigned short station_id;
 310 };
 311 
 312 #define DIR_INTERRUPT 0x00
 313 struct srb_interrupt {
 314         unsigned char command;
 315         unsigned char cmd_corr;
 316         unsigned char ret_code;
 317 };
 318 
 319 #define DIR_READ_LOG 0x08
 320 struct srb_read_log {
 321         unsigned char command;
 322         unsigned char reserved1;
 323         unsigned char ret_code;
 324         unsigned char reserved2;
 325         unsigned char line_errors;
 326         unsigned char internal_errors;
 327         unsigned char burst_errors;
 328         unsigned char A_C_errors;
 329         unsigned char abort_delimiters;
 330         unsigned char reserved3;
 331         unsigned char lost_frames;
 332         unsigned char recv_congest_count;
 333         unsigned char frame_copied_errors;
 334         unsigned char frequency_errors;
 335         unsigned char token_errors;
 336 };
 337 
 338 struct asb_xmit_resp {
 339         unsigned char command;
 340         unsigned char cmd_corr;
 341         unsigned char ret_code;
 342         unsigned char reserved;
 343         unsigned short station_id;
 344         unsigned short frame_length;
 345         unsigned char hdr_length;
 346         unsigned        char rsap_value;
 347 };
 348 
 349 #define XMIT_DATA_REQ 0x82
 350 struct arb_xmit_req {
 351         unsigned char command;
 352         unsigned char cmd_corr;
 353         unsigned char reserved1[2];
 354         unsigned short station_id;
 355         unsigned short dhb_address;
 356 };
 357 
 358 #define REC_DATA 0x81
 359 struct arb_rec_req {
 360         unsigned char command;
 361         unsigned char reserved1[3];
 362         unsigned short station_id;
 363         unsigned short rec_buf_addr;
 364         unsigned char lan_hdr_len;
 365         unsigned char dlc_hdr_len;
 366         unsigned short frame_len;
 367         unsigned char msg_type;
 368 };
 369 
 370 #define DATA_LOST 0x20
 371 struct asb_rec {
 372         unsigned char command;
 373         unsigned char reserved1;
 374         unsigned char ret_code;
 375         unsigned char reserved2;
 376         unsigned short station_id;
 377         unsigned short rec_buf_addr;
 378 };
 379 
 380 struct rec_buf {
 381         unsigned char reserved1[2];
 382         unsigned short buf_ptr;
 383         unsigned char reserved2;
 384         unsigned short buf_len;
 385         unsigned char data[0];
 386 };
 387 
 388 #define DLC_STATUS          0x83
 389 struct arb_dlc_status {
 390         unsigned char command;
 391         unsigned char reserved1[3];
 392         unsigned short station_id;
 393         unsigned short status;
 394         unsigned char frmr_data[5];
 395         unsigned char access_prio;
 396         unsigned char rem_addr[TR_ALEN];
 397         unsigned        char rsap_value;
 398 };
 399 
 400 #define RING_STAT_CHANGE    0x84
 401 struct arb_ring_stat_change {
 402         unsigned char command;
 403         unsigned char reserved1[5];
 404         unsigned short ring_status;
 405 };
 406 
 407 #define DIR_CLOSE_ADAPTER   0x04
 408 struct srb_close_adapter {
 409         unsigned char command;
 410         unsigned char reserved1;
 411         unsigned char ret_code;
 412 };
 413 
 414 #define DIR_MOD_OPEN_PARAMS 0x01
 415 #define DIR_SET_GRP_ADDR    0x06
 416 #define DIR_SET_FUNC_ADDR   0x07
 417 #define DLC_CLOSE_SAP       0x16
 418 
 419 
 420 #define SIGNAL_LOSS  0x8000
 421 #define HARD_ERROR   0x4000
 422 #define XMIT_BEACON  0x1000
 423 #define LOBE_FAULT   0x0800
 424 #define AUTO_REMOVAL 0x0400
 425 #define REMOVE_RECV  0x0100
 426 #define LOG_OVERFLOW 0x0080
 427 #define RING_RECOVER 0x0020
 428 

/* */