drivers/scsi/aic7xxx.c

/* */
This source file includes following definitions.
debug
debug_config
debug_scb
aic7xxx_setup
aic7xxx_loadseq
aic7xxx_delay
rcs_version
aic7xxx_info
aic7xxx_length
aic7xxx_scsirate
aic7xxx_putscb
aic7xxx_putscb_dma
aic7xxx_getscb
aic7xxx_match_scb
aic7xxx_unbusy_target
aic7xxx_done
aic7xxx_add_waiting_scb
aic7xxx_abort_waiting_scb
aic7xxx_reset_device
aic7xxx_reset_current_bus
aic7xxx_reset_channel
aic7xxx_isr
aic7xxx_probe
read_2840_seeprom
read_seeprom
detect_maxscb
aic7xxx_register
aic7xxx_detect
aic7xxx_buildscb
aic7xxx_queue
aic7xxx_abort_scb
aic7xxx_abort_reset
aic7xxx_abort
aic7xxx_reset
aic7xxx_biosparam
   1 /*+M*************************************************************************
   2  * Adaptec 274x/284x/294x device driver for Linux.
   3  *
   4  * Copyright (c) 1994 John Aycock
   5  *   The University of Calgary Department of Computer Science.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; see the file COPYING.  If not, write to
  19  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F
  22  * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA
  23  * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide,
  24  * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux,
  25  * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file
  26  * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual,
  27  * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the
  28  * ANSI SCSI-2 specification (draft 10c), ...
  29  *
  30  * ----------------------------------------------------------------
  31  *  Modified to include support for wide and twin bus adapters,
  32  *  DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes,
  33  *  and other rework of the code.
  34  *
  35  *  Parts of this driver are based on the FreeBSD driver by Justin
  36  *  T. Gibbs.
  37  *
  38  *  A Boot time option was also added for not resetting the scsi bus.
  39  *
  40  *    Form:  aic7xxx=extended,no_reset
  41  *
  42  *    -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95
  43  *
  44  *  $Id: aic7xxx.c,v 2.15 1995/12/17 19:43:20 deang Exp $
  45  *-M*************************************************************************/
  46 
  47 #ifdef MODULE
  48 #include <linux/module.h>
  49 #endif
  50 
  51 #include <stdarg.h>
  52 #include <asm/io.h>
  53 #include <linux/string.h>
  54 #include <linux/errno.h>
  55 #include <linux/kernel.h>
  56 #include <linux/ioport.h>
  57 #include <linux/bios32.h>
  58 #include <linux/delay.h>
  59 #include <linux/sched.h>
  60 #include <linux/pci.h>
  61 #include <linux/proc_fs.h>
  62 #include <linux/blk.h>
  63 #include "sd.h"
  64 #include "scsi.h"
  65 #include "hosts.h"
  66 #include "aic7xxx.h"
  67 #include <linux/stat.h>
  68 
  69 #include <linux/config.h>       /* for CONFIG_PCI */
  70 
  71 struct proc_dir_entry proc_scsi_aic7xxx = {
  72     PROC_SCSI_AIC7XXX, 7, "aic7xxx",
  73     S_IFDIR | S_IRUGO | S_IXUGO, 2
  74 };
  75 
  76 #define AIC7XXX_C_VERSION  "$Revision: 2.15 $"
  77 
  78 #define NUMBER(arr)     (sizeof(arr) / sizeof(arr[0]))
  79 #define MIN(a,b)        ((a < b) ? a : b)
  80 #define ALL_TARGETS -1
  81 #ifndef TRUE
  82 #  define TRUE 1
  83 #endif
  84 #ifndef FALSE
  85 #  define FALSE 0
  86 #endif
  87 
  88 /*
  89  * Defines for PCI bus support, testing twin bus support, DMAing of
  90  * SCBs, tagged queueing, commands (SCBs) per lun, and SCSI bus reset
  91  * delay time.
  92  *
  93  *   o PCI bus support - this has been implemented and working since
  94  *     the December 1, 1994 release of this driver. If you don't have
  95  *     a PCI bus and do not wish to configure your kernel with PCI
  96  *     support, then make sure this define is set to the cprrect
  97  *     define for PCI support (CONFIG_PCI) and configure your kernel
  98  *     without PCI support (make config).
  99  *
 100  *   o Twin bus support - this has been tested and does work.
 101  *
 102  *   o DMAing of SCBs - thanks to Kai Makisara, this now works.
 103  *     This define is now taken out and DMAing of SCBs is always
 104  *     performed (8/12/95 - DE).
 105  *
 106  *   o Tagged queueing - this driver is capable of tagged queueing
 107  *     but I am unsure as to how well the higher level driver implements
 108  *     tagged queueing. Therefore, the maximum commands per lun is
 109  *     set to 2. If you want to implement tagged queueing, ensure
 110  *     this define is not commented out.
 111  *
 112  *   o Sharing IRQs - allowed for sharing of IRQs. This will allow
 113  *     for multiple aic7xxx host adapters sharing the same IRQ, but
 114  *     not for sharing IRQs with other devices. The higher level
 115  *     PCI code and interrupt handling needs to be modified to
 116  *     support this.
 117  *
 118  *   o Commands per lun - If tagged queueing is enabled, then you
 119  *     may want to try increasing AIC7XXX_CMDS_PER_LUN to more
 120  *     than 2.  By default, we limit the SCBs per lun to 2 with
 121  *     or without tagged queueing enabled.  If tagged queueing is
 122  *     disabled, the sequencer will keep the 2nd SCB in the input
 123  *     queue until the first one completes - so it is OK to to have
 124  *     more than 1 SCB queued.  If tagged queueing is enabled, then
 125  *     the sequencer will attempt to send the 2nd SCB to the device
 126  *     while the first SCB is executing and the device is disconnected.
 127  *     For adapters limited to 4 SCBs, you may want to actually
 128  *     decrease the commands per lun to 1, if you often have more
 129  *     than 2 devices active at the same time.  This will allocate
 130  *     1 SCB for each device and ensure that there will always be
 131  *     a free SCB for up to 4 devices active at the same time.
 132  *
 133  *  Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95
 134  */
 135 
 136 /* Uncomment this for testing twin bus support. */
 137 #define AIC7XXX_TWIN_SUPPORT
 138 
 139 /* Uncomment this for tagged queueing. */
 140 /* #define AIC7XXX_TAGGED_QUEUEING */
 141 
 142 /* Uncomment this for allowing sharing of IRQs. */
 143 #define AIC7XXX_SHARE_IRQS
 144 
 145 /*
 146  * You can try raising me if tagged queueing is enabled, or lowering
 147  * me if you only have 4 SCBs.
 148  */
 149 #define AIC7XXX_CMDS_PER_LUN 2
 150 
 151 /* Set this to the delay in seconds after SCSI bus reset. */
 152 #define AIC7XXX_RESET_DELAY 15
 153 
 154 /*
 155  * Uncomment the following define for collection of SCSI transfer statistics
 156  * for the /proc filesystem.
 157  *
 158  * NOTE: This does affect performance since it has to maintain statistics.
 159  */
 160 /* #define AIC7XXX_PROC_STATS */
 161 
 162 /*
 163  * For debugging the abort/reset code.
 164  */
 165 /* #define AIC7XXX_DEBUG_ABORT */
 166 
 167 /*
 168  * For general debug messages
 169  */
 170 #define AIC7XXX_DEBUG
 171 
 172 /*
 173  * Controller type and options
 174  */
 175 typedef enum {
 176   AIC_NONE,
 177   AIC_7770,     /* EISA aic7770 on motherboard */
 178   AIC_7771,     /* EISA aic7771 on 274x */
 179   AIC_284x,     /* VLB  aic7770 on 284x */
 180   AIC_7850,     /* PCI  aic7850 */
 181   AIC_7870,     /* PCI  aic7870 on motherboard */
 182   AIC_7871,     /* PCI  aic7871 on 294x */
 183   AIC_7872,     /* PCI  aic7872 on 3940 */
 184   AIC_7873,     /* PCI  aic7873 on 3985 */
 185   AIC_7874,     /* PCI  aic7874 on 294x Differential */
 186   AIC_7880,     /* PCI  aic7880 on motherboard */
 187   AIC_7881,     /* PCI  aic7881 on 294x Ultra */
 188   AIC_7882,     /* PCI  aic7882 on 3940 Ultra */
 189   AIC_7883,     /* PCI  aic7883 on 3985 Ultra */
 190   AIC_7884      /* PCI  aic7884 on 294x Ultra Differential */
 191 } aha_type;
 192 
 193 typedef enum {
 194   AIC_777x,     /* AIC-7770 based */
 195   AIC_785x,     /* AIC-7850 based */
 196   AIC_787x,     /* AIC-7870 based */
 197   AIC_788x      /* AIC-7880 based */
 198 } aha_chip_type;
 199 
 200 typedef enum {
 201   AIC_SINGLE,  /* Single Channel */
 202   AIC_TWIN,    /* Twin Channel */
 203   AIC_WIDE     /* Wide Channel */
 204 } aha_bus_type;
 205 
 206 typedef enum {
 207   AIC_UNKNOWN,
 208   AIC_ENABLED,
 209   AIC_DISABLED
 210 } aha_status_type;
 211 
 212 typedef enum {
 213   LIST_HEAD,
 214   LIST_SECOND,
 215   LIST_TAIL
 216 } insert_type;
 217 
 218 typedef enum {
 219   ABORT_RESET_INACTIVE,
 220   ABORT_RESET_PENDING,
 221   ABORT_RESET_SUCCESS
 222 } aha_abort_reset_type;
 223 
 224 /*
 225  * Define an array of board names that can be indexed by aha_type.
 226  * Don't forget to change this when changing the types!
 227  */
 228 static const char * board_names[] = {
 229   "<AIC-7xxx Unknown>",         /* AIC_NONE */
 230   "AIC-7770",                   /* AIC_7770 */
 231   "AHA-2740",                   /* AIC_7771 */
 232   "AHA-2840",                   /* AIC_284x */
 233   "AIC-7850",                   /* AIC_7850 */
 234   "AIC-7870",                   /* AIC_7870 */
 235   "AHA-2940",                   /* AIC_7871 */
 236   "AHA-3940",                   /* AIC_7872 */
 237   "AHA-3985",                   /* AIC_7873 */
 238   "AHA-2940 Differential",      /* AIC_7874 */
 239   "AIC-7880 Ultra",             /* AIC_7880 */
 240   "AHA-2940 Ultra",             /* AIC_7881 */
 241   "AHA-3940 Ultra",             /* AIC_7882 */
 242   "AHA-3985 Ultra",             /* AIC_7883 */
 243   "AHA-2940 Ultra Differential" /* AIC_7884 */
 244 };
 245 
 246 /*
 247  * There should be a specific return value for this in scsi.h, but
 248  * it seems that most drivers ignore it.
 249  */
 250 #define DID_UNDERFLOW   DID_ERROR
 251 
 252 /*
 253  *  What we want to do is have the higher level scsi driver requeue
 254  *  the command to us. There is no specific driver status for this
 255  *  condition, but the higher level scsi driver will requeue the
 256  *  command on a DID_BUS_BUSY error.
 257  */
 258 #define DID_RETRY_COMMAND DID_BUS_BUSY
 259 
 260 /*
 261  * EISA/VL-bus stuff
 262  */
 263 #define MINSLOT         1
 264 #define MAXSLOT         15
 265 #define SLOTBASE(x)     ((x) << 12)
 266 #define MAXIRQ          15
 267 
 268 /*
 269  * Standard EISA Host ID regs  (Offset from slot base)
 270  */
 271 #define HID0(x)         ((x) + 0xC80)   /* 0,1: msb of ID2, 2-7: ID1      */
 272 #define HID1(x)         ((x) + 0xC81)   /* 0-4: ID3, 5-7: LSB ID2         */
 273 #define HID2(x)         ((x) + 0xC82)   /* product                        */
 274 #define HID3(x)         ((x) + 0xC83)   /* firmware revision              */
 275 
 276 /*
 277  * AIC-7770 I/O range to reserve for a card
 278  */
 279 #define MINREG(x)       ((x) + 0xC00ul)
 280 #define MAXREG(x)       ((x) + 0xCBFul)
 281 
 282 /* -------------------- AIC-7770 offset definitions ----------------------- */
 283 
 284 /*
 285  * SCSI Sequence Control (p. 3-11).
 286  * Each bit, when set starts a specific SCSI sequence on the bus
 287  */
 288 #define SCSISEQ(x)              ((x) + 0xC00ul)
 289 #define         TEMODEO         0x80
 290 #define         ENSELO          0x40
 291 #define         ENSELI          0x20
 292 #define         ENRSELI         0x10
 293 #define         ENAUTOATNO      0x08
 294 #define         ENAUTOATNI      0x04
 295 #define         ENAUTOATNP      0x02
 296 #define         SCSIRSTO        0x01
 297 
 298 
 299 /*
 300  * SCSI Transfer Control 0 Register (pp. 3-13).
 301  * Controls the SCSI module data path.
 302  */
 303 #define SXFRCTL0(x)             ((x) + 0xC01ul)
 304 #define         DFON            0x80
 305 #define         DFPEXP          0x40
 306 #define         ULTRAEN         0x20
 307 #define         CLRSTCNT        0x10
 308 #define         SPIOEN          0x08
 309 #define         SCAMEN          0x04
 310 #define         CLRCHN          0x02
 311 /*  UNUSED                      0x01 */
 312 
 313 /*
 314  * SCSI Transfer Control 1 Register (pp. 3-14,15).
 315  * Controls the SCSI module data path.
 316  */
 317 #define SXFRCTL1(x)             ((x) + 0xC02ul)
 318 #define         BITBUCKET       0x80
 319 #define         SWRAPEN         0x40
 320 #define         ENSPCHK         0x20
 321 #define         STIMESEL        0x18
 322 #define         ENSTIMER        0x04
 323 #define         ACTNEGEN        0x02
 324 #define         STPWEN          0x01            /* Powered Termination */
 325 
 326 /*
 327  * SCSI Control Signal Read Register (p. 3-15).
 328  * Reads the actual state of the SCSI bus pins
 329  */
 330 #define SCSISIGI(x)             ((x) + 0xC03ul)
 331 #define         CDI             0x80
 332 #define         IOI             0x40
 333 #define         MSGI            0x20
 334 #define         ATNI            0x10
 335 #define         SELI            0x08
 336 #define         BSYI            0x04
 337 #define         REQI            0x02
 338 #define         ACKI            0x01
 339 
 340 /*
 341  * SCSI Contol Signal Write Register (p. 3-16).
 342  * Writing to this register modifies the control signals on the bus. Only
 343  * those signals that are allowed in the current mode (Initiator/Target) are
 344  * asserted.
 345  */
 346 #define SCSISIGO(x)             ((x) + 0xC03ul)
 347 #define         CDO             0x80
 348 #define         IOO             0x40
 349 #define         MSGO            0x20
 350 #define         ATNO            0x10
 351 #define         SELO            0x08
 352 #define         BSYO            0x04
 353 #define         REQO            0x02
 354 #define         ACKO            0x01
 355 
 356 /*
 357  * SCSI Rate
 358  */
 359 #define SCSIRATE(x)             ((x) + 0xC04ul)
 360 #define WIDEXFER                0x80            /* Wide transfer control */
 361 #define SXFR                    0x70            /* Sync transfer rate */
 362 #define SOFS                    0x0F            /* Sync offset */
 363 
 364 /*
 365  * SCSI ID (p. 3-18).
 366  * Contains the ID of the board and the current target on the
 367  * selected channel
 368  */
 369 #define SCSIID(x)               ((x) + 0xC05ul)
 370 #define         TID             0xF0            /* Target ID mask */
 371 #define         OID             0x0F            /* Our ID mask */
 372 
 373 /*
 374  * SCSI Transfer Count (pp. 3-19,20)
 375  * These registers count down the number of bytes transfered
 376  * across the SCSI bus.  The counter is decremented only once
 377  * the data has been safely transfered.  SDONE in SSTAT0 is
 378  * set when STCNT goes to 0
 379  */
 380 #define STCNT(x)                ((x) + 0xC08ul)
 381 
 382 /*
 383  * SCSI Status 0 (p. 3-21)
 384  * Contains one set of SCSI Interrupt codes
 385  * These are most likely of interest to the sequencer
 386  */
 387 #define SSTAT0(x)               ((x) + 0xC0Bul)
 388 #define         TARGET          0x80            /* Board is a target */
 389 #define         SELDO           0x40            /* Selection Done */
 390 #define         SELDI           0x20            /* Board has been selected */
 391 #define         SELINGO         0x10            /* Selection In Progress */
 392 #define         SWRAP           0x08            /* 24bit counter wrap */
 393 #define         SDONE           0x04            /* STCNT = 0x000000 */
 394 #define         SPIORDY         0x02            /* SCSI PIO Ready */
 395 #define         DMADONE         0x01            /* DMA transfer completed */
 396 
 397 /*
 398  * Clear SCSI Interrupt 1 (p. 3-23)
 399  * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 400  */
 401 #define CLRSINT1(x)             ((x) + 0xC0Cul)
 402 #define         CLRSELTIMEO     0x80
 403 #define         CLRATNO         0x40
 404 #define         CLRSCSIRSTI     0x20
 405 /*  UNUSED                      0x10 */
 406 #define         CLRBUSFREE      0x08
 407 #define         CLRSCSIPERR     0x04
 408 #define         CLRPHASECHG     0x02
 409 #define         CLRREQINIT      0x01
 410 
 411 /*
 412  * SCSI Status 1 (p. 3-24)
 413  * These interrupt bits are of interest to the kernel driver
 414  */
 415 #define SSTAT1(x)               ((x) + 0xC0Cul)
 416 #define         SELTO           0x80
 417 #define         ATNTARG         0x40
 418 #define         SCSIRSTI        0x20
 419 #define         PHASEMIS        0x10
 420 #define         BUSFREE         0x08
 421 #define         SCSIPERR        0x04
 422 #define         PHASECHG        0x02
 423 #define         REQINIT         0x01
 424 
 425 /*
 426  * SCSI Interrrupt Mode 1 (pp. 3-28,29).
 427  * Set bits in this register enable the corresponding
 428  * interrupt source.
 429  */
 430 #define SIMODE1(x)              ((x) + 0xC11ul)
 431 #define         ENSELTIMO       0x80
 432 #define         ENATNTARG       0x40
 433 #define         ENSCSIRST       0x20
 434 #define         ENPHASEMIS      0x10
 435 #define         ENBUSFREE       0x08
 436 #define         ENSCSIPERR      0x04
 437 #define         ENPHASECHG      0x02
 438 #define         ENREQINIT       0x01
 439 
 440 /*
 441  * SCSI/Host Address (p. 3-30)
 442  * These registers hold the host address for the byte about to be
 443  * transfered on the SCSI bus.  They are counted up in the same
 444  * manner as STCNT is counted down.  SHADDR should always be used
 445  * to determine the address of the last byte transfered since HADDR
 446  * can be squewed by write ahead.
 447  */
 448 #define SHADDR(x)               ((x) + 0xC14ul)
 449 
 450 /*
 451  * Selection/Reselection ID (p. 3-31)
 452  * Upper four bits are the device id. The ONEBIT is set when the re/selecting
 453  * device did not set its own ID.
 454  */
 455 #define SELID(x)                ((x) + 0xC19ul)
 456 #define         SELID_MASK      0xF0
 457 #define         ONEBIT          0x08
 458 /*  UNUSED                      0x07 */
 459 
 460 /*
 461  * SCSI Block Control (p. 3-32)
 462  * Controls Bus type and channel selection. In a twin channel configuration
 463  * addresses 0x00-0x1E are gated to the appropriate channel based on this
 464  * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
 465  * on a wide bus.
 466  */
 467 #define SBLKCTL(x)              ((x) + 0xC1Ful)
 468 /*  UNUSED                      0xC0 */
 469 #define         DIAGLEDEN       0x80
 470 #define         DIAGLEDON       0x40
 471 #define         AUTOFLUSHDIS    0x20            /* used for Rev C check */
 472 /*  UNUSED                      0x10 */
 473 #define         SELBUS_MASK     0x0F
 474 #define         SELBUSB         0x08
 475 /*  UNUSED                      0x04 */
 476 #define         SELWIDE         0x02
 477 /*  UNUSED                      0x01 */
 478 #define         SELSINGLE       0x00
 479 
 480 /*
 481  * Sequencer Control (p. 3-33)
 482  * Error detection mode and speed configuration
 483  */
 484 #define SEQCTL(x)               ((x) + 0xC60ul)
 485 #define         PERRORDIS       0x80
 486 #define         PAUSEDIS        0x40
 487 #define         FAILDIS         0x20
 488 #define         FASTMODE        0x10
 489 #define         BRKADRINTEN     0x08
 490 #define         STEP            0x04
 491 #define         SEQRESET        0x02
 492 #define         LOADRAM         0x01
 493 
 494 /*
 495  * Sequencer RAM Data (p. 3-34)
 496  * Single byte window into the Scratch Ram area starting at the address
 497  * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
 498  * four bytes in sucessesion. The SEQADDRs will increment after the most
 499  * significant byte is written
 500  */
 501 #define SEQRAM(x)               ((x) + 0xC61ul)
 502 
 503 /*
 504  * Sequencer Address Registers (p. 3-35)
 505  * Only the first bit of SEQADDR1 holds addressing information
 506  */
 507 #define SEQADDR0(x)             ((x) + 0xC62ul)
 508 #define SEQADDR1(x)             ((x) + 0xC63ul)
 509 
 510 #define ACCUM(x)                ((x) + 0xC64ul)         /* accumulator */
 511 #define SINDEX(x)               ((x) + 0xC65ul)
 512 
 513 /*
 514  * Board Control (p. 3-43)
 515  */
 516 #define BCTL(x)                 ((x) + 0xC84ul)
 517 /*   RSVD                       0xF0 */
 518 #define         ACE             0x08    /* Support for external processors */
 519 /*   RSVD                       0x06 */
 520 #define         ENABLE          0x01
 521 
 522 /*
 523  * Bus On/Off Time (p. 3-44)
 524  */
 525 #define BUSTIME(x)              ((x) + 0xC85ul)
 526 #define         BOFF            0xF0
 527 #define         BON             0x0F
 528 
 529 /*
 530  * Bus Speed (p. 3-45)
 531  */
 532 #define BUSSPD(x)               ((x) + 0xC86ul)
 533 #define         DFTHRSH         0xC0
 534 #define         STBOFF          0x38
 535 #define         STBON           0x07
 536 
 537 /*
 538  * Host Control (p. 3-47) R/W
 539  * Overal host control of the device.
 540  */
 541 #define HCNTRL(x)               ((x) + 0xC87ul)
 542 /*    UNUSED                    0x80 */
 543 #define         POWRDN          0x40
 544 /*    UNUSED                    0x20 */
 545 #define         SWINT           0x10
 546 #define         IRQMS           0x08
 547 #define         PAUSE           0x04
 548 #define         INTEN           0x02
 549 #define         CHIPRST         0x01
 550 #define         REQ_PAUSE       IRQMS | INTEN | PAUSE
 551 #define         UNPAUSE_274X    IRQMS | INTEN
 552 #define         UNPAUSE_284X    INTEN
 553 #define         UNPAUSE_294X    IRQMS | INTEN
 554 
 555 /*
 556  * Host Address (p. 3-48)
 557  * This register contains the address of the byte about
 558  * to be transfered across the host bus.
 559  */
 560 #define HADDR(x)                ((x) + 0xC88ul)
 561 
 562 /*
 563  * SCB Pointer (p. 3-49)
 564  * Gate one of the four SCBs into the SCBARRAY window.
 565  */
 566 #define SCBPTR(x)               ((x) + 0xC90ul)
 567 
 568 /*
 569  * Interrupt Status (p. 3-50)
 570  * Status for system interrupts
 571  */
 572 #define INTSTAT(x)              ((x) + 0xC91ul)
 573 #define         SEQINT_MASK     0xF0            /* SEQINT Status Codes */
 574 #define                 BAD_PHASE       0x00
 575 #define                 SEND_REJECT     0x10
 576 #define                 NO_IDENT        0x20
 577 #define                 NO_MATCH        0x30
 578 #define                 MSG_SDTR        0x40
 579 #define                 MSG_WDTR        0x50
 580 #define                 MSG_REJECT      0x60
 581 #define                 BAD_STATUS      0x70
 582 #define                 RESIDUAL        0x80
 583 #define                 ABORT_TAG       0x90
 584 #define                 AWAITING_MSG    0xA0
 585 #define                 IMMEDDONE       0xB0
 586 #define         BRKADRINT 0x08
 587 #define         SCSIINT   0x04
 588 #define         CMDCMPLT  0x02
 589 #define         SEQINT    0x01
 590 #define         INT_PEND  (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
 591 
 592 /*
 593  * Hard Error (p. 3-53)
 594  * Reporting of catastrophic errors. You usually cannot recover from
 595  * these without a full board reset.
 596  */
 597 #define ERROR(x)                ((x) + 0xC92ul)
 598 /*    UNUSED                    0xF0 */
 599 #define         PARERR          0x08
 600 #define         ILLOPCODE       0x04
 601 #define         ILLSADDR        0x02
 602 #define         ILLHADDR        0x01
 603 
 604 /*
 605  * Clear Interrupt Status (p. 3-52)
 606  */
 607 #define CLRINT(x)               ((x) + 0xC92ul)
 608 #define         CLRBRKADRINT    0x08
 609 #define         CLRSCSIINT      0x04
 610 #define         CLRCMDINT       0x02
 611 #define         CLRSEQINT       0x01
 612 
 613 /*
 614  * SCB Auto Increment (p. 3-59)
 615  * Byte offset into the SCB Array and an optional bit to allow auto
 616  * incrementing of the address during download and upload operations
 617  */
 618 #define SCBCNT(x)               ((x) + 0xC9Aul)
 619 #define         SCBAUTO         0x80
 620 #define         SCBCNT_MASK     0x1F
 621 
 622 /*
 623  * Queue In FIFO (p. 3-60)
 624  * Input queue for queued SCBs (commands that the seqencer has yet to start)
 625  */
 626 #define QINFIFO(x)              ((x) + 0xC9Bul)
 627 
 628 /*
 629  * Queue In Count (p. 3-60)
 630  * Number of queued SCBs
 631  */
 632 #define QINCNT(x)               ((x) + 0xC9Cul)
 633 
 634 /*
 635  * Queue Out FIFO (p. 3-61)
 636  * Queue of SCBs that have completed and await the host
 637  */
 638 #define QOUTFIFO(x)             ((x) + 0xC9Dul)
 639 
 640 /*
 641  * Queue Out Count (p. 3-61)
 642  * Number of queued SCBs in the Out FIFO
 643  */
 644 #define QOUTCNT(x)              ((x) + 0xC9Eul)
 645 
 646 #define SCBARRAY(x)             ((x) + 0xCA0ul)
 647 
 648 /* ---------------- END AIC-7770 Register Definitions ----------------- */
 649 
 650 /* --------------------- AHA-2840-only definitions -------------------- */
 651 
 652 #define SEECTL_2840(x)          ((x) + 0xCC0ul)
 653 /*    UNUSED                    0xF8 */
 654 #define         CS_2840         0x04
 655 #define         CK_2840         0x02
 656 #define         DO_2840         0x01
 657 
 658 #define STATUS_2840(x)          ((x) + 0xCC1ul)
 659 #define         EEPROM_TF       0x80
 660 #define         BIOS_SEL        0x60
 661 #define         ADSEL           0x1E
 662 #define         DI_2840         0x01
 663 
 664 /* --------------------- AIC-7870-only definitions -------------------- */
 665 
 666 #define DSPCISTATUS(x)          ((x) + 0xC86ul)
 667 #define         DFTHRESH        0xC0
 668 
 669 /*
 670  * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 671  * Controls the reading and writing of an external serial 1-bit
 672  * EEPROM Device.  In order to access the serial EEPROM, you must
 673  * first set the SEEMS bit that generates a request to the memory
 674  * port for access to the serial EEPROM device.  When the memory
 675  * port is not busy servicing another request, it reconfigures
 676  * to allow access to the serial EEPROM.  When this happens, SEERDY
 677  * gets set high to verify that the memory port access has been
 678  * granted.  See aic7xxx_read_eprom for detailed information on
 679  * the protocol necessary to read the serial EEPROM.
 680  */
 681 #define SEECTL(x)               ((x) + 0xC1Eul)
 682 #define         EXTARBACK       0x80
 683 #define         EXTARBREQ       0x40
 684 #define         SEEMS           0x20
 685 #define         SEERDY          0x10
 686 #define         SEECS           0x08
 687 #define         SEECK           0x04
 688 #define         SEEDO           0x02
 689 #define         SEEDI           0x01
 690 
 691 #define DEVREVID                0x08ul
 692 
 693 #define DEVSTATUS               0x40ul
 694 #define         MPORTMODE       0x04    /* aic7870 only */
 695 #define         RAMPSM          0x02    /* aic7870 only */
 696 #define         VOLSENSE        0x01
 697 
 698 #define DEVCONFIG               0x41ul
 699 #define         SCBRAMSEL       0x80
 700 #define         MRDCEN          0x40
 701 #define         EXTSCBTIME      0x20    /* aic7870 only */
 702 #define         EXTSCBPEN       0x10    /* aic7870 only */
 703 #define         BERREN          0x08
 704 #define         DACEN           0x04
 705 #define         STPWLEVEL       0x02
 706 #define         DIFACTNEGEN     0x01    /* aic7870 only */
 707 
 708 /* Scratch RAM offset definitions */
 709 
 710 /* ---------------------- Scratch RAM Offsets ------------------------- */
 711 /* These offsets are either to values that are initialized by the board's
 712  * BIOS or are specified by the Linux sequencer code. If I can figure out
 713  * how to read the EISA configuration info at probe time, the cards could
 714  * be run without BIOS support installed
 715  */
 716 
 717 /*
 718  * 1 byte per target starting at this address for configuration values
 719  */
 720 #define HA_TARG_SCRATCH(x)      ((x) + 0xC20ul)
 721 
 722 /*
 723  * The sequencer will stick the first byte of any rejected message here so
 724  * we can see what is getting thrown away.
 725  */
 726 #define HA_REJBYTE(x)           ((x) + 0xC31ul)
 727 
 728 /*
 729  * Bit vector of targets that have disconnection disabled.
 730  */
 731 #define HA_DISC_DSB(x)          ((x) + 0xC32ul)
 732 
 733 /*
 734  * Length of pending message
 735  */
 736 #define HA_MSG_LEN(x)           ((x) + 0xC34ul)
 737 
 738 /*
 739  * Outgoing Message Body
 740  */
 741 #define HA_MSG_START(x)         ((x) + 0xC35ul)
 742 
 743 /*
 744  * These are offsets into the card's scratch ram. Some of the values are
 745  * specified in the AHA2742 technical reference manual and are initialized
 746  * by the BIOS at boot time.
 747  */
 748 #define HA_ARG_1(x)             ((x) + 0xC4Aul) /* sdtr <-> rate parameters */
 749 #define HA_RETURN_1(x)          ((x) + 0xC4Aul)
 750 #define         SEND_SENSE      0x80
 751 #define         SEND_SDTR       0x80
 752 #define         SEND_WDTR       0x80
 753 #define         SEND_REJ        0x40
 754 
 755 #define SG_COUNT(x)             ((x) + 0xC4Dul)
 756 #define SG_NEXT(x)              ((x) + 0xC4Eul)
 757 #define HA_SIGSTATE(x)          ((x) + 0xC4Bul) /* value in SCSISIGO */
 758 #define HA_SCBCOUNT(x)          ((x) + 0xC52ul) /* number of hardware SCBs */
 759 
 760 #define HA_FLAGS(x)             ((x) + 0xC53ul) /* TWIN and WIDE bus flags */
 761 #define         SINGLE_BUS      0x00
 762 #define         TWIN_BUS        0x01
 763 #define         WIDE_BUS        0x02
 764 #define         ACTIVE_MSG      0x20
 765 #define         IDENTIFY_SEEN   0x40
 766 #define         RESELECTING     0x80
 767 
 768 #define HA_ACTIVE0(x)           ((x) + 0xC54ul) /* Active bits; targets 0-7 */
 769 #define HA_ACTIVE1(x)           ((x) + 0xC55ul) /* Active bits; targets 8-15 */
 770 #define SAVED_TCL(x)            ((x) + 0xC56ul) /* Saved target, channel, LUN */
 771 #define WAITING_SCBH(x)         ((x) + 0xC57ul) /* Head of disconnected targets list. */
 772 #define WAITING_SCBT(x)         ((x) + 0xC58ul) /* Tail of disconnected targets list. */
 773 
 774 #define HA_SCSICONF(x)          ((x) + 0xC5Aul) /* SCSI config register */
 775 #define HA_INTDEF(x)            ((x) + 0xC5Cul) /* interrupt def'n register */
 776 #define HA_HOSTCONF(x)          ((x) + 0xC5Dul) /* host config def'n register */
 777 
 778 #define HA_274_BIOSCTRL(x)      ((x) + 0xC5Ful) /* BIOS enabled for 274x */
 779 #define BIOSMODE                0x30
 780 #define BIOSDISABLED            0x30
 781 
 782 #define MSG_ABORT               0x06
 783 #define MSG_BUS_DEVICE_RESET    0x0C
 784 #define BUS_8_BIT               0x00
 785 #define BUS_16_BIT              0x01
 786 #define BUS_32_BIT              0x02
 787 
 788 
 789 /*
 790  *
 791  * Define the format of the SEEPROM registers (16 bits).
 792  *
 793  */
 794 struct seeprom_config {
 795 
 796 /*
 797  * SCSI ID Configuration Flags
 798  */
 799 #define CFXFER          0x0007          /* synchronous transfer rate */
 800 #define CFSYNCH         0x0008          /* enable synchronous transfer */
 801 #define CFDISC          0x0010          /* enable disconnection */
 802 #define CFWIDEB         0x0020          /* wide bus device (wide card) */
 803 /* UNUSED               0x00C0 */
 804 #define CFSTART         0x0100          /* send start unit SCSI command */
 805 #define CFINCBIOS       0x0200          /* include in BIOS scan */
 806 #define CFRNFOUND       0x0400          /* report even if not found */
 807 /* UNUSED               0xF800 */
 808   unsigned short device_flags[16];      /* words 0-15 */
 809 
 810 /*
 811  * BIOS Control Bits
 812  */
 813 #define CFSUPREM        0x0001          /* support all removeable drives */
 814 #define CFSUPREMB       0x0002          /* support removeable drives for boot only */
 815 #define CFBIOSEN        0x0004          /* BIOS enabled */
 816 /* UNUSED               0x0008 */
 817 #define CFSM2DRV        0x0010          /* support more than two drives */
 818 #define CF284XEXTEND    0x0020          /* extended translation (284x cards) */
 819 /* UNUSED               0x0040 */
 820 #define CFEXTEND        0x0080          /* extended translation enabled */
 821 /* UNUSED               0xFF00 */
 822   unsigned short bios_control;          /* word 16 */
 823 
 824 /*
 825  * Host Adapter Control Bits
 826  */
 827 /* UNUSED               0x0001 */
 828 #define CFULTRAEN       0x0002          /* Ultra SCSI speed enable (Ultra cards) */
 829 #define CF284XSELTO     0x0003          /* Selection timeout (284x cards) */
 830 #define CF284XFIFO      0x000C          /* FIFO Threshold (284x cards) */
 831 #define CFSTERM         0x0004          /* SCSI low byte termination (non-wide cards) */
 832 #define CFWSTERM        0x0008          /* SCSI high byte termination (wide card) */
 833 #define CFSPARITY       0x0010          /* SCSI parity */
 834 #define CF284XSTERM     0x0020          /* SCSI low byte termination (284x cards) */
 835 #define CFRESETB        0x0040          /* reset SCSI bus at IC initialization */
 836 /* UNUSED               0xFF80 */
 837   unsigned short adapter_control;       /* word 17 */
 838 
 839 /*
 840  * Bus Release, Host Adapter ID
 841  */
 842 #define CFSCSIID        0x000F          /* host adapter SCSI ID */
 843 /* UNUSED               0x00F0 */
 844 #define CFBRTIME        0xFF00          /* bus release time */
 845   unsigned short brtime_id;             /* word 18 */
 846 
 847 /*
 848  * Maximum targets
 849  */
 850 #define CFMAXTARG       0x00FF  /* maximum targets */
 851 /* UNUSED               0xFF00 */
 852   unsigned short max_targets;           /* word 19 */
 853 
 854   unsigned short res_1[11];             /* words 20-30 */
 855   unsigned short checksum;              /* word 31 */
 856 
 857 };
 858 
 859 /*
 860  * Pause the sequencer and wait for it to actually stop - this
 861  * is important since the sequencer can disable pausing for critical
 862  * sections.
 863  */
 864 #define PAUSE_SEQUENCER(p) \
 865   outb(p->pause, HCNTRL(p->base));                      \
 866   while ((inb(HCNTRL(p->base)) & PAUSE) == 0)           \
 867     ;                                                   \
 868 
 869 /*
 870  * Unpause the sequencer. Unremarkable, yet done often enough to
 871  * warrant an easy way to do it.
 872  */
 873 #define UNPAUSE_SEQUENCER(p) \
 874   outb(p->unpause, HCNTRL(p->base))
 875 
 876 /*
 877  * Restart the sequencer program from address zero
 878  */
 879 #define RESTART_SEQUENCER(p) \
 880   do {                                                  \
 881     outb(SEQRESET | FASTMODE, SEQCTL(p->base));         \
 882   } while (inb(SEQADDR0(p->base)) != 0 &&               \
 883            inb(SEQADDR1(p->base)) != 0);                \
 884   UNPAUSE_SEQUENCER(p);
 885 
 886 /*
 887  * If an error occurs during a data transfer phase, run the comand
 888  * to completion - it's easier that way - making a note of the error
 889  * condition in this location. This then will modify a DID_OK status
 890  * into an appropriate error for the higher-level SCSI code.
 891  */
 892 #define aic7xxx_error(cmd)      ((cmd)->SCp.Status)
 893 
 894 /*
 895  * Keep track of the targets returned status.
 896  */
 897 #define aic7xxx_status(cmd)     ((cmd)->SCp.sent_command)
 898 
 899 /*
 900  * The position of the SCSI commands scb within the scb array.
 901  */
 902 #define aic7xxx_position(cmd)   ((cmd)->SCp.have_data_in)
 903 
 904 /*
 905  * Since the sequencer code DMAs the scatter-gather structures
 906  * directly from memory, we use this macro to assert that the
 907  * kernel structure hasn't changed.
 908  */
 909 #define SG_STRUCT_CHECK(sg) \
 910   ((char *) &(sg).address - (char *) &(sg) != 0 ||  \
 911    (char *) &(sg).length  - (char *) &(sg) != 8 ||  \
 912    sizeof((sg).address) != 4 ||                   \
 913    sizeof((sg).length)  != 4 ||                   \
 914    sizeof(sg)           != 12)
 915 
 916 /*
 917  * "Static" structures. Note that these are NOT initialized
 918  * to zero inside the kernel - we have to initialize them all
 919  * explicitly.
 920  *
 921  * We support multiple adapter cards per interrupt, but keep a
 922  * linked list of Scsi_Host structures for each IRQ.  On an interrupt,
 923  * use the IRQ as an index into aic7xxx_boards[] to locate the card
 924  * information.
 925  */
 926 static struct Scsi_Host *aic7xxx_boards[MAXIRQ + 1];
 927 
 928 /*
 929  * When we detect and register the card, it is possible to
 930  * have the card raise a spurious interrupt.  Because we need
 931  * to support multiple cards, we cannot tell which card caused
 932  * the spurious interrupt.  And, we might not even have added
 933  * the card info to the linked list at the time the spurious
 934  * interrupt gets raised.  This variable is suppose to keep track
 935  * of when we are registering a card and how many spurious
 936  * interrupts we have encountered.
 937  *
 938  *   0 - do not allow spurious interrupts.
 939  *   1 - allow 1 spurious interrupt
 940  *   2 - have 1 spurious interrupt, do not allow any more.
 941  *
 942  * I've made it an integer instead of a boolean in case we
 943  * want to allow more than one spurious interrupt for debugging
 944  * purposes.  Otherwise, it could just go from true to false to
 945  * true (or something like that).
 946  *
 947  * When the driver detects the cards, we'll set the count to 1
 948  * for each card detection and registration.  After the registration
 949  * of a card completes, we'll set the count back to 0.  So far, it
 950  * seems to be enough to allow a spurious interrupt only during
 951  * card registration; if a spurious interrupt is going to occur,
 952  * this is where it happens.
 953  *
 954  * We should be able to find a way to avoid getting the spurious
 955  * interrupt.  But until we do, we have to keep this ugly code.
 956  */
 957 static int aic7xxx_spurious_count;
 958 
 959 /*
 960  * The driver keeps up to four scb structures per card in memory. Only the
 961  * first 26 bytes of the structure are valid for the hardware, the rest used
 962  * for driver level bookeeping.
 963  */
 964 #define SCB_DOWNLOAD_SIZE       26      /* amount to actually download */
 965 #define SCB_UPLOAD_SIZE         26      /* amount to actually upload */
 966 
 967 struct aic7xxx_scb {
 968 /* ------------    Begin hardware supported fields    ---------------- */
 969 /*1 */  unsigned char control;
 970 #define SCB_NEEDWDTR 0x80                       /* Initiate Wide Negotiation */
 971 #define SCB_DISCENB  0x40                       /* Disconnection Enable */
 972 #define SCB_TE       0x20                       /* Tag enable */
 973 #define SCB_NEEDSDTR 0x10                       /* Initiate Sync Negotiation */
 974 #define SCB_NEEDDMA  0x08                       /* Refresh SCB from host ram */
 975 #define SCB_DIS      0x04
 976 #define SCB_TAG_TYPE 0x03
 977 #define         SIMPLE_QUEUE    0x00
 978 #define         HEAD_QUEUE      0x01
 979 #define         OR_QUEUE        0x02
 980 /*              ILLEGAL      0x03 */
 981 /*2 */  unsigned char target_channel_lun;       /* 4/1/3 bits */
 982 /*3 */  unsigned char SG_segment_count;
 983 /*7 */  unsigned char SG_list_pointer[4] __attribute__ ((packed));
 984 /*11*/  unsigned char SCSI_cmd_pointer[4] __attribute__ ((packed));
 985 /*12*/  unsigned char SCSI_cmd_length;
 986 /*14*/  unsigned char RESERVED[2];              /* must be zero */
 987 /*15*/  unsigned char target_status;
 988 /*18*/  unsigned char residual_data_count[3];
 989 /*19*/  unsigned char residual_SG_segment_count;
 990 /*23*/  unsigned char data_pointer[4] __attribute__ ((packed));
 991 /*26*/  unsigned char data_count[3];
 992 /*30*/  unsigned char host_scb[4] __attribute__ ((packed));
 993 /*31*/  u_char next_waiting;            /* Used to thread SCBs awaiting selection. */
 994 #define SCB_LIST_NULL 0xFF              /* SCB list equivelent to NULL */
 995 #if 0
 996         /*
 997          *  No real point in transferring this to the
 998          *  SCB registers.
 999          */
1000         unsigned char RESERVED[1];
1001 #endif
1002 
1003         /*-----------------end of hardware supported fields----------------*/
1004         struct aic7xxx_scb *next;       /* next ptr when in free list */
1005         Scsi_Cmnd          *cmd;        /* Scsi_Cmnd for this scb */
1006 #define SCB_FREE               0x00
1007 #define SCB_ACTIVE             0x01
1008 #define SCB_ABORTED            0x02
1009 #define SCB_DEVICE_RESET       0x04
1010 #define SCB_IMMED              0x08
1011 #define SCB_SENSE              0x10
1012         int                 state;          /* current state of scb */
1013         unsigned int        position;       /* Position in scb array */
1014         struct scatterlist  sg;
1015         struct scatterlist  sense_sg;
1016         unsigned char       sense_cmd[6];   /* Allocate 6 characters for sense command */
1017 };
1018 
1019 typedef void (*timeout_fn)(unsigned long);
1020 
1021 static struct {
1022   unsigned char errno;
1023   const char *errmesg;
1024 } hard_error[] = {
1025   { ILLHADDR,  "Illegal Host Access" },
1026   { ILLSADDR,  "Illegal Sequencer Address referrenced" },
1027   { ILLOPCODE, "Illegal Opcode in sequencer program" },
1028   { PARERR,    "Sequencer Ram Parity Error" }
1029 };
1030 
1031 static unsigned char
1032 generic_sense[] = { REQUEST_SENSE, 0, 0, 0, 255, 0 };
1033 
1034 /*
1035  * The maximum number of SCBs we could have for ANY type
1036  * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE
1037  * SEQUENCER CODE IF THIS IS MODIFIED!
1038  */
1039 #define AIC7XXX_MAXSCB  255
1040 
1041 /*
1042  * Define a structure used for each host adapter, only one per IRQ.
1043  */
1044 struct aic7xxx_host {
1045   int                      base;             /* card base address */
1046   int                      maxscb;           /* hardware SCBs */
1047   int                      numscb;           /* current number of scbs */
1048   int                      extended;         /* extended xlate? */
1049   aha_type                 type;             /* card type */
1050   aha_chip_type            chip_type;        /* chip base type */
1051   int                      ultra_enabled;    /* Ultra SCSI speed enabled */
1052   int                      chan_num;         /* for 3940/3985, channel number */
1053   aha_bus_type             bus_type;         /* normal/twin/wide bus */
1054   unsigned char            a_scanned;        /* 0 not scanned, 1 scanned */
1055   unsigned char            b_scanned;        /* 0 not scanned, 1 scanned */
1056   unsigned int             isr_count;        /* Interrupt count */
1057   volatile unsigned char   unpause;          /* unpause value for HCNTRL */
1058   volatile unsigned char   pause;            /* pause value for HCNTRL */
1059   volatile unsigned short  needsdtr_copy;    /* default config */
1060   volatile unsigned short  needsdtr;
1061   volatile unsigned short  sdtr_pending;
1062   volatile unsigned short  needwdtr_copy;    /* default config */
1063   volatile unsigned short  needwdtr;
1064   volatile unsigned short  wdtr_pending;
1065   volatile unsigned short  discenable;       /* Targets allowed to disconnect */
1066   struct seeprom_config    seeprom;
1067   int                      have_seeprom;
1068   struct Scsi_Host        *next;             /* allow for multiple IRQs */
1069   struct aic7xxx_scb       scb_array[AIC7XXX_MAXSCB];  /* active commands */
1070   struct aic7xxx_scb      *free_scb;         /* list of free SCBs */
1071 #ifdef AIC7XXX_PROC_STATS
1072   /*
1073    * Statistics Kept:
1074    *
1075    * Total Xfers (count for each command that has a data xfer),
1076    * broken down further by reads && writes.
1077    *
1078    * Binned sizes, writes && reads:
1079    *    < 512, 512, 1-2K, 2-4K, 4-8K, 8-16K, 16-32K, 32-64K, 64K-128K, > 128K
1080    *
1081    * Total amounts read/written above 512 bytes (amts under ignored)
1082    */
1083   struct aic7xxx_xferstats {
1084     long xfers;                              /* total xfer count */
1085     long w_total;                            /* total writes */
1086     long w_total512;                         /* 512 byte blocks written */
1087     long w_bins[10];                         /* binned write */
1088     long r_total;                            /* total reads */
1089     long r_total512;                         /* 512 byte blocks read */
1090     long r_bins[10];                         /* binned reads */
1091   } stats[2][16][8];                         /* channel, target, lun */
1092 #endif /* AIC7XXX_PROC_STATS */
1093 };
1094 
1095 struct aic7xxx_host_config {
1096   int              irq;        /* IRQ number */
1097   int              base;       /* I/O base */
1098   int              maxscb;     /* hardware SCBs */
1099   int              unpause;    /* unpause value for HCNTRL */
1100   int              pause;      /* pause value for HCNTRL */
1101   int              scsi_id;    /* host SCSI ID */
1102   int              scsi_id_b;  /* host SCSI ID B channel for twin cards */
1103   int              extended;   /* extended xlate? */
1104   int              busrtime;   /* bus release time */
1105   int              walk_scbs;  /* external SCB RAM detected; walk the scb array */
1106   aha_type         type;       /* card type */
1107   aha_chip_type    chip_type;  /* chip base type */
1108   int              ultra_enabled;    /* Ultra SCSI speed enabled */
1109   int              chan_num;   /* for 3940/3985, channel number */
1110   aha_bus_type     bus_type;   /* normal/twin/wide bus */
1111   aha_status_type  parity;     /* bus parity enabled/disabled */
1112   aha_status_type  low_term;   /* bus termination low byte */
1113   aha_status_type  high_term;  /* bus termination high byte (wide cards only) */
1114 };
1115 
1116 /*
1117  * Valid SCSIRATE values. (p. 3-17)
1118  * Provides a mapping of tranfer periods in ns to the proper value to
1119  * stick in the scsiscfr reg to use that transfer rate.
1120  */
1121 static struct {
1122   short period;
1123   /* Rates in Ultra mode have bit 8 of sxfr set */
1124 #define         ULTRA_SXFR 0x100
1125   short rate;
1126   const char *english;
1127 } aic7xxx_syncrates[] = {
1128   {  50,  0x100,  "20.0" },
1129   {  62,  0x110,  "16.0" },
1130   {  75,  0x120,  "13.4" },
1131   { 100,  0x140,  "10.0" },
1132   { 100,  0x000,  "10.0" },
1133   { 125,  0x010,  "8.0"  },
1134   { 150,  0x020,  "6.67" },
1135   { 175,  0x030,  "5.7"  },
1136   { 200,  0x040,  "5.0"  },
1137   { 225,  0x050,  "4.4"  },
1138   { 250,  0x060,  "4.0"  },
1139   { 275,  0x070,  "3.6"  }
1140 };
1141 
1142 static int num_aic7xxx_syncrates =
1143     sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
1144 
1145 static int number_of_39xxs = 0;
1146 
1147 #ifdef AIC7XXX_DEBUG
1148 
1149 static void
1150 debug(const char *fmt, ...)
     /*  */
1151 {
1152   va_list ap;
1153   char buf[256];
1154 
1155   va_start(ap, fmt);
1156   vsprintf(buf, fmt, ap);
1157   printk(buf);
1158   va_end(ap);
1159 }
1160 
1161 static void
1162 debug_config(struct aic7xxx_host_config *p)
     /*  */
1163 {
1164   int host_conf, scsi_conf;
1165   unsigned char brelease;
1166   unsigned char dfthresh;
1167 
1168   static int DFT[] = { 0, 50, 75, 100 };
1169   static int SST[] = { 256, 128, 64, 32 };
1170   static const char *BUSW[] = { "", "-TWIN", "-WIDE" };
1171 
1172   host_conf = inb(HA_HOSTCONF(p->base));
1173   scsi_conf = inb(HA_SCSICONF(p->base));
1174 
1175   /*
1176    * The 7870 gets the bus release time and data FIFO threshold
1177    * from the serial EEPROM (stored in the config structure) and
1178    * scsi_conf register respectively.  The 7770 gets the bus
1179    * release time and data FIFO threshold from the scsi_conf and
1180    * host_conf registers respectively.
1181    */
1182   if (p->chip_type == AIC_777x)
1183   {
1184     dfthresh = (host_conf >> 6);
1185   }
1186   else
1187   {
1188     dfthresh = (scsi_conf >> 6);
1189   }
1190 
1191   brelease = p->busrtime;
1192   if (brelease == 0)
1193   {
1194     brelease = 2;
1195   }
1196 
1197   switch (p->type)
1198   {
1199     case AIC_7770:
1200     case AIC_7771:
1201       printk("%s%s AT EISA SLOT %d:\n", board_names[p->type], BUSW[p->bus_type],
1202              p->base >> 12);
1203       break;
1204 
1205     case AIC_284x:
1206       printk("%s%s AT VLB SLOT %d:\n", board_names[p->type], BUSW[p->bus_type],
1207              p->base >> 12);
1208       break;
1209 
1210     case AIC_7850:
1211     case AIC_7870:
1212     case AIC_7871:
1213     case AIC_7872:
1214     case AIC_7873:
1215     case AIC_7874:
1216     case AIC_7880:
1217     case AIC_7881:
1218     case AIC_7882:
1219     case AIC_7883:
1220     case AIC_7884:
1221       printk("%s%s (PCI-bus):\n", board_names[p->type], BUSW[p->bus_type]);
1222       break;
1223 
1224     default:
1225       panic("aic7xxx: (debug_config) internal error.\n");
1226   }
1227 
1228   printk("    irq %d\n"
1229          "    bus release time %d bclks\n"
1230          "    data fifo threshold %d%%\n",
1231          p->irq,
1232          brelease,
1233          DFT[dfthresh]);
1234 
1235   printk("    SCSI CHANNEL A:\n"
1236          "        scsi id %d\n"
1237          "        scsi selection timeout %d ms\n"
1238          "        scsi bus reset at power-on %sabled\n",
1239          scsi_conf & 0x07,
1240          SST[(scsi_conf >> 3) & 0x03],
1241          (scsi_conf & 0x40) ? "en" : "dis");
1242 
1243   if ((p->chip_type == AIC_777x) && (p->parity == AIC_UNKNOWN))
1244   {
1245     /*
1246      * Set the parity for 7770 based cards.
1247      */
1248     p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
1249   }
1250   if (p->parity != AIC_UNKNOWN)
1251   {
1252     printk("        scsi bus parity %sabled\n",
1253            (p->parity == AIC_ENABLED) ? "en" : "dis");
1254   }
1255 
1256   if ((p->type == AIC_7770) || (p->type == AIC_7771))
1257   {
1258     p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
1259   }
1260   if (p->low_term != AIC_UNKNOWN)
1261   {
1262     printk("        scsi bus termination (low byte) %sabled\n",
1263           (p->low_term == AIC_ENABLED) ? "en" : "dis");
1264   }
1265   if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1266   {
1267     printk("        scsi bus termination (high byte) %sabled\n",
1268           (p->high_term == AIC_ENABLED) ? "en" : "dis");
1269   }
1270 }
1271 
1272 #if 0
1273 static void
1274 debug_scb(struct aic7xxx_scb *scb)
     /*  */
1275 {
1276   printk("control 0x%x, tcl 0x%x, sg_count %d, sg_ptr 0x%x, cmdp 0x%x, cmdlen %d\n",
1277          scb->control, scb->target_channel_lun, scb->SG_segment_count,
1278          (scb->SG_list_pointer[3] << 24) | (scb->SG_list_pointer[2] << 16) |
1279          (scb->SG_list_pointer[1] << 8) | scb->SG_list_pointer[0],
1280          (scb->SCSI_cmd_pointer[3] << 24) | (scb->SCSI_cmd_pointer[2] << 16) |
1281          (scb->SCSI_cmd_pointer[1] << 8) | scb->SCSI_cmd_pointer[0],
1282          scb->SCSI_cmd_length);
1283   printk("reserved 0x%x, target status 0x%x, resid SG count %d, resid data count %d\n",
1284          (scb->RESERVED[1] << 8) | scb->RESERVED[0], scb->target_status,
1285          scb->residual_SG_segment_count, (scb->residual_data_count[2] << 16) |
1286          (scb->residual_data_count[1] << 8) | scb->residual_data_count[0]);
1287   printk("data ptr 0x%x, data count %d, host scb 0x%x, next waiting %d\n",
1288          (scb->data_pointer[3] << 24) | (scb->data_pointer[2] << 16) |
1289          (scb->data_pointer[1] << 8) | scb->data_pointer[0],
1290          (scb->data_count[2] << 16) | (scb->data_count[1] << 8) | scb->data_count[0],
1291          (unsigned int) scb->host_scb, scb->next_waiting);
1292   printk("next ptr 0x%lx, Scsi Cmnd 0x%lx, state 0x%x, position %d\n",
1293          (unsigned long) scb->next, (unsigned long) scb->cmd, scb->state,
1294          scb->position);
1295 }
1296 #endif
1297 
1298 #else
1299 #  define debug(fmt, args...)
1300 #  define debug_config(x)
1301 #  define debug_scb(x)
1302 #endif AIC7XXX_DEBUG
1303 
1304 /*
1305  * XXX - these options apply unilaterally to _all_ 274x/284x/294x
1306  *       cards in the system. This should be fixed, but then,
1307  *       does anyone really have more than one in a machine?
1308  */
1309 static unsigned int aic7xxx_extended = 0;    /* extended translation on? */
1310 static unsigned int aic7xxx_no_reset = 0;    /* no resetting of SCSI bus */
1311 
1312 /*+F*************************************************************************
1313  * Function:
1314  *   aic7xxx_setup
1315  *
1316  * Description:
1317  *   Handle Linux boot parameters. This routine allows for assigning a value
1318  *   to a parameter with a ':' between the parameter and the value.
1319  *   ie. aic7xxx=unpause:0x0A,extended
1320  *-F*************************************************************************/
1321 void
1322 aic7xxx_setup(char *s, int *dummy)
     /*  */
1323 {
1324   int   i, n;
1325   char *p;
1326 
1327   static struct {
1328     const char *name;
1329     unsigned int *flag;
1330   } options[] = {
1331     { "extended",    &aic7xxx_extended },
1332     { "no_reset",    &aic7xxx_no_reset },
1333     { NULL,          NULL }
1334   };
1335 
1336   for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1337   {
1338     for (i = 0; options[i].name; i++)
1339     {
1340       n = strlen(options[i].name);
1341       if (!strncmp(options[i].name, p, n))
1342       {
1343         if (p[n] == ':')
1344         {
1345           *(options[i].flag) = simple_strtoul(p + n + 1, NULL, 0);
1346         }
1347         else
1348         {
1349           *(options[i].flag) = !0;
1350         }
1351       }
1352     }
1353   }
1354 }
1355 
1356 /*+F*************************************************************************
1357  * Function:
1358  *   aic7xxx_loadseq
1359  *
1360  * Description:
1361  *   Load the sequencer code into the controller memory.
1362  *-F*************************************************************************/
1363 static void
1364 aic7xxx_loadseq(int base)
     /*  */
1365 {
1366   static unsigned char seqprog[] = {
1367     /*
1368      * Each sequencer instruction is 29 bits
1369      * long (fill in the excess with zeroes)
1370      * and has to be loaded from least -> most
1371      * significant byte, so this table has the
1372      * byte ordering reversed.
1373      */
1374 #   include "aic7xxx_seq.h"
1375   };
1376 
1377   /*
1378    * When the AIC-7770 is paused (as on chip reset), the
1379    * sequencer address can be altered and a sequencer
1380    * program can be loaded by writing it, byte by byte, to
1381    * the sequencer RAM port - the Adaptec documentation
1382    * recommends using REP OUTSB to do this, hence the inline
1383    * assembly. Since the address autoincrements as we load
1384    * the program, reset it back to zero afterward. Disable
1385    * sequencer RAM parity error detection while loading, and
1386    * make sure the LOADRAM bit is enabled for loading.
1387    */
1388   outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1389 
1390   asm volatile("cld\n\t"
1391                "rep\n\t"
1392                "outsb"
1393                : /* no output */
1394                :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1395                :"si", "cx", "dx");
1396 
1397   /*
1398    * WARNING!  This is a magic sequence!  After extensive
1399    * experimentation, it seems that you MUST turn off the
1400    * LOADRAM bit before you play with SEQADDR again, else
1401    * you will end up with parity errors being flagged on
1402    * your sequencer program. (You would also think that
1403    * turning off LOADRAM and setting SEQRESET to reset the
1404    * address to zero would work, but you need to do it twice
1405    * for it to take effect on the address. Timing problem?)
1406    */
1407   do {
1408     /*
1409      * Actually, reset it until
1410      * the address shows up as
1411      * zero just to be safe..
1412      */
1413     outb(SEQRESET | FASTMODE, SEQCTL(base));
1414   } while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1415 }
1416 
1417 /*+F*************************************************************************
1418  * Function:
1419  *   aic7xxx_delay
1420  *
1421  * Description:
1422  *   Delay for specified amount of time.
1423  *-F*************************************************************************/
1424 static void
1425 aic7xxx_delay(int seconds)
     /*  */
1426 {
1427   unsigned long i;
1428 
1429   i = jiffies + (seconds * HZ);  /* compute time to stop */
1430 
1431   while (jiffies < i)
1432   {
1433     ;  /* Do nothing! */
1434   }
1435 }
1436 
1437 /*+F*************************************************************************
1438  * Function:
1439  *   rcs_version
1440  *
1441  * Description:
1442  *   Return a string containing just the RCS version number from either
1443  *   an Id or Revison RCS clause.
1444  *-F*************************************************************************/
1445 const char *
1446 rcs_version(const char *version_info)
     /*  */
1447 {
1448   static char buf[10];
1449   char *bp, *ep;
1450 
1451   bp = NULL;
1452   strcpy(buf, "????");
1453   if (!strncmp(version_info, "$Id: ", 5))
1454   {
1455     if ((bp = strchr(version_info, ' ')) != NULL)
1456     {
1457       bp++;
1458       if ((bp = strchr(bp, ' ')) != NULL)
1459       {
1460         bp++;
1461       }
1462     }
1463   }
1464   else
1465   {
1466     if (!strncmp(version_info, "$Revision: ", 11))
1467     {
1468       if ((bp = strchr(version_info, ' ')) != NULL)
1469       {
1470         bp++;
1471       }
1472     }
1473   }
1474 
1475   if (bp != NULL)
1476   {
1477     if ((ep = strchr(bp, ' ')) != NULL)
1478     {
1479       register int len = ep - bp;
1480 
1481       strncpy(buf, bp, len);
1482       buf[len] = '\0';
1483     }
1484   }
1485 
1486   return buf;
1487 }
1488 
1489 /*+F*************************************************************************
1490  * Function:
1491  *   aic7xxx_info
1492  *
1493  * Description:
1494  *   Return a string describing the driver.
1495  *-F*************************************************************************/
1496 const char *
1497 aic7xxx_info(struct Scsi_Host *notused)
     /*  */
1498 {
1499   static char buffer[128];
1500 
1501   strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1502   strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1503   strcat(buffer, "/");
1504   strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1505   strcat(buffer, "/");
1506   strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1507 
1508   return buffer;
1509 }
1510 
1511 /*+F*************************************************************************
1512  * Function:
1513  *   aic7xxx_length
1514  *
1515  * Description:
1516  *   How much data should be transferred for this SCSI command? Stop
1517  *   at segment sg_last if it's a scatter-gather command so we can
1518  *   compute underflow easily.
1519  *-F*************************************************************************/
1520 static unsigned
1521 aic7xxx_length(Scsi_Cmnd *cmd, int sg_last)
     /*  */
1522 {
1523   int i, segments;
1524   unsigned length;
1525   struct scatterlist *sg;
1526 
1527   segments = cmd->use_sg - sg_last;
1528   sg = (struct scatterlist *) cmd->buffer;
1529 
1530   if (cmd->use_sg)
1531   {
1532     for (i = length = 0; (i < cmd->use_sg) && (i < segments); i++)
1533     {
1534       length += sg[i].length;
1535     }
1536   }
1537   else
1538   {
1539     length = cmd->request_bufflen;
1540   }
1541 
1542   return (length);
1543 }
1544 
1545 /*+F*************************************************************************
1546  * Function:
1547  *   aic7xxx_scsirate
1548  *
1549  * Description:
1550  *   Look up the valid period to SCSIRATE conversion in our table
1551  *-F*************************************************************************/
1552 static void
1553 aic7xxx_scsirate(struct aic7xxx_host *p, unsigned char *scsirate,
     /*  */
1554                  unsigned char period, unsigned char offset,
1555                  int target, char channel)
1556 {
1557   int i;
1558 
1559   for (i = 0; i < num_aic7xxx_syncrates; i++)
1560   {
1561     if ((aic7xxx_syncrates[i].period - period) >= 0)
1562     {
1563       /*
1564        * Watch out for Ultra speeds when ultra is not enabled and
1565        * vice-versa.
1566        */
1567       if (p->ultra_enabled)
1568       {
1569         if (!(aic7xxx_syncrates[i].rate & ULTRA_SXFR))
1570         {
1571           printk ("aic7xxx: Target %d, channel %c, requests %sMB/s transfers, "
1572                   "but adapter in Ultra mode can only sync at 10MB/s or "
1573                   "above.\n", target, channel, aic7xxx_syncrates[i].english);
1574           break;  /* Use asynchronous transfers. */
1575         }
1576       }
1577       else
1578       {
1579         /*
1580          * Check for an Ultra device trying to negotiate an Ultra rate
1581          * on an adapter with Ultra mode disabled.
1582          */
1583         if (aic7xxx_syncrates[i].rate & ULTRA_SXFR)
1584         {
1585           /*
1586            * This should only happen if the driver is the first to negotiate
1587            * and chooses a high rate.  We'll just move down the table until
1588            * we hit a non Ultra speed.
1589            */
1590            continue;
1591         }
1592       }
1593       *scsirate = (aic7xxx_syncrates[i].rate) | (offset & 0x0F);
1594       printk("aic7xxx: Target %d, channel %c, now synchronous at %sMB/s, "
1595              "offset(0x%x).\n",
1596              target, channel, aic7xxx_syncrates[i].english, offset);
1597       return;
1598     }
1599   }
1600 
1601   /*
1602    * Default to asynchronous transfer
1603    */
1604   *scsirate = 0;
1605   printk("aic7xxx: Target %d, channel %c, using asynchronous transfers.\n",
1606          target, channel);
1607 }
1608 
1609 /*+F*************************************************************************
1610  * Function:
1611  *   aic7xxx_putscb
1612  *
1613  * Description:
1614  *   Transfer a SCB to the controller.
1615  *-F*************************************************************************/
1616 static void
1617 aic7xxx_putscb(int base, struct aic7xxx_scb *scb)
     /*  */
1618 {
1619   /*
1620    * All we need to do, is to output the position
1621    * of the SCB in the SCBARRAY to the QINFIFO
1622    * of the host adapter.
1623    */
1624   outb(scb->position, QINFIFO(base));
1625 }
1626 
1627 /*+F*************************************************************************
1628  * Function:
1629  *   aic7xxx_putscb_dma
1630  *
1631  * Description:
1632  *   DMA a SCB to the controller.
1633  *-F*************************************************************************/
1634 static void
1635 aic7xxx_putscb_dma(int base, struct aic7xxx_scb *scb)
     /*  */
1636 {
1637   /*
1638    * By turning on the SCB auto increment, any reference
1639    * to the SCB I/O space postincrements the SCB address
1640    * we're looking at. So turn this on and dump the relevant
1641    * portion of the SCB to the card.
1642    */
1643   outb(SCBAUTO, SCBCNT(base));
1644 
1645   asm volatile("cld\n\t"
1646                "rep\n\t"
1647                "outsb"
1648                : /* no output */
1649                :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1650                :"si", "cx", "dx");
1651 
1652   outb(0, SCBCNT(base));
1653 }
1654 
1655 /*+F*************************************************************************
1656  * Function:
1657  *   aic7xxx_getscb
1658  *
1659  * Description:
1660  *   Get a SCB from the controller.
1661  *-F*************************************************************************/
1662 static void
1663 aic7xxx_getscb(int base, struct aic7xxx_scb *scb)
     /*  */
1664 {
1665   /*
1666    * This is almost identical to aic7xxx_putscb().
1667    */
1668   outb(SCBAUTO, SCBCNT(base));
1669 
1670   asm volatile("cld\n\t"
1671                "rep\n\t"
1672                "insb"
1673                : /* no output */
1674                :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1675                :"di", "cx", "dx");
1676 
1677   outb(0, SCBCNT(base));
1678 }
1679 
1680 /*+F*************************************************************************
1681  * Function:
1682  *   aic7xxx_match_scb
1683  *
1684  * Description:
1685  *   Checks to see if an scb matches the target/channel as specified.
1686  *   If target is ALL_TARGETS (-1), then we're looking for any device
1687  *   on the specified channel; this happens when a channel is going
1688  *   to be reset and all devices on that channel must be aborted.
1689  *-F*************************************************************************/
1690 static int
1691 aic7xxx_match_scb(struct aic7xxx_scb *scb, int target, char channel)
     /*  */
1692 {
1693   int targ = (scb->target_channel_lun >> 4) & 0x0F;
1694   char chan = (scb->target_channel_lun & SELBUSB) ? 'B' : 'A';
1695 
1696 #ifdef AIC7XXX_DEBUG_ABORT
1697   printk ("aic7xxx: (match_scb) comparing target/channel %d/%c to scb %d/%c\n",
1698           target, channel, targ, chan);
1699 #endif
1700   if (target == ALL_TARGETS)
1701   {
1702     return (chan == channel);
1703   }
1704   else
1705   {
1706     return ((chan == channel) && (targ == target));
1707   }
1708 }
1709 
1710 /*+F*************************************************************************
1711  * Function:
1712  *   aic7xxx_unbusy_target
1713  *
1714  * Description:
1715  *   Set the specified target inactive.
1716  *-F*************************************************************************/
1717 static void
1718 aic7xxx_unbusy_target(unsigned char target, char channel, int base)
     /*  */
1719 {
1720   unsigned char active;
1721   unsigned long active_port = HA_ACTIVE0(base);
1722 
1723 #ifdef AIC7XXX_DEBUG_ABORT
1724   printk ("aic7xxx: (unbusy_target) target/channel %d/%c\n",
1725           target, channel);
1726 #endif
1727   if ((target > 0x07) || (channel == 'B'))
1728   {
1729     /*
1730      * targets on the Second channel or above id 7 store info in byte two
1731      * of HA_ACTIVE
1732      */
1733     active_port++;
1734   }
1735   active = inb(active_port);
1736   active &= ~(0x01 << (target & 0x07));
1737   outb(active_port, active);
1738 }
1739 
1740 /*+F*************************************************************************
1741  * Function:
1742  *   aic7xxx_done
1743  *
1744  * Description:
1745  *   Calls the higher level scsi done function and frees the scb.
1746  *-F*************************************************************************/
1747 static void
1748 aic7xxx_done(struct aic7xxx_host *p, struct aic7xxx_scb *scb)
     /*  */
1749 {
1750   long flags;
1751   Scsi_Cmnd *cmd = scb->cmd;
1752 
1753 #ifdef 0
1754   printk ("aic7xxx: (done) target/channel %d/%d\n",
1755           cmd->target, cmd->channel);
1756 #endif
1757   /*
1758    * This is a critical section, since we don't want the
1759    * queue routine mucking with the host data.
1760    */
1761   save_flags(flags);
1762   cli();
1763 
1764   /*
1765    * Process the command after marking the scb as free
1766    * and adding it to the free list.
1767    */
1768   scb->state = SCB_FREE;
1769   scb->next = p->free_scb;
1770   p->free_scb = &(p->scb_array[scb->position]);
1771   scb->cmd = NULL;
1772 
1773   restore_flags(flags);
1774 
1775   cmd->scsi_done(cmd);
1776 }
1777 
1778 /*+F*************************************************************************
1779  * Function:
1780  *   aic7xxx_add_waiting_scb
1781  *
1782  * Description:
1783  *   Add this SCB to the "waiting for selection" list.
1784  *-F*************************************************************************/
1785 static void
1786 aic7xxx_add_waiting_scb(u_long              base,
     /*  */
1787                         struct aic7xxx_scb *scb,
1788                         insert_type         where)
1789 {
1790   unsigned char head, tail;
1791   unsigned char curscb;
1792 
1793   curscb = inb(SCBPTR(base));
1794   head = inb(WAITING_SCBH(base));
1795   tail = inb(WAITING_SCBT(base));
1796   if (head == SCB_LIST_NULL)
1797   {
1798     /*
1799      * List was empty
1800      */
1801     head = scb->position;
1802     tail = SCB_LIST_NULL;
1803   }
1804   else
1805   {
1806     if (where == LIST_HEAD)
1807     {
1808       outb(scb->position, SCBPTR(base));
1809       outb(head, SCBARRAY(base) + 30);
1810       head = scb->position;
1811     }
1812     else
1813     {
1814       if (tail == SCB_LIST_NULL)
1815       {
1816         /*
1817          * List had one element
1818          */
1819         tail = scb->position;
1820         outb(head, SCBPTR(base));
1821         outb(tail, SCBARRAY(base) + 30);
1822       }
1823       else
1824       {
1825         if (where == LIST_SECOND)
1826         {
1827           unsigned char third_scb;
1828 
1829           outb(head, SCBPTR(base));
1830           third_scb = inb(SCBARRAY(base) + 30);
1831           outb(scb->position, SCBARRAY(base) + 30);
1832           outb(scb->position, SCBPTR(base));
1833           outb(third_scb, SCBARRAY(base) + 30);
1834         }
1835         else
1836         {
1837           outb(tail, SCBPTR(base));
1838           tail = scb->position;
1839           outb(tail, SCBARRAY(base) + 30);
1840         }
1841       }
1842     }
1843   }
1844   outb(head, WAITING_SCBH(base));
1845   outb(tail, WAITING_SCBT(base));
1846   outb(curscb, SCBPTR(base));
1847 }
1848 
1849 /*+F*************************************************************************
1850  * Function:
1851  *   aic7xxx_abort_waiting_scb
1852  *
1853  * Description:
1854  *   Manipulate the waiting for selection list and return the
1855  *   scb that follows the one that we remove.
1856  *-F*************************************************************************/
1857 static unsigned char
1858 aic7xxx_abort_waiting_scb(struct aic7xxx_host *p, struct aic7xxx_scb *scb,
     /*  */
1859                           unsigned char prev, unsigned char timedout_scb)
1860 {
1861   unsigned char curscb, next;
1862   int target = (scb->target_channel_lun >> 4) & 0x0F;
1863   char channel = (scb->target_channel_lun & SELBUSB) ? 'B' : 'A';
1864   int base = p->base;
1865 
1866   /*
1867    * Select the SCB we want to abort and
1868    * pull the next pointer out of it.
1869    */
1870   curscb = inb(SCBPTR(base));
1871   outb(scb->position, SCBPTR(base));
1872   next = inb(SCBARRAY(base) + 30);
1873 
1874   /*
1875    * Clear the necessary fields
1876    */
1877   outb(SCB_NEEDDMA, SCBARRAY(base));
1878   outb(SCB_LIST_NULL, SCBARRAY(base) + 30);
1879   aic7xxx_unbusy_target(target, channel, base);
1880 
1881   /*
1882    * Update the waiting list
1883    */
1884   if (prev == SCB_LIST_NULL)
1885   {
1886     /*
1887      * First in the list
1888      */
1889     outb(next, WAITING_SCBH(base));
1890   }
1891   else
1892   {
1893     /*
1894      * Select the scb that pointed to us and update its next pointer.
1895      */
1896     outb(prev, SCBPTR(base));
1897     outb(next, SCBARRAY(base) + 30);
1898   }
1899   /*
1900    * Update the tale pointer
1901    */
1902   if (inb(WAITING_SCBT(base)) == scb->position)
1903   {
1904     outb(prev, WAITING_SCBT(base));
1905   }
1906 
1907   /*
1908    * Point us back at the original scb position
1909    * and inform the SCSI system that the command
1910    * has been aborted.
1911    */
1912   outb(curscb, SCBPTR(base));
1913   scb->state |= SCB_ABORTED;
1914   scb->cmd->result = (DID_RESET << 16);
1915   aic7xxx_done(p, scb);
1916 
1917 #ifdef AIC7XXX_DEBUG_ABORT
1918   printk ("aic7xxx: (abort_waiting_scb) target/channel %d/%c, prev %d, "
1919           "to_scb %d, next %d\n", target, channel, prev, timedout_scb, next);
1920 #endif
1921   return (next);
1922 }
1923 
1924 /*+F*************************************************************************
1925  * Function:
1926  *   aic7xxx_reset_device
1927  *
1928  * Description:
1929  *   The device at the given target/channel has been reset.  Abort
1930  *   all active and queued scbs for that target/channel.
1931  *-F*************************************************************************/
1932 static int
1933 aic7xxx_reset_device(struct aic7xxx_host *p, int target, char channel,
     /*  */
1934                      unsigned char timedout_scb)
1935 {
1936   int base = p->base;
1937   struct aic7xxx_scb *scb;
1938   unsigned char active_scb;
1939   int i = 0;
1940   int found = 0;
1941 
1942   /*
1943    * Restore this when we're done
1944    */
1945   active_scb = inb(SCBPTR(base));
1946 
1947 #ifdef AIC7XXX_DEBUG_ABORT
1948   printk ("aic7xxx: (reset_device) target/channel %d/%c, to_scb %d, "
1949           "active_scb %d\n", target, channel, timedout_scb, active_scb);
1950 #endif
1951   /*
1952    * Search the QINFIFO.
1953    */
1954   {
1955     int saved_queue[AIC7XXX_MAXSCB];
1956     int queued = inb(QINCNT(base));
1957 
1958     for (i = 0; i < (queued - found); i++)
1959     {
1960       saved_queue[i] = inb(QINFIFO(base));
1961       scb = &(p->scb_array[saved_queue[i]]);
1962       if (aic7xxx_match_scb(scb, target, channel))
1963       {
1964         /*
1965          * We found an scb that needs to be aborted.
1966          */
1967         scb->state |= SCB_ABORTED;
1968         scb->cmd->result = (DID_RESET << 16);
1969         aic7xxx_done(p, scb);
1970         outb(scb->position, SCBPTR(base));
1971         outb(SCB_NEEDDMA, SCBARRAY(base));
1972         i--;
1973         found++;
1974       }
1975     }
1976     /*
1977      * Now put the saved scbs back.
1978      */
1979     for (queued = 0; queued < i; queued++)
1980     {
1981       outb(saved_queue[queued], QINFIFO(base));
1982     }
1983   }
1984 
1985   /*
1986    * Search waiting for selection list.
1987    */
1988   {
1989     unsigned char next, prev;
1990 
1991     next = inb(WAITING_SCBH(base));  /* Start at head of list. */
1992     prev = SCB_LIST_NULL;
1993 
1994     while (next != SCB_LIST_NULL)
1995     {
1996       scb = &(p->scb_array[next]);
1997       /*
1998        * Select the SCB.
1999        */
2000       if (aic7xxx_match_scb(scb, target, channel))
2001       {
2002         next = aic7xxx_abort_waiting_scb(p, scb, prev, timedout_scb);
2003         found++;
2004       }
2005       else
2006       {
2007         outb(scb->position, SCBPTR(base));
2008         prev = next;
2009         next = inb(SCBARRAY(base) + 30);
2010       }
2011     }
2012   }
2013 
2014   /*
2015    * Go through the entire SCB array now and look for
2016    * commands for this target that are active.  These
2017    * are other (most likely tagged) commands that
2018    * were disconnected when the reset occured.
2019    */
2020   for (i = 0; i < p->numscb; i++)
2021   {
2022     scb = &(p->scb_array[i]);
2023     if ((scb->state & SCB_ACTIVE) && aic7xxx_match_scb(scb, target, channel))
2024     {
2025       /*
2026        * Ensure the target is "free"
2027        */
2028       aic7xxx_unbusy_target(target, channel, base);
2029       outb(scb->position, SCBPTR(base));
2030       outb(SCB_NEEDDMA, SCBARRAY(base));
2031       scb->state |= SCB_ABORTED;
2032       scb->cmd->result = (DID_RESET << 16);
2033       aic7xxx_done(p, scb);
2034       found++;
2035     }
2036   }
2037 
2038   outb(active_scb, SCBPTR(base));
2039   return (found);
2040 }
2041 
2042 /*+F*************************************************************************
2043  * Function:
2044  *   aic7xxx_reset_current_bus
2045  *
2046  * Description:
2047  *   Reset the current SCSI bus.
2048  *-F*************************************************************************/
2049 static void
2050 aic7xxx_reset_current_bus(int base)
     /*  */
2051 {
2052 #ifdef AIC7XXX_DEBUG_ABORT
2053     printk ("aic7xxx: (reset_current_bus)\n");
2054 #endif
2055   outb(SCSIRSTO, SCSISEQ(base));
2056   udelay(1000);
2057   outb(0, SCSISEQ(base));
2058 }
2059 
2060 /*+F*************************************************************************
2061  * Function:
2062  *   aic7xxx_reset_channel
2063  *
2064  * Description:
2065  *   Reset the channel.
2066  *-F*************************************************************************/
2067 static int
2068 aic7xxx_reset_channel(struct aic7xxx_host *p, char channel,
     /*  */
2069                      unsigned char timedout_scb)
2070 {
2071   int base = p->base;
2072   unsigned char sblkctl;
2073   char cur_channel;
2074   unsigned long offset, offset_max;
2075   int found;
2076 
2077 #ifdef AIC7XXX_DEBUG_ABORT
2078   printk ("aic7xxx: (reset_channel) channel %c, to_scb %d\n",
2079           channel, timedout_scb);
2080 #endif
2081   /*
2082    * Clean up all the state information for the
2083    * pending transactions on this bus.
2084    */
2085   found = aic7xxx_reset_device(p, ALL_TARGETS, channel, timedout_scb);
2086 
2087   if (channel == 'B')
2088   {
2089     p->needsdtr |= (p->needsdtr_copy & 0xFF00);
2090     p->sdtr_pending &= 0x00FF;
2091     outb(0, HA_ACTIVE1(base));
2092     offset = HA_TARG_SCRATCH(base) + 8;
2093     offset_max = HA_TARG_SCRATCH(base) + 16;
2094   }
2095   else
2096   {
2097     if (p->bus_type == AIC_WIDE)
2098     {
2099       p->needsdtr = p->needsdtr_copy;
2100       p->needwdtr = p->needwdtr_copy;
2101       p->sdtr_pending = 0;
2102       p->wdtr_pending = 0;
2103       outb(0, HA_ACTIVE0(base));
2104       outb(0, HA_ACTIVE1(base));
2105       offset = HA_TARG_SCRATCH(base);
2106       offset_max = HA_TARG_SCRATCH(base) + 16;
2107     }
2108     else
2109     {
2110       p->needsdtr |= (p->needsdtr_copy & 0x00FF);
2111       p->sdtr_pending &= 0xFF00;
2112       outb(0, HA_ACTIVE0(base));
2113       offset = HA_TARG_SCRATCH(base);
2114       offset_max = HA_TARG_SCRATCH(base) + 8;
2115     }
2116   }
2117   while (offset < offset_max)
2118   {
2119     /*
2120      * Revert to async/narrow transfers
2121      * until we renegotiate.
2122      */
2123     u_char targ_scratch;
2124     targ_scratch = inb(offset);
2125     targ_scratch &= SXFR;
2126     outb(targ_scratch, offset);
2127     offset++;
2128   }
2129 
2130   /*
2131    * Reset the bus and unpause/restart the controller
2132    */
2133 
2134   /*
2135    * Case 1: Command for another bus is active
2136    */
2137   sblkctl = inb(SBLKCTL(base));
2138   cur_channel = (sblkctl & SELBUSB) ? 'B' : 'A';
2139   if (cur_channel != channel)
2140   {
2141 #ifdef AIC7XXX_DEBUG_ABORT
2142     printk ("aic7xxx: (reset_channel) Stealthily resetting channel %c\n",
2143             channel);
2144 #endif
2145     /*
2146      * Stealthily reset the other bus without upsetting the current bus
2147      */
2148     outb(sblkctl ^ SELBUSB, SBLKCTL(base));
2149     aic7xxx_reset_current_bus(base);
2150     outb(sblkctl, SBLKCTL(base));
2151 
2152     UNPAUSE_SEQUENCER(p);
2153   }
2154   /*
2155    * Case 2: A command from this bus is active or we're idle
2156    */
2157   else
2158   {
2159 #ifdef AIC7XXX_DEBUG_ABORT
2160     printk ("aic7xxx: (reset_channel) Resetting current channel %c\n",
2161             channel);
2162 #endif
2163     aic7xxx_reset_current_bus(base);
2164     RESTART_SEQUENCER(p);
2165   }
2166 
2167   return found;
2168 }
2169 
2170 /*+F*************************************************************************
2171  * Function:
2172  *   aic7xxx_isr
2173  *
2174  * Description:
2175  *   SCSI controller interrupt handler.
2176  *
2177  *   NOTE: Since we declared this using SA_INTERRUPT, interrupts should
2178  *         be disabled all through this function unless we say otherwise.
2179  *-F*************************************************************************/
2180 static void
2181 aic7xxx_isr(int irq, struct pt_regs * regs)
     /*  */
2182 {
2183   int base, intstat;
2184   struct aic7xxx_host *p;
2185   struct aic7xxx_scb *scb;
2186   unsigned char ha_flags, transfer;
2187   unsigned char scsi_id, bus_width;
2188   unsigned char offset, rate, scratch, scratch_offset;
2189   unsigned char max_offset, rej_byte;
2190   unsigned short target_mask, active;
2191   char channel;
2192   void *addr;
2193   int actual;
2194   int scb_index;
2195   Scsi_Cmnd *cmd;
2196 
2197   p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
2198 
2199   /*
2200    * Search for the host with a pending interrupt.  If we can't find
2201    * one, then we've encountered a spurious interrupt.
2202    */
2203   while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
2204   {
2205     if (p->next == NULL)
2206     {
2207       p = NULL;
2208     }
2209     else
2210     {
2211       p = (struct aic7xxx_host *) p->next->hostdata;
2212     }
2213   }
2214 
2215   if (p == NULL)
2216   {
2217     if (aic7xxx_spurious_count == 1)
2218     {
2219       aic7xxx_spurious_count = 2;
2220       printk("aic7xxx: (aic7xxx_isr) Encountered spurious interrupt.\n");
2221       return;
2222     }
2223     else
2224     {
2225       /*
2226        * The best we can do is to set p back to head of list and process
2227        * the erroneous interrupt - most likely a BRKADRINT.
2228        */
2229       p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
2230     }
2231   }
2232 
2233   /*
2234    * Keep track of interrupts for /proc/scsi
2235    */
2236   p->isr_count++;
2237 
2238   if ((p->a_scanned == 0) && (p->isr_count == 1))
2239   {
2240     /*
2241      * We must only have one card at this IRQ and it must have been
2242      * added to the board data before the spurious interrupt occurred.
2243      * It is sufficient that we check isr_count and not the spurious
2244      * interrupt count.
2245      */
2246     printk("aic7xxx: (aic7xxx_isr) Encountered spurious interrupt.\n");
2247     return;
2248   }
2249 
2250   base = p->base;
2251   /*
2252    * Handle all the interrupt sources - especially for SCSI
2253    * interrupts, we won't get a second chance at them.
2254    */
2255   intstat = inb(INTSTAT(base));
2256 
2257   if (intstat & BRKADRINT)
2258   {
2259     int i;
2260     unsigned char errno = inb(ERROR(base));
2261 
2262     printk("aic7xxx: (aic7xxx_isr) BRKADRINT error(0x%x):\n", errno);
2263     for (i = 0; i < NUMBER(hard_error); i++)
2264     {
2265       if (errno & hard_error[i].errno)
2266       {
2267         printk("  %s\n", hard_error[i].errmesg);
2268       }
2269     }
2270 
2271     panic("aic7xxx: (aic7xxx_isr) BRKADRINT, error(0x%x) seqaddr(0x%x).\n",
2272           inb(ERROR(base)), (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
2273   }
2274 
2275   if (intstat & SEQINT)
2276   {
2277     /*
2278      * Although the sequencer is paused immediately on
2279      * a SEQINT, an interrupt for a SCSIINT condition will
2280      * unpaused the sequencer before this point.
2281      */
2282     PAUSE_SEQUENCER(p);
2283 
2284     scsi_id = (inb(SCSIID(base)) >> 4) & 0x0F;
2285     scratch_offset = scsi_id;
2286     channel = 'A';
2287     if (inb(SBLKCTL(base)) & SELBUSB)
2288     {
2289       channel = 'B';
2290       scratch_offset += 8;
2291     }
2292     target_mask = (0x01 << scratch_offset);
2293 
2294     switch (intstat & SEQINT_MASK)
2295     {
2296       case BAD_PHASE:
2297         panic("aic7xxx: (aic7xxx_isr) Unknown scsi bus phase.\n");
2298         break;
2299 
2300       case SEND_REJECT:
2301         rej_byte = inb(HA_REJBYTE(base));
2302         if (rej_byte != 0x20)
2303         {
2304           debug("aic7xxx: Warning - Issuing message reject, 1st byte(0x%x)\n",
2305                 rej_byte);
2306         }
2307         else
2308         {
2309           scb_index = inb(SCBPTR(base));
2310           scb = &(p->scb_array[scb_index]);
2311           printk("aic7xxx: Warning - Tagged message rejected for target %d,"
2312                  " channel %c.\n", scsi_id, channel);
2313           scb->cmd->device->tagged_supported = 0;
2314           scb->cmd->device->tagged_queue = 0;
2315         }
2316         break;
2317 
2318       case NO_IDENT:
2319         panic("aic7xxx: Target %d, channel %c, did not send an IDENTIFY "
2320               "message. SAVED_TCL(0x%x).\n",
2321               scsi_id, channel, inb(SAVED_TCL(base)));
2322         break;
2323 
2324       case NO_MATCH:
2325         printk("aic7xxx: No active SCB for reconnecting target %d, "
2326               "channel %c - Issuing ABORT. SAVED_TCL(0x%x).\n",
2327               scsi_id, channel, inb(SAVED_TCL(base)));
2328         aic7xxx_unbusy_target(scsi_id, channel, base);
2329         outb(SCB_NEEDDMA, SCBARRAY(base));
2330 
2331         outb(CLRSELTIMEO, CLRSINT1(base));
2332         RESTART_SEQUENCER(p);
2333         break;
2334 
2335       case MSG_SDTR:
2336         /*
2337          * Help the sequencer to translate the negotiated
2338          * transfer rate. Transfer is 1/4 the period
2339          * in ns as is returned by the sync negotiation
2340          * message. So, we must multiply by four.
2341          */
2342         transfer = (inb(HA_ARG_1(base)) << 2);
2343         offset = inb(ACCUM(base));
2344         scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2345         /*
2346          * The maximum offset for a wide device is 0x08; for a
2347          * 8-bit bus device the maximum offset is 0x0F.
2348          */
2349         if (scratch & WIDEXFER)
2350         {
2351           max_offset = 0x08;
2352         }
2353         else
2354         {
2355           max_offset = 0x0F;
2356         }
2357         aic7xxx_scsirate(p, &rate, transfer, MIN(offset, max_offset), scsi_id, channel);
2358         /*
2359          * Preserve the wide transfer flag.
2360          */
2361         scratch = rate | (scratch & WIDEXFER);
2362         outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2363         outb(scratch, SCSIRATE(base));
2364         if ((scratch & 0x0F) == 0)
2365         { /*
2366            * The requested rate was so low that asynchronous transfers
2367            * are faster (not to mention the controller won't support
2368            * them), so we issue a reject to ensure we go to asynchronous
2369            * transfers.
2370            */
2371            outb(SEND_REJ, HA_RETURN_1(base));
2372         }
2373         else
2374         {
2375           /*
2376            * See if we initiated Sync Negotiation
2377            */
2378           if (p->sdtr_pending & target_mask)
2379           {
2380             /*
2381              * Don't send an SDTR back to the target.
2382              */
2383             outb(0, HA_RETURN_1(base));
2384           }
2385           else
2386           {
2387             /*
2388              * Send our own SDTR in reply.
2389              */
2390             printk("aic7xxx: Sending SDTR!!\n");
2391             outb(SEND_SDTR, HA_RETURN_1(base));
2392           }
2393         }
2394         /*
2395          * Clear the flags.
2396          */
2397         p->needsdtr &= ~target_mask;
2398         p->sdtr_pending &= ~target_mask;
2399 #if 0
2400   scb_index = inb(SCBPTR(base));
2401   scb = &(p->scb_array[scb_index]);
2402   debug_scb(scb);
2403 #endif
2404 
2405         break;
2406 
2407       case MSG_WDTR:
2408       {
2409         bus_width = inb(ACCUM(base));
2410         printk("aic7xxx: Received MSG_WDTR, Target %d, channel %c "
2411                "needwdtr(0x%x).\n", scsi_id, channel, p->needwdtr);
2412         scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2413 
2414         if (p->wdtr_pending & target_mask)
2415         {
2416           /*
2417            * Don't send an WDTR back to the target, since we asked first.
2418            */
2419           outb(0, HA_RETURN_1(base));
2420           switch (bus_width)
2421           {
2422             case BUS_8_BIT:
2423               scratch &= 0x7F;
2424               break;
2425 
2426             case BUS_16_BIT:
2427               printk("aic7xxx: Target %d, channel %c, using 16 bit "
2428                      "transfers.\n", scsi_id, channel);
2429               scratch |= 0x80;
2430               break;
2431           }
2432         }
2433         else
2434         {
2435           /*
2436            * Send our own WDTR in reply.
2437            */
2438           printk("aic7xxx: Will send WDTR!!\n");
2439           switch (bus_width)
2440           {
2441             case BUS_8_BIT:
2442               scratch &= 0x7F;
2443               break;
2444 
2445             case BUS_32_BIT:
2446               /*
2447                * Negotiate 16 bits.
2448                */
2449               bus_width = BUS_16_BIT;
2450               /* Yes, we mean to fall thru here. */
2451 
2452             case BUS_16_BIT:
2453               printk("aic7xxx: Target %d, channel %c, using 16 bit "
2454                      "transfers.\n", scsi_id, channel);
2455               scratch |= 0x80;
2456               break;
2457           }
2458           outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
2459         }
2460         p->needwdtr &= ~target_mask;
2461         p->wdtr_pending &= ~target_mask;
2462         outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2463         outb(scratch, SCSIRATE(base));
2464         break;
2465       }
2466 
2467       case MSG_REJECT:
2468       {
2469         /*
2470          * What we care about here is if we had an
2471          * outstanding SDTR or WDTR message for this
2472          * target. If we did, this is a signal that
2473          * the target is refusing negotiation.
2474          */
2475 
2476         scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2477 
2478         if (p->wdtr_pending & target_mask)
2479         {
2480           /*
2481            * note 8bit xfers and clear flag
2482            */
2483           scratch &= 0x7F;
2484           p->needwdtr &= ~target_mask;
2485           p->wdtr_pending &= ~target_mask;
2486           outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2487           printk("aic7xxx: Target %d, channel %c, refusing WIDE negotiation. "
2488                  "Using 8 bit transfers.\n", scsi_id, channel);
2489         }
2490         else
2491         {
2492           if (p->sdtr_pending & target_mask)
2493           {
2494             /*
2495              * note asynch xfers and clear flag
2496              */
2497             scratch &= 0xF0;
2498             p->needsdtr &= ~target_mask;
2499             p->sdtr_pending &= ~target_mask;
2500             outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2501             printk("aic7xxx: Target %d, channel %c, refusing synchronous "
2502                    "negotiation. Using asynchronous transfers.\n",
2503                    scsi_id, channel);
2504           }
2505           /*
2506            * Otherwise, we ignore it.
2507            */
2508         }
2509         outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2510         outb(scratch, SCSIRATE(base));
2511         break;
2512       }
2513 
2514       case BAD_STATUS:
2515         scb_index = inb(SCBPTR(base));
2516         scb = &(p->scb_array[scb_index]);
2517         outb(0, HA_RETURN_1(base));   /* CHECK_CONDITION may change this */
2518         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2519         {
2520           printk("aic7xxx: Referenced SCB not valid during SEQINT(0x%x) "
2521                  "scb(%d) state(0x%x) cmd(0x%x).\n",
2522                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2523         }
2524         else
2525         {
2526           cmd = scb->cmd;
2527           aic7xxx_getscb(base, scb);
2528           aic7xxx_status(cmd) = scb->target_status;
2529 
2530           cmd->result |= scb->target_status;
2531 
2532           switch (status_byte(scb->target_status))
2533           {
2534             case GOOD:
2535               printk("aic7xxx: Interrupted for status of GOOD???\n");
2536               break;
2537 
2538             case CHECK_CONDITION:
2539               if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
2540               {
2541                 unsigned char tcl;
2542                 unsigned char control;
2543                 void         *req_buf;
2544 
2545                 tcl = scb->target_channel_lun;
2546                 /*
2547                  * Send a sense command to the requesting target.
2548                  */
2549                 cmd->flags |= WAS_SENSE;
2550                 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
2551                        sizeof(generic_sense));
2552 
2553                 scb->sense_cmd[1] = (cmd->lun << 5);
2554                 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
2555 
2556                 scb->sense_sg.address = (char *) &cmd->sense_buffer;
2557                 scb->sense_sg.length = sizeof(cmd->sense_buffer);
2558                 req_buf = &scb->sense_sg;
2559                 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
2560                 control = scb->control;
2561                 memset(scb, 0, SCB_DOWNLOAD_SIZE);
2562                 scb->control = control & SCB_DISCENB;
2563                 scb->target_channel_lun = tcl;
2564                 addr = scb->sense_cmd;
2565                 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
2566                 memcpy(scb->SCSI_cmd_pointer, &addr,
2567                        sizeof(scb->SCSI_cmd_pointer));
2568                 scb->SG_segment_count = 1;
2569                 memcpy(scb->SG_list_pointer, &req_buf,
2570                         sizeof(scb->SG_list_pointer));
2571                 scb->data_count[0] = scb->sense_sg.length & 0xFF;
2572                 scb->data_count[1] = (scb->sense_sg.length >> 8) & 0xFF;
2573                 scb->data_count[2] = (scb->sense_sg.length >> 16) & 0xFF;
2574                 memcpy(scb->data_pointer, &(scb->sense_sg.address), 4);
2575 
2576                 outb(SCBAUTO, SCBCNT(base));
2577                 asm volatile("cld\n\t"
2578                              "rep\n\t"
2579                              "outsb"
2580                              : /* no output */
2581                              :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
2582                              :"si", "cx", "dx");
2583                 outb(0, SCBCNT(base));
2584                 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
2585                 /*
2586                  * Ensure that the target is "BUSY" so we don't get overlapping
2587                  * commands if we happen to be doing tagged I/O.
2588                  */
2589                 active = inb(HA_ACTIVE0(base)) | (inb(HA_ACTIVE1(base)) << 8);
2590                 active |= target_mask;
2591                 outb(active & 0xFF, HA_ACTIVE0(base));
2592                 outb((active >> 8) & 0xFF, HA_ACTIVE1(base));
2593 
2594                 aic7xxx_add_waiting_scb(base, scb, LIST_HEAD);
2595                 outb(SEND_SENSE, HA_RETURN_1(base));
2596               }  /* first time sense, no errors */
2597               else
2598               {
2599                 /*
2600                  * Indicate that we asked for sense, have the sequencer do
2601                  * a normal command complete, and have the scsi driver handle
2602                  * this condition.
2603                  */
2604                 cmd->flags |= ASKED_FOR_SENSE;
2605               }
2606               break;
2607 
2608             case BUSY:
2609               printk("aic7xxx: Target busy.\n");
2610               if (!aic7xxx_error(cmd))
2611               {
2612                 aic7xxx_error(cmd) = DID_BUS_BUSY;
2613               }
2614               break;
2615 
2616             case QUEUE_FULL:
2617               printk("aic7xxx: Queue full.\n");
2618               if (!aic7xxx_error(cmd))
2619               {
2620                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2621               }
2622               break;
2623 
2624             default:
2625               printk("aic7xxx: Unexpected target status(0x%x).\n",
2626                      scb->target_status);
2627               if (!aic7xxx_error(cmd))
2628               {
2629                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2630               }
2631               break;
2632           }  /* end switch */
2633         }  /* end else of */
2634         break;
2635 
2636       case RESIDUAL:
2637         scb_index = inb(SCBPTR(base));
2638         scb = &(p->scb_array[scb_index]);
2639         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2640         {
2641           printk("aic7xxx: Referenced SCB not valid during SEQINT(0x%x) "
2642                  "scb(%d) state(0x%x) cmd(0x%x).\n",
2643                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2644         }
2645         else
2646         {
2647           cmd = scb->cmd;
2648           /*
2649            *  Don't destroy valid residual information with
2650            *  residual coming from a check sense operation.
2651            */
2652           if (!(cmd->flags & WAS_SENSE))
2653           {
2654             /*
2655              *  We had an underflow. At this time, there's only
2656              *  one other driver that bothers to check for this,
2657              *  and cmd->underflow seems to be set rather half-
2658              *  heartedly in the higher-level SCSI code.
2659              */
2660             actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
2661 
2662             actual -= ((inb(SCBARRAY(base + 17)) << 16) |
2663                        (inb(SCBARRAY(base + 16)) <<  8) |
2664                        inb(SCBARRAY(base + 15)));
2665 
2666             if (actual < cmd->underflow)
2667             {
2668               printk("aic7xxx: Target %d underflow - "
2669                      "Wanted (at least) (%u) got(%u) count(%d).\n",
2670                      cmd->target, cmd->underflow, actual,
2671                      inb(SCBARRAY(base + 18)));
2672               aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2673               aic7xxx_status(cmd) = scb->target_status;
2674             }
2675           }
2676         }
2677         break;
2678 
2679       case ABORT_TAG:
2680         scb_index = inb(SCBPTR(base));
2681         scb = &(p->scb_array[scb_index]);
2682         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2683         {
2684           printk("aic7xxx: Referenced SCB not valid during SEQINT(0x%x) "
2685                  "scb(%d) state(0x%x) cmd(0x%x)\n",
2686                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2687         }
2688         else
2689         {
2690           cmd = scb->cmd;
2691           /*
2692            * We didn't receive a valid tag back from the target
2693            * on a reconnect.
2694            */
2695           printk("aic7xxx: Invalid tag received on target %d, channel %c, "
2696                  "lun %d - Sending ABORT_TAG.\n",
2697                   scsi_id, channel, cmd->lun & 0x07);
2698 
2699           cmd->result = (DID_RETRY_COMMAND << 16);
2700           aic7xxx_done(p, scb);
2701         }
2702         break;
2703 
2704       case AWAITING_MSG:
2705         scb_index = inb(SCBPTR(base));
2706         scb = &(p->scb_array[scb_index]);
2707         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2708         {
2709           printk("aic7xxx: Referenced SCB not valid during SEQINT(0x%x) "
2710                  "scb(%d) state(0x%x) cmd(0x%x).\n",
2711                  intstat, scb_index, scb->state, (unsigned int) scb->cmd);
2712         }
2713         else
2714         {
2715           /*
2716            * This SCB had a zero length command, informing the sequencer
2717            * that we wanted to send a special message to this target.
2718            * We only do this for BUS_DEVICE_RESET messages currently.
2719            */
2720            if (scb->state & SCB_DEVICE_RESET)
2721            {
2722 #ifdef AIC7XXX_DEBUG_ABORT
2723   printk ("aic7xxx: (isr) sending bus device reset to target %d\n",
2724           scsi_id);
2725 #endif
2726              outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
2727              outb(1, HA_MSG_LEN(base));
2728            }
2729            else
2730            {
2731              panic("aic7xxx: AWAITING_SCB for an SCB that does "
2732                    "not have a waiting message.\n");
2733            }
2734         }
2735         break;
2736 
2737       case IMMEDDONE:
2738         scb_index = inb(SCBPTR(base));
2739         scb = &(p->scb_array[scb_index]);
2740 #ifdef AIC7XXX_DEBUG_ABORT
2741   printk ("aic7xxx: (isr) received IMMEDDONE for target %d, scb %d, state %d\n",
2742           scsi_id, scb_index, scb->state);
2743 #endif
2744         if (scb->state & SCB_DEVICE_RESET)
2745         {
2746           int found;
2747 
2748           /*
2749            * Go back to async/narrow transfers and renogiate.
2750            */
2751           aic7xxx_unbusy_target(scsi_id, channel, base);
2752           p->needsdtr |= (p->needsdtr_copy & target_mask);
2753           p->needwdtr |= (p->needwdtr_copy & target_mask);
2754           p->sdtr_pending &= ~target_mask;
2755           p->wdtr_pending &= ~target_mask;
2756           scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2757           scratch &= SXFR;
2758           outb(scratch, HA_TARG_SCRATCH(base));
2759           found = aic7xxx_reset_device(p, (int) scsi_id, channel, SCB_LIST_NULL);
2760         }
2761         else
2762         {
2763           panic("aic7xxx: Immediate complete for unknown operation.\n");
2764         }
2765         break;
2766 
2767       default:               /* unknown */
2768         debug("aic7xxx: SEQINT, INTSTAT(0x%x) SCSISIGI(0x%x).\n",
2769               intstat, inb(SCSISIGI(base)));
2770         break;
2771     }
2772     outb(CLRSEQINT, CLRINT(base));
2773     UNPAUSE_SEQUENCER(p);
2774   }
2775 
2776   if (intstat & SCSIINT)
2777   {
2778     int status = inb(SSTAT1(base));
2779 
2780     scb_index = inb(SCBPTR(base));
2781     scb = &(p->scb_array[scb_index]);
2782     if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2783     {
2784       printk("aic7xxx: No command for SCB (SCSIINT).\n");
2785       /*
2786        * Turn off the interrupt and set status
2787        * to zero, so that it falls through the
2788        * reset of the SCSIINT code.
2789        */
2790       outb(status, CLRSINT1(base));
2791       UNPAUSE_SEQUENCER(p);
2792       outb(CLRSCSIINT, CLRINT(base));
2793       status = 0;
2794       scb = NULL;
2795     }
2796     else
2797     {
2798       cmd = scb->cmd;
2799 
2800       /*
2801        * Only the SCSI Status 1 register has information
2802        * about exceptional conditions that we'd have a
2803        * SCSIINT about; anything in SSTAT0 will be handled
2804        * by the sequencer. Note that there can be multiple
2805        * bits set.
2806        */
2807       if (status & SELTO)
2808       {
2809         unsigned char target_mask = (1 << (cmd->target & 0x07));
2810         unsigned char waiting;
2811 
2812         /*
2813          * Hardware selection timer has expired. Turn
2814          * off SCSI selection sequence.
2815          */
2816         outb(ENRSELI, SCSISEQ(base));
2817         cmd->result = (DID_TIME_OUT << 16);
2818         /*
2819          * Clear an pending messages for the timed out
2820          * target and mark the target as free.
2821          */
2822         ha_flags = inb(HA_FLAGS(base));
2823         outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2824 
2825         if (scb->target_channel_lun & 0x88)
2826         {
2827           active = inb(HA_ACTIVE1(base));
2828           active = active & ~(target_mask);
2829           outb(active, HA_ACTIVE1(base));
2830         }
2831         else
2832         {
2833           active = inb(HA_ACTIVE0(base));
2834           active &= ~(target_mask);
2835           outb(active, HA_ACTIVE0(base));
2836         }
2837 
2838         outb(SCB_NEEDDMA, SCBARRAY(base));
2839 
2840         /*
2841          * Shut off the offending interrupt sources, reset
2842          * the sequencer address to zero and unpause it,
2843          * then call the high-level SCSI completion routine.
2844          *
2845          * WARNING!  This is a magic sequence!  After many
2846          * hours of guesswork, turning off the SCSI interrupts
2847          * in CLRSINT? does NOT clear the SCSIINT bit in
2848          * INTSTAT. By writing to the (undocumented, unused
2849          * according to the AIC-7770 manual) third bit of
2850          * CLRINT, you can clear INTSTAT. But, if you do it
2851          * while the sequencer is paused, you get a BRKADRINT
2852          * with an Illegal Host Address status, so the
2853          * sequencer has to be restarted first.
2854          */
2855         outb(CLRSELTIMEO, CLRSINT1(base));
2856 
2857         outb(CLRSCSIINT, CLRINT(base));
2858 
2859         /*
2860          * Shift the waiting for selection queue forward
2861          */
2862         waiting = inb(WAITING_SCBH(base));
2863         outb(waiting, SCBPTR(base));
2864         waiting = inb(SCBARRAY(base) + 30);
2865         outb(waiting, WAITING_SCBH(base));
2866 
2867         RESTART_SEQUENCER(p);
2868         aic7xxx_done(p, scb);
2869 #if 0
2870   printk("aic7xxx: SELTO SCB(%d) state(0x%x) cmd(0x%x).\n",
2871          scb->position, scb->state, (unsigned int) scb->cmd);
2872 #endif
2873       }
2874       else
2875       {
2876         if (status & SCSIPERR)
2877         {
2878           /*
2879            * A parity error has occurred during a data
2880            * transfer phase. Flag it and continue.
2881            */
2882           printk("aic7xxx: Parity error on target %d, channel %d, lun %d.\n",
2883                  cmd->target, cmd->channel & 0x01, cmd->lun & 0x07);
2884           aic7xxx_error(cmd) = DID_PARITY;
2885 
2886           /*
2887            * Clear interrupt and resume as above.
2888            */
2889           outb(CLRSCSIPERR, CLRSINT1(base));
2890           UNPAUSE_SEQUENCER(p);
2891 
2892           outb(CLRSCSIINT, CLRINT(base));
2893           scb = NULL;
2894         }
2895         else
2896         {
2897           if (!(status & BUSFREE))
2898           {
2899              /*
2900               * We don't know what's going on. Turn off the
2901               * interrupt source and try to continue.
2902               */
2903              printk("aic7xxx: SSTAT1(0x%x).\n", status);
2904              outb(status, CLRSINT1(base));
2905              UNPAUSE_SEQUENCER(p);
2906              outb(CLRSCSIINT, CLRINT(base));
2907              scb = NULL;
2908           }
2909         }
2910       }
2911     }  /* else */
2912   }
2913 
2914   if (intstat & CMDCMPLT)
2915   {
2916     int complete;
2917 
2918     /*
2919      * The sequencer will continue running when it
2920      * issues this interrupt. There may be >1 commands
2921      * finished, so loop until we've processed them all.
2922      */
2923     do {
2924       complete = inb(QOUTFIFO(base));
2925 
2926       scb = &(p->scb_array[complete]);
2927       if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2928       {
2929         printk("aic7xxx: Warning - No command for SCB %d (CMDCMPLT).\n"
2930                "         QOUTCNT(%d) SCB state(0x%x) cmd(0x%x) pos(%d).\n",
2931                complete, inb(QOUTFIFO(base)),
2932                scb->state, (unsigned int) scb->cmd, scb->position);
2933         outb(CLRCMDINT, CLRINT(base));
2934         continue;
2935       }
2936       cmd = scb->cmd;
2937 
2938       cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2939       if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2940       {
2941         /*
2942          * Got sense information.
2943          */
2944         cmd->flags &= ASKED_FOR_SENSE;
2945       }
2946 #if 0
2947       printk("aic7xxx: (complete) State(%d) cmd(0x%x) free(0x%x).\n",
2948              scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2949 #endif
2950 
2951       /*
2952        * Clear interrupt status before checking
2953        * the output queue again. This eliminates
2954        * a race condition whereby a command could
2955        * complete between the queue poll and the
2956        * interrupt clearing, so notification of the
2957        * command being complete never made it back
2958        * up to the kernel.
2959        */
2960       outb(CLRCMDINT, CLRINT(base));
2961       aic7xxx_done(p, scb);
2962 #if 0
2963   if (scb != &p->scb_array[scb->position])
2964   {
2965     printk("aic7xxx: (complete) Address mismatch, pos(%d).\n", scb->position);
2966   }
2967   printk("aic7xxx: (complete) State(%d) cmd(0x%x) free(0x%x).\n",
2968          scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2969 #endif
2970 
2971 #ifdef AIC7XXX_PROC_STATS
2972       /*
2973        * XXX: we should actually know how much actually transferred
2974        * XXX: for each command, but apparently that's too difficult.
2975        */
2976       actual = aic7xxx_length(cmd, 0);
2977       if (((cmd->flags & WAS_SENSE) == 0) && (actual > 0))
2978       {
2979         struct aic7xxx_xferstats *sp;
2980         long *ptr;
2981         int x;
2982 
2983         sp = &p->stats[cmd->channel & 0x01][cmd->target & 0x0F][cmd->lun & 0x07];
2984         sp->xfers++;
2985 
2986         if (cmd->request.cmd == WRITE)
2987         {
2988           sp->w_total++;
2989           sp->w_total512 += (actual >> 9);
2990           ptr = sp->w_bins;
2991         }
2992         else
2993         {
2994           sp->r_total++;
2995           sp->r_total512 += (actual >> 9);
2996           ptr = sp->r_bins;
2997         }
2998         for (x = 9; x <= 17; x++)
2999         {
3000           if (actual < (1 << x))
3001           {
3002             ptr[x - 9]++;
3003             break;
3004           }
3005         }
3006         if (x > 17)
3007         {
3008           ptr[x - 9]++;
3009         }
3010       }
3011 #endif /* AIC7XXX_PROC_STATS */
3012 
3013     } while (inb(QOUTCNT(base)));
3014   }
3015 }
3016 
3017 /*+F*************************************************************************
3018  * Function:
3019  *   aic7xxx_probe
3020  *
3021  * Description:
3022  *   Probing for EISA boards: it looks like the first two bytes
3023  *   are a manufacturer code - three characters, five bits each:
3024  *
3025  *               BYTE 0   BYTE 1   BYTE 2   BYTE 3
3026  *              ?1111122 22233333 PPPPPPPP RRRRRRRR
3027  *
3028  *   The characters are baselined off ASCII '@', so add that value
3029  *   to each to get the real ASCII code for it. The next two bytes
3030  *   appear to be a product and revision number, probably vendor-
3031  *   specific. This is what is being searched for at each port,
3032  *   and what should probably correspond to the ID= field in the
3033  *   ECU's .cfg file for the card - if your card is not detected,
3034  *   make sure your signature is listed in the array.
3035  *
3036  *   The fourth byte's lowest bit seems to be an enabled/disabled
3037  *   flag (rest of the bits are reserved?).
3038  *-F*************************************************************************/
3039 static aha_type
3040 aic7xxx_probe(int slot, int base)
     /*  */
3041 {
3042   int i;
3043   unsigned char buf[4];
3044 
3045   static struct {
3046     int n;
3047     unsigned char signature[sizeof(buf)];
3048     aha_type type;
3049   } AIC7xxx[] = {
3050     { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_7771 },  /* host adapter 274x */
3051     { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_7770 },  /* motherboard 7770  */
3052     { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x },  /* 284x, BIOS enabled */
3053     { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x }   /* 284x, BIOS disabled */
3054   };
3055 
3056   /*
3057    * The VL-bus cards need to be primed by
3058    * writing before a signature check.
3059    */
3060   for (i = 0; i < sizeof(buf); i++)
3061   {
3062     outb(0x80 + i, base);
3063     buf[i] = inb(base + i);
3064   }
3065 
3066   for (i = 0; i < NUMBER(AIC7xxx); i++)
3067   {
3068     /*
3069      * Signature match on enabled card?
3070      */
3071     if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
3072     {
3073       if (inb(base + 4) & 1)
3074       {
3075         return (AIC7xxx[i].type);
3076       }
3077 
3078       printk("aic7xxx: Disabled at slot %d, ignored.\n", slot);
3079     }
3080   }
3081 
3082   return (AIC_NONE);
3083 }
3084 
3085 /*+F*************************************************************************
3086  * Function:
3087  *   read_2840_seeprom
3088  *
3089  * Description:
3090  *   Reads the 2840 serial EEPROM and returns 1 if successful and 0 if
3091  *   not successful.
3092  *
3093  *   See read_seeprom (for the 2940) for the instruction set of the 93C46
3094  *   chip.
3095  *
3096  *   The 2840 interface to the 93C46 serial EEPROM is through the
3097  *   STATUS_2840 and SEECTL_2840 registers.  The CS_2840, CK_2840, and
3098  *   DO_2840 bits of the SEECTL_2840 register are connected to the chip
3099  *   select, clock, and data out lines respectively of the serial EEPROM.
3100  *   The DI_2840 bit of the STATUS_2840 is connected to the data in line
3101  *   of the serial EEPROM.  The EEPROM_TF bit of STATUS_2840 register is
3102  *   useful in that it gives us an 800 nsec timer.  After a read from the
3103  *   SEECTL_2840 register the timing flag is cleard and goes high 800 nsec
3104  *   later.
3105  *
3106  *-F*************************************************************************/
3107 static int
3108 read_2840_seeprom(int base, struct seeprom_config *sc)
     /*  */
3109 {
3110   int i = 0, k = 0;
3111   unsigned char temp;
3112   unsigned short checksum = 0;
3113   unsigned short *seeprom = (unsigned short *) sc;
3114   struct seeprom_cmd {
3115     unsigned char len;
3116     unsigned char bits[3];
3117   };
3118   struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
3119 
3120 #define CLOCK_PULSE(p) \
3121   while ((inb(STATUS_2840(base)) & EEPROM_TF) == 0)     \
3122   {                                             \
3123     ;  /* Do nothing */                         \
3124   }                                             \
3125   (void) inb(SEECTL_2840(base));
3126 
3127   /*
3128    * Read the first 32 registers of the seeprom.  For the 2840,
3129    * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers
3130    * but only the first 32 are used by Adaptec BIOS.  The loop
3131    * will range from 0 to 31.
3132    */
3133   for (k = 0; k < (sizeof(*sc) / 2); k++)
3134   {
3135     /*
3136      * Send chip select for one clock cycle.
3137      */
3138     outb(CK_2840 | CS_2840, SEECTL_2840(base));
3139     CLOCK_PULSE(base);
3140 
3141     /*
3142      * Now we're ready to send the read command followed by the
3143      * address of the 16-bit register we want to read.
3144      */
3145     for (i = 0; i < seeprom_read.len; i++)
3146     {
3147       temp = CS_2840 | seeprom_read.bits[i];
3148       outb(temp, SEECTL_2840(base));
3149       CLOCK_PULSE(base);
3150       temp = temp ^ CK_2840;
3151       outb(temp, SEECTL_2840(base));
3152       CLOCK_PULSE(base);
3153     }
3154     /*
3155      * Send the 6 bit address (MSB first, LSB last).
3156      */
3157     for (i = 5; i >= 0; i--)
3158     {
3159       temp = k;
3160       temp = (temp >> i) & 1;  /* Mask out all but lower bit. */
3161       temp = CS_2840 | temp;
3162       outb(temp, SEECTL_2840(base));
3163       CLOCK_PULSE(base);
3164       temp = temp ^ CK_2840;
3165       outb(temp, SEECTL_2840(base));
3166       CLOCK_PULSE(base);
3167     }
3168 
3169     /*
3170      * Now read the 16 bit register.  An initial 0 precedes the
3171      * register contents which begins with bit 15 (MSB) and ends
3172      * with bit 0 (LSB).  The initial 0 will be shifted off the
3173      * top of our word as we let the loop run from 0 to 16.
3174      */
3175     for (i = 0; i <= 16; i++)
3176     {
3177       temp = CS_2840;
3178       outb(temp, SEECTL_2840(base));
3179       CLOCK_PULSE(base);
3180       temp = temp ^ CK_2840;
3181       seeprom[k] = (seeprom[k] << 1) | (inb(STATUS_2840(base)) & DI_2840);
3182       outb(temp, SEECTL_2840(base));
3183       CLOCK_PULSE(base);
3184     }
3185     /*
3186      * The serial EEPROM has a checksum in the last word.  Keep a
3187      * running checksum for all words read except for the last
3188      * word.  We'll verify the checksum after all words have been
3189      * read.
3190      */
3191     if (k < (sizeof(*sc) / 2) - 1)
3192     {
3193       checksum = checksum + seeprom[k];
3194     }
3195 
3196     /*
3197      * Reset the chip select for the next command cycle.
3198      */
3199     outb(0, SEECTL_2840(base));
3200     CLOCK_PULSE(base);
3201     outb(CK_2840, SEECTL_2840(base));
3202     CLOCK_PULSE(base);
3203     outb(0, SEECTL_2840(base));
3204     CLOCK_PULSE(base);
3205   }
3206 
3207 #if 0
3208   printk("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
3209   printk("Serial EEPROM:");
3210   for (k = 0; k < (sizeof(*sc) / 2); k++)
3211   {
3212     if (((k % 8) == 0) && (k != 0))
3213     {
3214       printk("\n              ");
3215     }
3216     printk(" 0x%x", seeprom[k]);
3217   }
3218   printk("\n");
3219 #endif
3220 
3221   if (checksum != sc->checksum)
3222   {
3223     printk("aic7xxx: SEEPROM checksum error, ignoring SEEPROM settings.\n");
3224     return (0);
3225   }
3226 
3227   return (1);
3228 #undef CLOCK_PULSE
3229 }
3230 
3231 /*+F*************************************************************************
3232  * Function:
3233  *   read_seeprom
3234  *
3235  * Description:
3236  *   Reads the serial EEPROM and returns 1 if successful and 0 if
3237  *   not successful.
3238  *
3239  *   The instruction set of the 93C46 chip is as follows:
3240  *
3241  *               Start  OP
3242  *     Function   Bit  Code  Address    Data     Description
3243  *     -------------------------------------------------------------------
3244  *     READ        1    10   A5 - A0             Reads data stored in memory,
3245  *                                               starting at specified address
3246  *     EWEN        1    00   11XXXX              Write enable must preceed
3247  *                                               all programming modes
3248  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
3249  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
3250  *     ERAL        1    00   10XXXX              Erase all registers
3251  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
3252  *     EWDS        1    00   00XXXX              Disables all programming
3253  *                                               instructions
3254  *     *Note: A value of X for address is a don't care condition.
3255  *
3256  *   The 93C46 has a four wire interface: clock, chip select, data in, and
3257  *   data out.  In order to perform one of the above functions, you need
3258  *   to enable the chip select for a clock period (typically a minimum of
3259  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
3260  *   respectively.  While the chip select remains high, you can clock in
3261  *   the instructions (above) starting with the start bit, followed by the
3262  *   OP code, Address, and Data (if needed).  For the READ instruction, the
3263  *   requested 16-bit register contents is read from the data out line but
3264  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
3265  *   first).  The clock cycling from low to high initiates the next data
3266  *   bit to be sent from the chip.
3267  *
3268  *   The 7870 interface to the 93C46 serial EEPROM is through the SEECTL
3269  *   register.  After successful arbitration for the memory port, the
3270  *   SEECS bit of the SEECTL register is connected to the chip select.
3271  *   The SEECK, SEEDO, and SEEDI are connected to the clock, data out,
3272  *   and data in lines respectively.  The SEERDY bit of SEECTL is useful
3273  *   in that it gives us an 800 nsec timer.  After a write to the SEECTL
3274  *   register, the SEERDY goes high 800 nsec later.  The one exception
3275  *   to this is when we first request access to the memory port.  The
3276  *   SEERDY goes high to signify that access has been granted and, for
3277  *   this case, has no implied timing.
3278  *
3279  *-F*************************************************************************/
3280 static int
3281 read_seeprom(int base, int offset, struct seeprom_config *sc)
     /*  */
3282 {
3283   int i = 0, k;
3284   unsigned long timeout;
3285   unsigned char temp;
3286   unsigned short checksum = 0;
3287   unsigned short *seeprom = (unsigned short *) sc;
3288   struct seeprom_cmd {
3289     unsigned char len;
3290     unsigned char bits[3];
3291   };
3292   struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
3293 
3294 #define CLOCK_PULSE(p) \
3295   while ((inb(SEECTL(base)) & SEERDY) == 0)     \
3296   {                                             \
3297     ;  /* Do nothing */                         \
3298   }
3299 
3300   /*
3301    * Request access of the memory port.  When access is
3302    * granted, SEERDY will go high.  We use a 1 second
3303    * timeout which should be near 1 second more than
3304    * is needed.  Reason: after the 7870 chip reset, there
3305    * should be no contention.
3306    */
3307   outb(SEEMS, SEECTL(base));
3308   timeout = jiffies + 100;  /* 1 second timeout */
3309   while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
3310   {
3311     ; /* Do nothing!  Wait for access to be granted.  */
3312   }
3313   if ((inb(SEECTL(base)) & SEERDY) == 0)
3314   {
3315     outb(0, SEECTL(base));
3316     return (0);
3317   }
3318 
3319   /*
3320    * Read the first 32 registers of the seeprom.  For the 7870,
3321    * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers
3322    * but only the first 32 are used by Adaptec BIOS.  The loop
3323    * will range from 0 to 31.
3324    */
3325   for (k = 0; k < (sizeof(*sc) / 2); k++)
3326   {
3327     /*
3328      * Send chip select for one clock cycle.
3329      */
3330     outb(SEEMS | SEECK | SEECS, SEECTL(base));
3331     CLOCK_PULSE(base);
3332 
3333     /*
3334      * Now we're ready to send the read command followed by the
3335      * address of the 16-bit register we want to read.
3336      */
3337     for (i = 0; i < seeprom_read.len; i++)
3338     {
3339       temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
3340       outb(temp, SEECTL(base));
3341       CLOCK_PULSE(base);
3342       temp = temp ^ SEECK;
3343       outb(temp, SEECTL(base));
3344       CLOCK_PULSE(base);
3345     }
3346     /*
3347      * Send the 6 bit address (MSB first, LSB last).
3348      */
3349     for (i = 5; i >= 0; i--)
3350     {
3351       temp = k + offset;
3352       temp = (temp >> i) & 1;  /* Mask out all but lower bit. */
3353       temp = SEEMS | SEECS | (temp << 1);
3354       outb(temp, SEECTL(base));
3355       CLOCK_PULSE(base);
3356       temp = temp ^ SEECK;
3357       outb(temp, SEECTL(base));
3358       CLOCK_PULSE(base);
3359     }
3360 
3361     /*
3362      * Now read the 16 bit register.  An initial 0 precedes the
3363      * register contents which begins with bit 15 (MSB) and ends
3364      * with bit 0 (LSB).  The initial 0 will be shifted off the
3365      * top of our word as we let the loop run from 0 to 16.
3366      */
3367     for (i = 0; i <= 16; i++)
3368     {
3369       temp = SEEMS | SEECS;
3370       outb(temp, SEECTL(base));
3371       CLOCK_PULSE(base);
3372       temp = temp ^ SEECK;
3373       seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
3374       outb(temp, SEECTL(base));
3375       CLOCK_PULSE(base);
3376     }
3377 
3378     /*
3379      * The serial EEPROM has a checksum in the last word.  Keep a
3380      * running checksum for all words read except for the last
3381      * word.  We'll verify the checksum after all words have been
3382      * read.
3383      */
3384     if (k < (sizeof(*sc) / 2) - 1)
3385     {
3386       checksum = checksum + seeprom[k];
3387     }
3388 
3389     /*
3390      * Reset the chip select for the next command cycle.
3391      */
3392     outb(SEEMS, SEECTL(base));
3393     CLOCK_PULSE(base);
3394     outb(SEEMS | SEECK, SEECTL(base));
3395     CLOCK_PULSE(base);
3396     outb(SEEMS, SEECTL(base));
3397     CLOCK_PULSE(base);
3398   }
3399 
3400   /*
3401    * Release access to the memory port and the serial EEPROM.
3402    */
3403   outb(0, SEECTL(base));
3404 
3405 #if 0
3406   printk("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
3407   printk("Serial EEPROM:");
3408   for (k = 0; k < (sizeof(*sc) / 2); k++)
3409   {
3410     if (((k % 8) == 0) && (k != 0))
3411     {
3412       printk("\n              ");
3413     }
3414     printk(" 0x%x", seeprom[k]);
3415   }
3416   printk("\n");
3417 #endif
3418 
3419   if (checksum != sc->checksum)
3420   {
3421     printk("aic7xxx: SEEPROM checksum error, ignoring SEEPROM settings.\n");
3422     return (0);
3423   }
3424 
3425   return (1);
3426 #undef CLOCK_PULSE
3427 }
3428 
3429 /*+F*************************************************************************
3430  * Function:
3431  *   detect_maxscb
3432  *
3433  * Description:
3434  *   Return the maximum number of SCB's allowed for a given controller.
3435  *-F*************************************************************************/
3436 static int
3437 detect_maxscb(aha_type type, int base, int walk_scbs)
     /*  */
3438 {
3439   unsigned char sblkctl_reg, scb_byte;
3440   int maxscb = 0, i;
3441 
3442   switch (type)
3443   {
3444     case AIC_7770:
3445     case AIC_7771:
3446     case AIC_284x:
3447       /*
3448        * Check for Rev C or E boards. Rev E boards can supposedly have
3449        * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.
3450        * Until we know how to access more than 4 SCBs for the Rev E chips,
3451        * we limit them, along with the Rev C chips, to 4 SCBs.
3452        *
3453        * The Rev E boards have a read/write autoflush bit in the
3454        * SBLKCTL registor, while in the Rev C boards it is read only.
3455        */
3456       sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
3457       outb(sblkctl_reg, SBLKCTL(base));
3458       if (inb(SBLKCTL(base)) == sblkctl_reg)
3459       {
3460         /*
3461          * We detected a Rev E board.
3462          */
3463         printk("aic7770: Rev E and subsequent; using 4 SCB's.\n");
3464         outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
3465         maxscb = 4;
3466       }
3467       else
3468       {
3469         printk("aic7770: Rev C and previous; using 4 SCB's.\n");
3470         maxscb = 4;
3471       }
3472       break;
3473 
3474     case AIC_7850:
3475       maxscb = 3;
3476       break;
3477 
3478     case AIC_7870:
3479     case AIC_7871:
3480     case AIC_7874:
3481     case AIC_7880:
3482     case AIC_7881:
3483     case AIC_7884:
3484       maxscb = 16;
3485       break;
3486 
3487     case AIC_7872:
3488     case AIC_7873:
3489     case AIC_7882:
3490     case AIC_7883:
3491       /*
3492        * Is suppose to have 255 SCBs, but we'll walk the SCBs
3493        * looking for more if external RAM is detected.
3494        */
3495       maxscb = 16;
3496       break;
3497 
3498     case AIC_NONE:
3499       /*
3500        * This should never happen... But just in case.
3501        */
3502       break;
3503   }
3504   if (walk_scbs)
3505   {
3506     /*
3507      * This adapter has external SCB memory.
3508      * Walk the SCBs to determine how many there are.
3509      */
3510     i = 0;
3511     while (i < AIC7XXX_MAXSCB)
3512     {
3513       outb(i, SCBPTR(base));
3514       scb_byte = ~(inb(SCBARRAY(base)));  /* complement the byte */
3515       outb(scb_byte, SCBARRAY(base));     /* write it back out */
3516       if (inb(SCBARRAY(base)) != scb_byte)
3517       {
3518         break;
3519       }
3520       i++;
3521     }
3522     maxscb = i;
3523   }
3524 
3525   return (maxscb);
3526 }
3527 
3528 /*+F*************************************************************************
3529  * Function:
3530  *   aic7xxx_register
3531  *
3532  * Description:
3533  *   Register a Adaptec aic7xxx chip SCSI controller with the kernel.
3534  *-F*************************************************************************/
3535 static int
3536 aic7xxx_register(Scsi_Host_Template *template,
     /*  */
3537                  struct aic7xxx_host_config *config)
3538 {
3539   int i;
3540   unsigned char sblkctl;
3541   int max_targets;
3542   int found = 1, base;
3543   int bios_disabled = 0;
3544   unsigned char target_settings;
3545   unsigned char scsi_conf, host_conf;
3546   int have_seeprom = 0;
3547   struct Scsi_Host *host;
3548   struct aic7xxx_host *p;
3549   struct seeprom_config sc;
3550 
3551   base = config->base;
3552 
3553   /*
3554    * Lock out other contenders for our i/o space.
3555    */
3556   request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
3557 
3558   switch (config->type)
3559   {
3560     case AIC_7770:
3561     case AIC_7771:
3562       /*
3563        * For some 274x boards, we must clear the CHIPRST bit
3564        * and pause the sequencer. For some reason, this makes
3565        * the driver work. For 284x boards, we give it a
3566        * CHIPRST just like the 294x boards.
3567        *
3568        * Use the BIOS settings to determine the interrupt
3569        * trigger type (level or edge) and use this value
3570        * for pausing and unpausing the sequencer.
3571        */
3572       config->unpause = (inb(HCNTRL(base)) & IRQMS) | INTEN;
3573       config->pause = config->unpause | PAUSE;
3574       config->extended = aic7xxx_extended;
3575 
3576       outb(config->pause | CHIPRST, HCNTRL(base));
3577       aic7xxx_delay(1);
3578       if (inb(HCNTRL(base)) & CHIPRST)
3579       {
3580         printk("aic7xxx: Chip reset not cleared; clearing manually.\n");
3581       }
3582       outb(config->pause, HCNTRL(base));
3583 
3584       /*
3585        * Just to be on the safe side with the 274x, we will re-read the irq
3586        * since there was some issue about reseting the board.
3587        */
3588       config->irq = inb(HA_INTDEF(base)) & 0x0F;
3589       if ((inb(HA_274_BIOSCTRL(base)) & BIOSMODE) == BIOSDISABLED)
3590       {
3591         bios_disabled = 1;
3592       }
3593       host_conf = inb(HA_HOSTCONF(base));
3594       config->busrtime = host_conf & 0x3C;
3595       /* XXX Is this valid for motherboard based controllers? */
3596       /* Setup the FIFO threshold and the bus off time */
3597       outb(host_conf & DFTHRSH, BUSSPD(base));
3598       outb((host_conf << 2) & BOFF, BUSTIME(base));
3599 
3600       /*
3601        * A reminder until this can be detected automatically.
3602        */
3603       printk("aic7xxx: Extended translation %sabled.\n",
3604              config->extended ? "en" : "dis");
3605       break;
3606 
3607     case AIC_284x:
3608       outb(CHIPRST, HCNTRL(base));
3609       config->unpause = UNPAUSE_284X;
3610       config->pause = REQ_PAUSE; /* DWG would like to be like the rest */
3611       aic7xxx_delay(1);
3612       outb(config->pause, HCNTRL(base));
3613 
3614       config->extended = aic7xxx_extended;
3615       config->irq = inb(HA_INTDEF(base)) & 0x0F;
3616       if ((inb(HA_274_BIOSCTRL(base)) & BIOSMODE) == BIOSDISABLED)
3617       {
3618         bios_disabled = 1;
3619       }
3620       host_conf = inb(HA_HOSTCONF(base));
3621 
3622       printk("aic7xxx: Reading SEEPROM...");
3623       have_seeprom = read_2840_seeprom(base, &sc);
3624       if (!have_seeprom)
3625       {
3626         printk("aic7xxx: Unable to read SEEPROM.\n");
3627         config->busrtime = host_conf & 0x3C;
3628       }
3629       else
3630       {
3631         printk("done.\n");
3632         config->extended = ((sc.bios_control & CF284XEXTEND) >> 5);
3633         config->scsi_id = (sc.brtime_id & CFSCSIID);
3634         config->parity = (sc.adapter_control & CFSPARITY) ?
3635                          AIC_ENABLED : AIC_DISABLED;
3636         config->low_term = (sc.adapter_control & CF284XSTERM) ?
3637                               AIC_ENABLED : AIC_DISABLED;
3638         /*
3639          * XXX - Adaptec *does* make 284x wide controllers, but the
3640          *       documents do not say where the high byte termination
3641          *       enable bit is located.  For now, we'll just assume
3642          *       that it's in the same place as for the 2940 card.
3643          */
3644         config->high_term = (sc.adapter_control & CFWSTERM) ?
3645                               AIC_ENABLED : AIC_DISABLED;
3646         config->busrtime = ((sc.brtime_id & CFBRTIME) >> 8);
3647       }
3648       /* XXX Is this valid for motherboard based controllers? */
3649       /* Setup the FIFO threshold and the bus off time */
3650       outb(host_conf & DFTHRSH, BUSSPD(base));
3651       outb((host_conf << 2) & BOFF, BUSTIME(base));
3652 
3653       printk("aic7xxx: Extended translation %sabled.\n",
3654              config->extended ? "en" : "dis");
3655       break;
3656 
3657     case AIC_7850:
3658     case AIC_7870:
3659     case AIC_7871:
3660     case AIC_7872:
3661     case AIC_7873:
3662     case AIC_7874:
3663     case AIC_7880:
3664     case AIC_7881:
3665     case AIC_7882:
3666     case AIC_7883:
3667     case AIC_7884:
3668       outb(CHIPRST, HCNTRL(base));
3669       config->unpause = UNPAUSE_294X;
3670       config->pause = config->unpause | PAUSE;
3671       aic7xxx_delay(1);
3672       outb(config->pause, HCNTRL(base));
3673 
3674       config->extended = aic7xxx_extended;
3675       config->scsi_id = 7;
3676 
3677       printk("aic7xxx: Reading SEEPROM...");
3678       have_seeprom = read_seeprom(base, config->chan_num * (sizeof(sc) / 2), &sc);
3679       if (!have_seeprom)
3680       {
3681         printk("aic7xxx: Unable to read SEEPROM.\n");
3682       }
3683       else
3684       {
3685         printk("done.\n");
3686         config->extended = ((sc.bios_control & CFEXTEND) >> 7);
3687         config->scsi_id = (sc.brtime_id & CFSCSIID);
3688         config->parity = (sc.adapter_control & CFSPARITY) ?
3689                          AIC_ENABLED : AIC_DISABLED;
3690         config->low_term = (sc.adapter_control & CFSTERM) ?
3691                               AIC_ENABLED : AIC_DISABLED;
3692         config->high_term = (sc.adapter_control & CFWSTERM) ?
3693                               AIC_ENABLED : AIC_DISABLED;
3694         config->busrtime = ((sc.brtime_id & CFBRTIME) >> 8);
3695         if (((config->type == AIC_7880) || (config->type == AIC_7882) ||
3696              (config->type == AIC_7883) || (config->type == AIC_7884)) &&
3697             (sc.adapter_control & CFULTRAEN))
3698         {
3699           printk ("aic7xxx: Enabling support for Ultra SCSI speed.\n");
3700           config->ultra_enabled = TRUE;
3701         }
3702       }
3703 
3704       /*
3705        * XXX - force data fifo threshold to 100%. Why does this
3706        *       need to be done?
3707        */
3708       outb(inb(DSPCISTATUS(base)) | DFTHRESH, DSPCISTATUS(base));
3709       outb(config->scsi_id | DFTHRESH, HA_SCSICONF(base));
3710 
3711       /*
3712        * In case we are a wide card, place scsi ID in second conf byte.
3713        */
3714       outb(config->scsi_id, (HA_SCSICONF(base) + 1));
3715 
3716       printk("aic7xxx: Extended translation %sabled.\n",
3717              config->extended ? "en" : "dis");
3718       break;
3719 
3720     default:
3721       panic("aic7xxx: (aic7xxx_register) Internal error.\n");
3722   }
3723 
3724   config->maxscb = detect_maxscb(config->type, base, config->walk_scbs);
3725 
3726   if (config->chip_type == AIC_777x)
3727   {
3728     if (config->pause & IRQMS)
3729     {
3730       printk("aic7xxx: Using level sensitive interrupts.\n");
3731     }
3732     else
3733     {
3734       printk("aic7xxx: Using edge triggered interrupts.\n");
3735     }
3736   }
3737 
3738   /*
3739    * Read the bus type from the SBLKCTL register. Set the FLAGS
3740    * register in the sequencer for twin and wide bus cards.
3741    */
3742   sblkctl = inb(SBLKCTL(base));
3743   switch (sblkctl & SELBUS_MASK)
3744   {
3745     case SELSINGLE:     /* narrow/normal bus */
3746       config->scsi_id = inb(HA_SCSICONF(base)) & 0x07;
3747       config->bus_type = AIC_SINGLE;
3748       outb(SINGLE_BUS, HA_FLAGS(base));
3749       break;
3750 
3751     case SELWIDE:     /* Wide bus */
3752       config->scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
3753       config->bus_type = AIC_WIDE;
3754       printk("aic7xxx: Enabling wide channel of %s-Wide.\n",
3755              board_names[config->type]);
3756       outb(WIDE_BUS, HA_FLAGS(base));
3757       break;
3758 
3759     case SELBUSB:     /* Twin bus */
3760       config->scsi_id = inb(HA_SCSICONF(base)) & 0x07;
3761 #ifdef AIC7XXX_TWIN_SUPPORT
3762       config->scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
3763       config->bus_type = AIC_TWIN;
3764       printk("aic7xxx: Enabled channel B of %s-Twin.\n",
3765              board_names[config->type]);
3766       outb(TWIN_BUS, HA_FLAGS(base));
3767 #else
3768       config->bus_type = AIC_SINGLE;
3769       printk("aic7xxx: Channel B of %s-Twin will be ignored.\n",
3770              board_names[config->type]);
3771       outb(0, HA_FLAGS(base));
3772 #endif
3773       break;
3774 
3775     default:
3776       printk("aic7xxx: Unsupported type 0x%x, please "
3777              "mail deang@ims.com\n", inb(SBLKCTL(base)));
3778       outb(0, HA_FLAGS(base));
3779       return (0);
3780   }
3781 
3782   /*
3783    * For the 294x cards, clearing DIAGLEDEN and DIAGLEDON, will
3784    * take the card out of diagnostic mode and make the host adatper
3785    * LED follow bus activity (will not always be on).
3786    */
3787   outb(sblkctl & ~(DIAGLEDEN | DIAGLEDON), SBLKCTL(base));
3788 
3789   /*
3790    * The IRQ level in i/o port 4 maps directly onto the real
3791    * IRQ number. If it's ok, register it with the kernel.
3792    *
3793    * NB. the Adaptec documentation says the IRQ number is only
3794    *     in the lower four bits; the ECU information shows the
3795    *     high bit being used as well. Which is correct?
3796    *
3797    * The PCI cards get their interrupt from PCI BIOS.
3798    */
3799   if ((config->chip_type == AIC_777x) && ((config->irq < 9) || (config->irq > 15)))
3800   {
3801     printk("aic7xxx: Host adapter uses unsupported IRQ level, ignoring.\n");
3802     return (0);
3803   }
3804 
3805   /*
3806    * Check the IRQ to see if it is shared by another aic7xxx
3807    * controller. If it is and sharing of IRQs is not defined,
3808    * then return 0 hosts found. If sharing of IRQs is allowed
3809    * or the IRQ is not shared by another host adapter, then
3810    * proceed.
3811    */
3812 #ifndef AIC7XXX_SHARE_IRQS
3813    if (aic7xxx_boards[config->irq] != NULL)
3814    {
3815      printk("aic7xxx: Sharing of IRQ's is not configured.\n");
3816      return (0);
3817    }
3818 #endif
3819 
3820   /*
3821    * Print out debugging information before re-enabling
3822    * the card - a lot of registers on it can't be read
3823    * when the sequencer is active.
3824    */
3825   debug_config(config);
3826 
3827   /*
3828    * Before registry, make sure that the offsets of the
3829    * struct scatterlist are what the sequencer will expect,
3830    * otherwise disable scatter-gather altogether until someone
3831    * can fix it. This is important since the sequencer will
3832    * DMA elements of the SG array in while executing commands.
3833    */
3834   if (template->sg_tablesize != SG_NONE)
3835   {
3836     struct scatterlist sg;
3837 
3838     if (SG_STRUCT_CHECK(sg))
3839     {
3840       printk("aic7xxx: Warning - Kernel scatter-gather structures changed, "
3841              "disabling it.\n");
3842       template->sg_tablesize = SG_NONE;
3843     }
3844   }
3845 
3846   /*
3847    * Register each "host" and fill in the returned Scsi_Host
3848    * structure as best we can. Some of the parameters aren't
3849    * really relevant for bus types beyond ISA, and none of the
3850    * high-level SCSI code looks at it anyway. Why are the fields
3851    * there? Also save the pointer so that we can find the
3852    * information when an IRQ is triggered.
3853    */
3854   host = scsi_register(template, sizeof(struct aic7xxx_host));
3855   host->can_queue = config->maxscb;
3856   host->cmd_per_lun = AIC7XXX_CMDS_PER_LUN;
3857   host->this_id = config->scsi_id;
3858   host->irq = config->irq;
3859   if (config->bus_type == AIC_WIDE)
3860   {
3861     host->max_id = 16;
3862   }
3863   if (config->bus_type == AIC_TWIN)
3864   {
3865     host->max_channel = 1;
3866   }
3867 
3868   p = (struct aic7xxx_host *) host->hostdata;
3869 
3870   /*
3871    * Initialize the scb array by setting the state to free.
3872    */
3873   for (i = 0; i < AIC7XXX_MAXSCB; i++)
3874   {
3875     p->scb_array[i].state = SCB_FREE;
3876     p->scb_array[i].next = NULL;
3877     p->scb_array[i].cmd = NULL;
3878   }
3879 
3880   p->isr_count = 0;
3881   p->a_scanned = 0;
3882   p->b_scanned = 0;
3883   p->base = base;
3884   p->maxscb = config->maxscb;
3885   p->numscb = 0;
3886   p->extended = config->extended;
3887   p->type = config->type;
3888   p->chip_type = config->chip_type;
3889   p->ultra_enabled = config->ultra_enabled;
3890   p->chan_num = config->chan_num;
3891   p->bus_type = config->bus_type;
3892   p->have_seeprom = have_seeprom;
3893   p->seeprom = sc;
3894   p->free_scb = NULL;
3895   p->next = NULL;
3896 
3897   p->unpause = config->unpause;
3898   p->pause = config->pause;
3899 
3900   if (aic7xxx_boards[config->irq] == NULL)
3901   {
3902     /*
3903      * Warning! This must be done before requesting the irq.  It is
3904      * possible for some boards to raise an interrupt as soon as
3905      * they are enabled.  So when we request the irq from the Linux
3906      * kernel, an interrupt is triggered immediately.  Therefore, we
3907      * must ensure the board data is correctly set before the request.
3908      */
3909     aic7xxx_boards[config->irq] = host;
3910 
3911     /*
3912      * Register IRQ with the kernel.
3913      */
3914     if (request_irq(config->irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
3915     {
3916       printk("aic7xxx: Couldn't register IRQ %d, ignoring.\n", config->irq);
3917       aic7xxx_boards[config->irq] = NULL;
3918       return (0);
3919     }
3920   }
3921   else
3922   {
3923     /*
3924      * We have found a host adapter sharing an IRQ of a previously
3925      * registered host adapter. Add this host adapter's Scsi_Host
3926      * to the beginning of the linked list of hosts at the same IRQ.
3927      */
3928     p->next = aic7xxx_boards[config->irq];
3929     aic7xxx_boards[config->irq] = host;
3930   }
3931 
3932   /*
3933    * Load the sequencer program, then re-enable the board -
3934    * resetting the AIC-7770 disables it, leaving the lights
3935    * on with nobody home. On the PCI bus you *may* be home,
3936    * but then your mailing address is dynamically assigned
3937    * so no one can find you anyway :-)
3938    */
3939   printk("aic7xxx: Downloading sequencer code...");
3940   aic7xxx_loadseq(base);
3941 
3942   /*
3943    * Set Fast Mode and Enable the board
3944    */
3945   outb(FASTMODE, SEQCTL(base));
3946 
3947   if (p->chip_type == AIC_777x)
3948   {
3949     outb(ENABLE, BCTL(base));
3950   }
3951 
3952   printk("done.\n");
3953 
3954   /*
3955    * Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels
3956    */
3957   if (p->bus_type == AIC_TWIN)
3958   {
3959     /*
3960      * Select Channel B.
3961      */
3962     outb((sblkctl & ~SELBUS_MASK) | SELBUSB, SBLKCTL(base));
3963 
3964     outb(config->scsi_id_b, SCSIID(base));
3965     scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
3966     outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
3967     outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3968     if (p->ultra_enabled)
3969     {
3970       outb(ULTRAEN, SXFRCTL0(base));
3971     }
3972 
3973     /*
3974      * Select Channel A
3975      */
3976     outb((sblkctl & ~SELBUS_MASK) | SELSINGLE, SBLKCTL(base));
3977   }
3978   outb(config->scsi_id, SCSIID(base));
3979   scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
3980   outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
3981   outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3982   if (p->ultra_enabled)
3983   {
3984     outb(ULTRAEN, SXFRCTL0(base));
3985   }
3986 
3987   /*
3988    * Look at the information that board initialization or the board
3989    * BIOS has left us. In the lower four bits of each target's
3990    * scratch space any value other than 0 indicates that we should
3991    * initiate synchronous transfers. If it's zero, the user or the
3992    * BIOS has decided to disable synchronous negotiation to that
3993    * target so we don't activate the needsdtr flag.
3994    */
3995   p->needsdtr_copy = 0;
3996   p->sdtr_pending = 0;
3997   p->needwdtr_copy = 0;
3998   p->wdtr_pending = 0;
3999   if (p->bus_type == AIC_SINGLE)
4000   {
4001     max_targets = 8;
4002   }
4003   else
4004   {
4005     max_targets = 16;
4006   }
4007 
4008   /*
4009    * Grab the disconnection disable table and invert it for our needs
4010    */
4011   if (have_seeprom)
4012   {
4013     p->discenable = 0;
4014   }
4015   else
4016   {
4017     if (bios_disabled)
4018     {
4019       printk("aic7xxx : Host adapter BIOS disabled. Using default SCSI "
4020              "device parameters.\n");
4021       p->discenable = 0xFFFF;
4022     }
4023     else
4024     {
4025       p->discenable = ~((inb(HA_DISC_DSB(base) + 1) << 8) |
4026           inb(HA_DISC_DSB(base)));
4027     }
4028   }
4029 
4030   for (i = 0; i < max_targets; i++)
4031   {
4032     if (have_seeprom)
4033     {
4034       target_settings = ((sc.device_flags[i] & CFXFER) << 4);
4035       if (sc.device_flags[i] & CFSYNCH)
4036       {
4037         p->needsdtr_copy |= (0x01 << i);
4038       }
4039       if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
4040       {
4041         p->needwdtr_copy |= (0x01 << i);
4042       }
4043       if (sc.device_flags[i] & CFDISC)
4044       {
4045         p->discenable |= (0x01 << i);
4046       }
4047     }
4048     else
4049     {
4050       target_settings = inb(HA_TARG_SCRATCH(base) + i);
4051       if (target_settings & 0x0F)
4052       {
4053         p->needsdtr_copy |= (0x01 << i);
4054         /*
4055          * Default to asynchronous transfers (0 offset)
4056          */
4057         target_settings &= 0xF0;
4058       }
4059       /*
4060        * If we are not wide, forget WDTR. This makes the driver
4061        * work on some cards that don't leave these fields cleared
4062        * when BIOS is not installed.
4063        */
4064       if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
4065       {
4066         p->needwdtr_copy |= (0x01 << i);
4067         target_settings &= 0x7F;
4068       }
4069     }
4070     outb(target_settings, (HA_TARG_SCRATCH(base) + i));
4071   }
4072 
4073   p->needsdtr = p->needsdtr_copy;
4074   p->needwdtr = p->needwdtr_copy;
4075 #if 0
4076   printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
4077   printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
4078 #endif
4079 
4080   /*
4081    * Clear the control byte for every SCB so that the sequencer
4082    * doesn't get confused and think that one of them is valid
4083    */
4084   for (i = 0; i < config->maxscb; i++)
4085   {
4086     outb(i, SCBPTR(base));
4087     outb(0, SCBARRAY(base));
4088   }
4089 
4090   /*
4091    * For reconnecting targets, the sequencer code needs to
4092    * know how many SCBs it has to search through.
4093    */
4094   outb(config->maxscb, HA_SCBCOUNT(base));
4095 
4096   /*
4097    * Clear the active flags - no targets are busy.
4098    */
4099   outb(0, HA_ACTIVE0(base));
4100   outb(0, HA_ACTIVE1(base));
4101 
4102   /*
4103    * We don't have any waiting selections
4104    */
4105   outb(SCB_LIST_NULL, WAITING_SCBH(base));
4106   outb(SCB_LIST_NULL, WAITING_SCBT(base));
4107 
4108   /*
4109    * Reset the SCSI bus. Is this necessary?
4110    *   There may be problems for a warm boot without resetting
4111    *   the SCSI bus. Either BIOS settings in scratch RAM
4112    *   will not get reinitialized, or devices may stay at
4113    *   previous negotiated settings (SDTR and WDTR) while
4114    *   the driver will think that no negotiations have been
4115    *   performed.
4116    *
4117    * Some devices need a long time to "settle" after a SCSI
4118    * bus reset.
4119    */
4120 
4121   if (!aic7xxx_no_reset)
4122   {
4123     printk("aic7xxx: Resetting the SCSI bus...");
4124     if (p->bus_type == AIC_TWIN)
4125     {
4126       /*
4127        * Select Channel B.
4128        */
4129       outb((sblkctl & ~SELBUS_MASK) | SELBUSB, SBLKCTL(base));
4130 
4131       outb(SCSIRSTO, SCSISEQ(base));
4132       udelay(1000);
4133       outb(0, SCSISEQ(base));
4134 
4135       /*
4136        * Select Channel A.
4137        */
4138       outb((sblkctl & ~SELBUS_MASK) | SELSINGLE, SBLKCTL(base));
4139     }
4140 
4141     outb(SCSIRSTO, SCSISEQ(base));
4142     udelay(1000);
4143     outb(0, SCSISEQ(base));
4144 
4145     aic7xxx_delay(AIC7XXX_RESET_DELAY);
4146 
4147     printk("done.\n");
4148   }
4149 
4150   /*
4151    * Unpause the sequencer before returning and enable
4152    * interrupts - we shouldn't get any until the first
4153    * command is sent to us by the high-level SCSI code.
4154    */
4155   UNPAUSE_SEQUENCER(p);
4156   return (found);
4157 }
4158 
4159 /*+F*************************************************************************
4160  * Function:
4161  *   aic7xxx_detect
4162  *
4163  * Description:
4164  *   Try to detect and register an Adaptec 7770 or 7870 SCSI controller.
4165  *-F*************************************************************************/
4166 int
4167 aic7xxx_detect(Scsi_Host_Template *template)
     /*  */
4168 {
4169   int found = 0, slot, base;
4170   unsigned char irq = 0;
4171   int i;
4172   struct aic7xxx_host_config config;
4173 
4174   template->proc_dir = &proc_scsi_aic7xxx;
4175   config.chan_num = 0;
4176 
4177   /*
4178    * Since we may allow sharing of IRQs, it is imperative
4179    * that we "null-out" the aic7xxx_boards array. It is
4180    * not guaranteed to be initialized to 0 (NULL). We use
4181    * a NULL entry to indicate that no prior hosts have
4182    * been found/registered for that IRQ.
4183    */
4184   for (i = 0; i <= MAXIRQ; i++)
4185   {
4186     aic7xxx_boards[i] = NULL;
4187   }
4188 
4189   /*
4190    * Initialize the spurious count to 0.
4191    */
4192   aic7xxx_spurious_count = 0;
4193 
4194   /*
4195    * EISA/VL-bus card signature probe.
4196    */
4197   for (slot = MINSLOT; slot <= MAXSLOT; slot++)
4198   {
4199     base = SLOTBASE(slot);
4200 
4201     if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
4202     {
4203       /*
4204        * Some other driver has staked a
4205        * claim to this i/o region already.
4206        */
4207       continue;
4208     }
4209 
4210     config.type = aic7xxx_probe(slot, HID0(base));
4211     if (config.type != AIC_NONE)
4212     {
4213       /*
4214        * We found a card, allow 1 spurious interrupt.
4215        */
4216       aic7xxx_spurious_count = 1;
4217 
4218       /*
4219        * We "find" a AIC-7770 if we locate the card
4220        * signature and we can set it up and register
4221        * it with the kernel without incident.
4222        */
4223       config.chip_type = AIC_777x;
4224       config.base = base;
4225       config.irq = irq;
4226       config.parity = AIC_UNKNOWN;
4227       config.low_term = AIC_UNKNOWN;
4228       config.high_term = AIC_UNKNOWN;
4229       config.busrtime = 0;
4230       config.walk_scbs = FALSE;
4231       config.ultra_enabled = FALSE;
4232       found += aic7xxx_register(template, &config);
4233 
4234       /*
4235        * Disallow spurious interrupts.
4236        */
4237       aic7xxx_spurious_count = 0;
4238     }
4239   }
4240 
4241 #ifdef CONFIG_PCI
4242   /*
4243    * PCI-bus probe.
4244    */
4245   if (pcibios_present())
4246   {
4247     struct
4248     {
4249       unsigned short vendor_id;
4250       unsigned short device_id;
4251       aha_type       card_type;
4252       aha_chip_type  chip_type;
4253     } const aic7xxx_pci_devices[] = {
4254       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7850, AIC_7850, AIC_785x},
4255       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7870, AIC_7870, AIC_787x},
4256       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7871, AIC_7871, AIC_787x},
4257       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7872, AIC_7872, AIC_787x},
4258       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7873, AIC_7873, AIC_787x},
4259       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7874, AIC_7874, AIC_787x},
4260       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7880, AIC_7880, AIC_788x},
4261       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7881, AIC_7881, AIC_788x},
4262       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7882, AIC_7882, AIC_788x},
4263       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7883, AIC_7883, AIC_788x},
4264       {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_7884, AIC_7884, AIC_788x}
4265     };
4266 
4267     int error;
4268     int done = 0;
4269     unsigned int io_port;
4270     unsigned short index = 0;
4271     unsigned char pci_bus, pci_device_fn;
4272     unsigned char devrevid, devconfig, devstatus;
4273     char rev_id[] = {'B', 'C', 'D'};
4274 
4275     for (i = 0; i < NUMBER(aic7xxx_pci_devices); i++)
4276     {
4277       done = FALSE;
4278       while (!done)
4279       {
4280         if (pcibios_find_device(aic7xxx_pci_devices[i].vendor_id,
4281                                 aic7xxx_pci_devices[i].device_id,
4282                                 index, &pci_bus, &pci_device_fn))
4283         {
4284           done = TRUE;
4285         }
4286         else  /* Found an Adaptec PCI device. */
4287         {
4288           config.type = aic7xxx_pci_devices[i].card_type;
4289           config.chip_type = aic7xxx_pci_devices[i].chip_type;
4290           switch (config.type)
4291           {
4292             case AIC_7872:  /* 3940 */
4293             case AIC_7882:  /* 3940-Ultra */
4294               config.chan_num = number_of_39xxs & 0x1;  /* Has 2 controllers */
4295               number_of_39xxs++;
4296               if (number_of_39xxs == 2)
4297               {
4298                 number_of_39xxs = 0;  /* To be consistent with 3985. */
4299               }
4300               break;
4301 
4302             case AIC_7873:  /* 3985 */
4303             case AIC_7883:  /* 3985-Ultra */
4304               config.chan_num = number_of_39xxs & 0x3;  /* Has 3 controllers */
4305               number_of_39xxs++;
4306               if (number_of_39xxs == 3)
4307               {
4308                 number_of_39xxs = 0;
4309               }
4310               break;
4311 
4312             default:
4313               break;
4314           }
4315 
4316           /*
4317            * Read esundry information from PCI BIOS.
4318            */
4319           error = pcibios_read_config_dword(pci_bus, pci_device_fn,
4320                                             PCI_BASE_ADDRESS_0, &io_port);
4321           if (error)
4322           {
4323             panic("aic7xxx: (aic7xxx_detect) Error %d reading I/O port.\n",
4324                   error);
4325           }
4326 
4327           error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4328                                            PCI_INTERRUPT_LINE, &irq);
4329           if (error)
4330           {
4331             panic("aic7xxx: (aic7xxx_detect) Error %d reading IRQ.\n",
4332                    error);
4333           }
4334 
4335           error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4336                                            DEVREVID, &devrevid);
4337           if (error)
4338           {
4339             panic("aic7xxx: (aic7xxx_detect) Error %d reading device "
4340                   "revision ID.\n", error);
4341           }
4342 
4343           if (devrevid < 3)
4344           {
4345             printk("aic7xxx: %s Rev %c.\n", board_names[config.type],
4346                    rev_id[devrevid]);
4347           }
4348 
4349           error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4350                                            DEVCONFIG, &devconfig);
4351           if (error)
4352           {
4353             panic("aic7xxx: (aic7xxx_detect) Error %d reading device "
4354                   "configuration.\n", error);
4355           }
4356 
4357           error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4358                                            DEVSTATUS, &devstatus);
4359           if (error)
4360           {
4361             panic("aic7xxx: (aic7xxx_detect) Error %d reading device status.\n",
4362                   error);
4363           }
4364 
4365           printk("aic7xxx: devconfig(0x%x) devstatus(0x%x).\n",
4366                  devconfig, devstatus);
4367 
4368           /*
4369            * Make the base I/O register look like EISA and VL-bus.
4370            */
4371           base = io_port - 0xC01;
4372 
4373           /*
4374            * I don't think we need to bother with allowing
4375            * spurious interrupts for the 787x/7850, but what
4376            * the hey.
4377            */
4378           aic7xxx_spurious_count = 1;
4379 
4380           config.base = base;
4381           config.irq = irq;
4382           config.parity = AIC_UNKNOWN;
4383           config.low_term = AIC_UNKNOWN;
4384           config.high_term = AIC_UNKNOWN;
4385           config.busrtime = 0;
4386           config.walk_scbs = FALSE;
4387           config.ultra_enabled = FALSE;
4388           if ((devstatus & RAMPSM) || (devconfig & SCBRAMSEL))
4389           {
4390             config.walk_scbs = TRUE;
4391           }
4392           found += aic7xxx_register(template, &config);
4393 
4394           /*
4395            * Disable spurious interrupts.
4396            */
4397           aic7xxx_spurious_count = 0;
4398 
4399           index++;
4400         }  /* Found an Adaptec PCI device. */
4401       }
4402     }
4403   }
4404 #endif CONFIG_PCI
4405 
4406   template->name = aic7xxx_info(NULL);
4407   return (found);
4408 }
4409 
4410 
4411 /*+F*************************************************************************
4412  * Function:
4413  *   aic7xxx_buildscb
4414  *
4415  * Description:
4416  *   Build a SCB.
4417  *-F*************************************************************************/
4418 static void
4419 aic7xxx_buildscb(struct aic7xxx_host *p,
     /*  */
4420                  Scsi_Cmnd *cmd,
4421                  struct aic7xxx_scb *scb)
4422 {
4423   void *addr;
4424   unsigned short mask;
4425   struct scatterlist *sg;
4426 
4427   /*
4428    * Setup the control byte if we need negotiation and have not
4429    * already requested it.
4430    */
4431 #ifdef AIC7XXX_TAGGED_QUEUEING
4432   if (cmd->device->tagged_supported)
4433   {
4434     if (cmd->device->tagged_queue == 0)
4435     {
4436       printk("aic7xxx: Enabling tagged queuing for target %d, "
4437              "channel %d.\n", cmd->target, cmd->channel);
4438       cmd->device->tagged_queue = 1;
4439       cmd->device->current_tag = 1;  /* enable tagging */
4440     }
4441     cmd->tag = cmd->device->current_tag;
4442     cmd->device->current_tag++;
4443     scb->control |= SCB_TE;
4444   }
4445 #endif
4446   mask = (0x01 << (cmd->target | (cmd->channel << 3)));
4447   if (p->discenable & mask)
4448   {
4449     scb->control |= SCB_DISCENB;
4450   }
4451   if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
4452   {
4453     p->wdtr_pending |= mask;
4454     scb->control |= SCB_NEEDWDTR;
4455 #if 0
4456     printk("aic7xxx: Sending WDTR request to target %d.\n", cmd->target);
4457 #endif
4458   }
4459   else
4460   {
4461     if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
4462     {
4463       p->sdtr_pending |= mask;
4464       scb->control |= SCB_NEEDSDTR;
4465 #if 0
4466       printk("aic7xxx: Sending SDTR request to target %d.\n", cmd->target);
4467 #endif
4468     }
4469   }
4470 
4471 #if 0
4472   printk("aic7xxx: (build_scb) Target %d, cmd(0x%x) size(%u) wdtr(0x%x) "
4473          "mask(0x%x).\n",
4474          cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
4475 #endif
4476   scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
4477         ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
4478 
4479   /*
4480    * The interpretation of request_buffer and request_bufflen
4481    * changes depending on whether or not use_sg is zero; a
4482    * non-zero use_sg indicates the number of elements in the
4483    * scatter-gather array.
4484    */
4485 
4486   /*
4487    * XXX - this relies on the host data being stored in a
4488    *       little-endian format.
4489    */
4490   addr = cmd->cmnd;
4491   scb->SCSI_cmd_length = cmd->cmd_len;
4492   memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
4493 
4494   if (cmd->use_sg)
4495   {
4496 #if 0
4497     debug("aic7xxx: (build_scb) SG used, %d segments, length(%u).\n",
4498            cmd->use_sg, length);
4499 #endif
4500     scb->SG_segment_count = cmd->use_sg;
4501     memcpy(scb->SG_list_pointer, &cmd->request_buffer,
4502            sizeof(scb->SG_list_pointer));
4503     memcpy(&sg, &cmd->request_buffer, sizeof(sg));
4504     memcpy(scb->data_pointer, &(sg[0].address), sizeof(scb->data_pointer));
4505     scb->data_count[0] = sg[0].length & 0xFF;
4506     scb->data_count[1] = (sg[0].length >> 8) & 0xFF;
4507     scb->data_count[2] = (sg[0].length >> 16) & 0xFF;
4508   }
4509   else
4510   {
4511 #if 0
4512   debug("aic7xxx: (build_scb) Creating scatterlist, addr(0x%lx) length(%d).\n",
4513         (unsigned long) cmd->request_buffer, cmd->request_bufflen);
4514 #endif
4515     if (cmd->request_bufflen == 0)
4516     {
4517       /*
4518        * In case the higher level SCSI code ever tries to send a zero
4519        * length command, ensure the SCB indicates no data.  The driver
4520        * will interpret a zero length command as a Bus Device Reset.
4521        */
4522       scb->SG_segment_count = 0;
4523       memset(scb->SG_list_pointer, 0, sizeof(scb->SG_list_pointer));
4524       memset(scb->data_pointer, 0, sizeof(scb->data_pointer));
4525       memset(scb->data_count, 0, sizeof(scb->data_count));
4526     }
4527     else
4528     {
4529       scb->SG_segment_count = 1;
4530       scb->sg.address = (char *) cmd->request_buffer;
4531       scb->sg.length = cmd->request_bufflen;
4532       addr = &scb->sg;
4533       memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
4534       scb->data_count[0] = scb->sg.length & 0xFF;
4535       scb->data_count[1] = (scb->sg.length >> 8) & 0xFF;
4536       scb->data_count[2] = (scb->sg.length >> 16) & 0xFF;
4537       memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
4538     }
4539   }
4540 }
4541 
4542 /*+F*************************************************************************
4543  * Function:
4544  *   aic7xxx_queue
4545  *
4546  * Description:
4547  *   Queue a SCB to the controller.
4548  *-F*************************************************************************/
4549 int
4550 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
     /*  */
4551 {
4552   long flags;
4553   struct aic7xxx_host *p;
4554   struct aic7xxx_scb *scb;
4555   unsigned char curscb;
4556 
4557   p = (struct aic7xxx_host *) cmd->host->hostdata;
4558 
4559   /*
4560    * Check to see if channel was scanned.
4561    */
4562   if (!p->a_scanned && (cmd->channel == 0))
4563   {
4564     printk("aic7xxx: Scanning channel A for devices.\n");
4565     p->a_scanned = 1;
4566   }
4567   else
4568   {
4569     if (!p->b_scanned && (cmd->channel == 1))
4570     {
4571       printk("aic7xxx: Scanning channel B for devices.\n");
4572       p->b_scanned = 1;
4573     }
4574   }
4575 
4576 #if 0
4577   debug("aic7xxx_queue: cmd(0x%x) size(%u), target %d, channel %d, lun %d.\n",
4578         cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
4579         cmd->lun & 0x07);
4580 #endif
4581 
4582   /*
4583    * This is a critical section, since we don't want the
4584    * interrupt routine mucking with the host data or the
4585    * card. Since the kernel documentation is vague on
4586    * whether or not we are in a cli/sti pair already, save
4587    * the flags to be on the safe side.
4588    */
4589   save_flags(flags);
4590   cli();
4591 
4592   /*
4593    * Find a free slot in the SCB array to load this command
4594    * into. Since can_queue is set to the maximum number of
4595    * SCBs for the card, we should always find one.
4596    *
4597    * First try to find an scb in the free list. If there are
4598    * none in the free list, then check the current number of
4599    * of scbs and take an unused one from the scb array.
4600    */
4601   scb = p->free_scb;
4602   if (scb != NULL)
4603   { /* found one in the free list */
4604     p->free_scb = scb->next;   /* remove and update head of list */
4605     /*
4606      * Warning! For some unknown reason, the scb at the head
4607      * of the free list is not the same address that it should
4608      * be. That's why we set the scb pointer taken by the
4609      * position in the array. The scb at the head of the list
4610      * should match this address, but it doesn't.
4611      */
4612     scb = &(p->scb_array[scb->position]);
4613     scb->control = 0;
4614     scb->state = SCB_ACTIVE;
4615   }
4616   else
4617   {
4618     if (p->numscb >= p->maxscb)
4619     {
4620       panic("aic7xxx: (aic7xxx_queue) Couldn't find a free SCB.\n");
4621     }
4622     else
4623     {
4624       /*
4625        * Initialize the scb within the scb array. The
4626        * position within the array is the position on
4627        * the board that it will be loaded.
4628        */
4629       scb = &(p->scb_array[p->numscb]);
4630       memset(scb, 0, sizeof(*scb));
4631 
4632       scb->position = p->numscb;
4633       p->numscb++;
4634       scb->state = SCB_ACTIVE;
4635       scb->next_waiting = SCB_LIST_NULL;
4636       memcpy(scb->host_scb, &scb, sizeof(scb));
4637       scb->control = SCB_NEEDDMA;
4638       PAUSE_SEQUENCER(p);
4639       curscb = inb(SCBPTR(p->base));
4640       outb(scb->position, SCBPTR(p->base));
4641       aic7xxx_putscb_dma(p->base, scb);
4642       outb(curscb, SCBPTR(p->base));
4643       UNPAUSE_SEQUENCER(p);
4644       scb->control = 0;
4645     }
4646   }
4647 
4648   scb->cmd = cmd;
4649   aic7xxx_position(cmd) = scb->position;
4650 #if 0
4651   debug_scb(scb);
4652 #endif;
4653 
4654   /*
4655    * Construct the SCB beforehand, so the sequencer is
4656    * paused a minimal amount of time.
4657    */
4658   aic7xxx_buildscb(p, cmd, scb);
4659 
4660 #if 0
4661   if (scb != &p->scb_array[scb->position])
4662   {
4663     printk("aic7xxx: (queue) Address of SCB by position does not match SCB "
4664            "address.\n");
4665   }
4666   printk("aic7xxx: (queue) SCB pos(%d) cmdptr(0x%x) state(%d) freescb(0x%x)\n",
4667          scb->position, (unsigned int) scb->cmd,
4668          scb->state, (unsigned int) p->free_scb);
4669 #endif
4670   /*
4671    * Pause the sequencer so we can play with its registers -
4672    * wait for it to acknowledge the pause.
4673    *
4674    * XXX - should the interrupts be left on while doing this?
4675    */
4676   PAUSE_SEQUENCER(p);
4677 
4678   /*
4679    * Save the SCB pointer and put our own pointer in - this
4680    * selects one of the four banks of SCB registers. Load
4681    * the SCB, then write its pointer into the queue in FIFO
4682    * and restore the saved SCB pointer.
4683    */
4684   aic7xxx_putscb(p->base, scb);
4685 
4686   /*
4687    * Make sure the Scsi_Cmnd pointer is saved, the struct it
4688    * points to is set up properly, and the parity error flag
4689    * is reset, then unpause the sequencer and watch the fun
4690    * begin.
4691    */
4692   cmd->scsi_done = fn;
4693   aic7xxx_error(cmd) = DID_OK;
4694   aic7xxx_status(cmd) = 0;
4695   cmd->result = 0;
4696   memset(&cmd->sense_buffer, 0, sizeof(cmd->sense_buffer));
4697 
4698   UNPAUSE_SEQUENCER(p);
4699 #if 0
4700   printk("aic7xxx: (queue) After - cmd(0x%lx) scb->cmd(0x%lx) pos(%d).\n",
4701          (long) cmd, (long) scb->cmd, scb->position);
4702 #endif;
4703   restore_flags(flags);
4704   return (0);
4705 }
4706 
4707 /*+F*************************************************************************
4708  * Function:
4709  *   aic7xxx_abort_scb
4710  *
4711  * Description:
4712  *   Abort an scb.  If the scb has not previously been aborted, then
4713  *   we attempt to send a BUS_DEVICE_RESET message to the target.  If
4714  *   the scb has previously been unsuccessfully aborted, then we will
4715  *   reset the channel and have all devices renegotiate.  Returns an
4716  *   enumerated type that indicates the status of the operation.
4717  *-F*************************************************************************/
4718 static aha_abort_reset_type
4719 aic7xxx_abort_scb(struct aic7xxx_host *p, struct aic7xxx_scb *scb,
     /*  */
4720                   unsigned char errcode)
4721 {
4722   int base = p->base;
4723   int found = 0;
4724   aha_abort_reset_type scb_status = ABORT_RESET_SUCCESS;
4725   char channel = scb->target_channel_lun & SELBUSB ? 'B': 'A';
4726 
4727   /*
4728    * Ensure that the card doesn't do anything
4729    * behind our back.
4730    */
4731   PAUSE_SEQUENCER(p);
4732 
4733 #ifdef AIC7XXX_DEBUG_ABORT 
4734   printk ("aic7xxx: (abort_scb) scb %d, scb_aborted 0x%x\n",
4735           scb->position, (scb->state & SCB_ABORTED));
4736 #endif
4737   /*
4738    * First, determine if we want to do a bus reset or simply a bus device
4739    * reset.  If this is the first time that a transaction has timed out,
4740    * just schedule a bus device reset.  Otherwise, we reset the bus and
4741    * abort all pending I/Os on that bus.
4742    */
4743   if (scb->state & SCB_ABORTED)
4744   {
4745     /*
4746      * Been down this road before.  Do a full bus reset.
4747      */
4748     found = aic7xxx_reset_channel(p, channel, scb->position);
4749   }
4750   else
4751   {
4752     unsigned char active_scb, control;
4753     struct aic7xxx_scb *active_scbp;
4754 
4755     /*
4756      * Send a Bus Device Reset Message:
4757      * The target we select to send the message to may be entirely
4758      * different than the target pointed to by the scb that timed
4759      * out.  If the command is in the QINFIFO or the waiting for
4760      * selection list, its not tying up the bus and isn't responsible
4761      * for the delay so we pick off the active command which should
4762      * be the SCB selected by SCBPTR.  If its disconnected or active,
4763      * we device reset the target scbp points to.  Although it may
4764      * be that this target is not responsible for the delay, it may
4765      * may also be that we're timing out on a command that just takes
4766      * too much time, so we try the bus device reset there first.
4767      */
4768     active_scb = inb(SCBPTR(base));
4769     active_scbp = &(p->scb_array[active_scb]);
4770     control = inb(SCBARRAY(base));
4771 
4772     /*
4773      * Test to see if scbp is disconnected
4774      */
4775     outb(scb->position, SCBPTR(base));
4776     if (inb(SCBARRAY(base)) & SCB_DIS)
4777     {
4778 #ifdef AIC7XXX_DEBUG_ABORT
4779   printk ("aic7xxx: (abort_scb) scb %d is disconnected.\n", scb->position);
4780 #endif
4781       scb->state |= (SCB_DEVICE_RESET | SCB_ABORTED);
4782       scb->SG_segment_count = 0;
4783       memset(scb->SG_list_pointer, 0, sizeof(scb->SG_list_pointer));
4784       memset(scb->data_pointer, 0, sizeof(scb->data_pointer));
4785       memset(scb->data_count, 0, sizeof(scb->data_count));
4786       outb(SCBAUTO, SCBCNT(base));
4787       asm volatile("cld\n\t"
4788                    "rep\n\t"
4789                    "outsb"
4790                    : /* no output */
4791                    :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
4792                    :"si", "cx", "dx");
4793       outb(0, SCBCNT(base));
4794       aic7xxx_error(scb->cmd) = errcode;
4795       scb_status = ABORT_RESET_PENDING;
4796       aic7xxx_add_waiting_scb(base, scb, LIST_SECOND);
4797       UNPAUSE_SEQUENCER(p);
4798     }
4799     else
4800     {
4801       /*
4802        * Is the active SCB really active?
4803        */
4804       if ((active_scbp->state & SCB_ACTIVE) && (control & SCB_NEEDDMA))
4805       {
4806         unsigned char flags = inb(HA_FLAGS(base));
4807         if (flags & ACTIVE_MSG)
4808         {
4809 #ifdef AIC7XXX_DEBUG_ABORT
4810           printk ("aic7xxx: (abort_scb) scb is active, needs DMA, "
4811                   "ha_flags active.\n");
4812 #endif
4813           /*
4814            * If we're in a message phase, tacking on another message
4815            * may confuse the target totally. The bus is probably wedged,
4816            * so reset the channel.
4817            */
4818           channel = (active_scbp->target_channel_lun & SELBUSB) ? 'B': 'A';
4819           aic7xxx_reset_channel(p, channel, scb->position);
4820         }
4821         else
4822         {
4823 #ifdef AIC7XXX_DEBUG_ABORT
4824           printk ("aic7xxx: (abort_scb) scb is active, needs DMA, "
4825                   "ha_flags inactive.\n");
4826 #endif
4827           /*
4828            * Load the message buffer and assert attention.
4829            */
4830           active_scbp->state |= (SCB_DEVICE_RESET | SCB_ABORTED);
4831           outb(flags | ACTIVE_MSG, HA_FLAGS(base));
4832           outb(1, HA_MSG_LEN(base));
4833           outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
4834           if (active_scbp->target_channel_lun != scb->target_channel_lun)
4835           {
4836             /*
4837              * XXX - We would like to increment the timeout on scb, but
4838              *       access to that routine is denied because it is hidden
4839              *       in scsi.c.  If we were able to do this, it would give
4840              *       scb a new lease on life.
4841              */
4842             ;
4843           }
4844           aic7xxx_error(scb->cmd) = errcode;
4845           scb_status = ABORT_RESET_PENDING;
4846           UNPAUSE_SEQUENCER(p);
4847         }
4848       }
4849       else
4850       {
4851 #ifdef AIC7XXX_DEBUG_ABORT
4852           printk ("aic7xxx: (abort_scb) no active command.\n");
4853 #endif
4854         /*
4855          * No active command to single out, so reset
4856          * the bus for the timed out target.
4857          */
4858         aic7xxx_reset_channel(p, channel, scb->position);
4859       }
4860     }
4861   }
4862   return (scb_status);
4863 }
4864 
4865 /*+F*************************************************************************
4866  * Function:
4867  *   aic7xxx_abort_reset
4868  *
4869  * Description:
4870  *   Abort or reset the current SCSI command(s).  Returns an enumerated
4871  *   type that indicates the status of the operation.
4872  *-F*************************************************************************/
4873 static aha_abort_reset_type
4874 aic7xxx_abort_reset(Scsi_Cmnd *cmd, unsigned char errcode)
     /*  */
4875 {
4876   struct aic7xxx_scb  *scb;
4877   struct aic7xxx_host *p;
4878   long flags;
4879   aha_abort_reset_type scb_status = ABORT_RESET_SUCCESS;
4880 
4881   p = (struct aic7xxx_host *) cmd->host->hostdata;
4882   scb = &(p->scb_array[aic7xxx_position(cmd)]);
4883 
4884   save_flags(flags);
4885   cli();
4886 
4887 #ifdef AIC7XXX_DEBUG_ABORT
4888   printk ("aic7xxx: (abort_reset) scb state 0x%x\n", scb->state);
4889 #endif
4890 
4891   if (scb->state & SCB_ACTIVE)
4892   {
4893     if (scb->state & SCB_IMMED)
4894     {
4895       /*
4896        * Don't know how set the number of retries to 0.
4897        */
4898       /* cmd->retries = 0; */
4899       aic7xxx_error(cmd) = errcode;
4900       aic7xxx_done (p, scb);
4901     }
4902     else
4903     {
4904       /*
4905        * Abort the operation.
4906        */
4907       scb_status = aic7xxx_abort_scb(p, scb, errcode);
4908     }
4909   }
4910   else
4911   {
4912     /*
4913      * The scb is not active and must have completed after the timeout
4914      * check in scsi.c and before we check the scb state above.  For
4915      * this case we return SCSI_ABORT_NOT_RUNNING (if abort was called)
4916      * or SCSI_RESET_SUCCESS (if reset was called).
4917      */
4918 #ifdef AIC7XXX_DEBUG_ABORT
4919     printk ("aic7xxx: (abort_reset) called with no active scb, errcode 0x%x\n",
4920             errcode);
4921 #endif
4922     scb_status = ABORT_RESET_INACTIVE;
4923     /*
4924      * According to the comments in scsi.h and Michael Neuffer, if we do not
4925      * have an active command for abort or reset, we should not call the
4926      * command done function.  Unfortunately, this hangs the system for me
4927      * unless we *do* call the done function.
4928      *
4929      * XXX - Revisit this sometime!
4930      */
4931     cmd->result = errcode << 16;
4932     cmd->scsi_done(cmd);
4933   }
4934   restore_flags(flags);
4935   return (scb_status);
4936 }
4937 
4938 
4939 /*+F*************************************************************************
4940  * Function:
4941  *   aic7xxx_abort
4942  *
4943  * Description:
4944  *   Abort the current SCSI command(s).
4945  *-F*************************************************************************/
4946 int
4947 aic7xxx_abort(Scsi_Cmnd *cmd)
     /*  */
4948 {
4949 #ifdef AIC7XXX_DEBUG_ABORT
4950   printk ("aic7xxx: (abort) target/channel %d/%d\n", cmd->target, cmd->channel);
4951 #endif
4952 
4953   switch (aic7xxx_abort_reset(cmd, DID_ABORT))
4954   {
4955     case ABORT_RESET_INACTIVE:
4956       return (SCSI_ABORT_NOT_RUNNING);
4957       break;
4958     case ABORT_RESET_PENDING:
4959       return (SCSI_ABORT_PENDING);
4960       break;
4961     case ABORT_RESET_SUCCESS:
4962     default:
4963       return (SCSI_ABORT_SUCCESS);
4964       break;
4965   }
4966 }
4967 
4968 /*+F*************************************************************************
4969  * Function:
4970  *   aic7xxx_reset
4971  *
4972  * Description:
4973  *   Resetting the bus always succeeds - is has to, otherwise the
4974  *   kernel will panic! Try a surgical technique - sending a BUS
4975  *   DEVICE RESET message - on the offending target before pulling
4976  *   the SCSI bus reset line.
4977  *-F*************************************************************************/
4978 int
4979 aic7xxx_reset(Scsi_Cmnd *cmd)
     /*  */
4980 {
4981 #ifdef AIC7XXX_DEBUG_ABORT
4982   printk ("aic7xxx: (reset) target/channel %d/%d\n", cmd->target, cmd->channel);
4983 #endif
4984 
4985   switch (aic7xxx_abort_reset(cmd, DID_RESET))
4986   {
4987     case ABORT_RESET_PENDING:
4988       return (SCSI_RESET_PENDING);
4989       break;
4990     case ABORT_RESET_INACTIVE:
4991     case ABORT_RESET_SUCCESS:
4992     default:
4993       return (SCSI_RESET_SUCCESS);
4994       break;
4995   }
4996 }
4997 
4998 /*+F*************************************************************************
4999  * Function:
5000  *   aic7xxx_biosparam
5001  *
5002  * Description:
5003  *   Return the disk geometry for the given SCSI device.
5004  *-F*************************************************************************/
5005 int
5006 aic7xxx_biosparam(Disk *disk, kdev_t dev, int geom[])
     /*  */
5007 {
5008   int heads, sectors, cylinders;
5009   struct aic7xxx_host *p;
5010 
5011   p = (struct aic7xxx_host *) disk->device->host->hostdata;
5012 
5013   /*
5014    * XXX - if I could portably find the card's configuration
5015    *       information, then this could be autodetected instead
5016    *       of left to a boot-time switch.
5017    */
5018   heads = 64;
5019   sectors = 32;
5020   cylinders = disk->capacity / (heads * sectors);
5021 
5022   if (p->extended && cylinders > 1024)
5023   {
5024     heads = 255;
5025     sectors = 63;
5026     cylinders = disk->capacity / (255 * 63);
5027   }
5028 
5029   geom[0] = heads;
5030   geom[1] = sectors;
5031   geom[2] = cylinders;
5032 
5033   return (0);
5034 }
5035 
5036 #include "aic7xxx_proc.c"
5037 
5038 #ifdef MODULE
5039 /* Eventually this will go into an include file, but this will be later */
5040 Scsi_Host_Template driver_template = AIC7XXX;
5041 
5042 #include "scsi_module.c"
5043 #endif
5044 
5045 /*
5046  * Overrides for Emacs so that we almost follow Linus's tabbing style.
5047  * Emacs will notice this stuff at the end of the file and automatically
5048  * adjust the settings for this buffer only.  This must remain at the end
5049  * of the file.
5050  * ---------------------------------------------------------------------------
5051  * Local variables:
5052  * c-indent-level: 2
5053  * c-brace-imaginary-offset: 0
5054  * c-brace-offset: -2
5055  * c-argdecl-indent: 2
5056  * c-label-offset: -2
5057  * c-continued-statement-offset: 2
5058  * c-continued-brace-offset: 0
5059  * indent-tabs-mode: nil
5060  * tab-width: 8
5061  * End:
5062  */
/* */
root/drivers/scsi/aic7xxx.c

DEFINITIONS
