include/asm-sparc/psr.h

/* */
This source file includes following definitions.
get_psr
put_psr
get_fsr
get_v9_pstate
put_v9_pstate
get_v9_version
get_v9_tstate
get_v9_pil
put_v9_pil
   1 /* $Id: psr.h,v 1.5 1995/11/25 02:32:31 davem Exp $
   2  * psr.h: This file holds the macros for masking off various parts of
   3  *        the processor status register on the Sparc. This is valid
   4  *        for Version 8. On the V9 this is renamed to the PSTATE
   5  *        register and its members are accessed as fields like
   6  *        PSTATE.PRIV for the current CPU privilege level.
   7  *
   8  * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
   9  */
  10 
  11 #ifndef __LINUX_SPARC_PSR_H
  12 #define __LINUX_SPARC_PSR_H
  13 
  14 #define __LINUX_SPARC_V8  /* duh */
  15 
  16 #ifdef __LINUX_SPARC_V8
  17 
  18 /* The Sparc PSR fields are laid out as the following:
  19  *
  20  *  ------------------------------------------------------------------------
  21  *  | impl  | vers  | icc   | resv  | EC | EF | PIL  | S | PS | ET |  CWP  |
  22  *  | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
  23  *  ------------------------------------------------------------------------
  24  */
  25 
  26 #define PSR_CWP     0x0000001f         /* current window pointer     */
  27 #define PSR_ET      0x00000020         /* enable traps field         */
  28 #define PSR_PS      0x00000040         /* previous privilege level   */
  29 #define PSR_S       0x00000080         /* current privilege level    */
  30 #define PSR_PIL     0x00000f00         /* processor interrupt level  */
  31 #define PSR_EF      0x00001000         /* enable floating point      */
  32 #define PSR_EC      0x00002000         /* enable co-processor        */
  33 #define PSR_ICC     0x00f00000         /* integer condition codes    */
  34 #define PSR_C       0x00100000         /* carry bit                  */
  35 #define PSR_V       0x00200000         /* overflow bit               */
  36 #define PSR_Z       0x00400000         /* zero bit                   */
  37 #define PSR_N       0x00800000         /* negative bit               */
  38 #define PSR_VERS    0x0f000000         /* cpu-version field          */
  39 #define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
  40 
  41 #ifndef __ASSEMBLY__
  42 /* Get the %psr register. */
  43 extern inline unsigned int get_psr(void)
     /*  */
  44 {
  45         unsigned int psr;
  46         __asm__ __volatile__("rd %%psr, %0\n\t" :
  47                              "=r" (psr));
  48         return psr;
  49 }
  50 
  51 extern inline void put_psr(unsigned int new_psr)
     /*  */
  52 {
  53   __asm__("wr %0, 0x0, %%psr\n\t" : :
  54           "r" (new_psr));
  55 }
  56 
  57 /* Get the %fsr register.  Be careful, make sure the floating point
  58  * enable bit is set in the %psr when you execute this or you will
  59  * incur a trap.
  60  */
  61 
  62 extern unsigned int fsr_storage;
  63 
  64 extern inline unsigned int get_fsr(void)
     /*  */
  65 {
  66         unsigned int fsr = 0;
  67 
  68         __asm__ __volatile__("st %%fsr, %1\n\t"
  69                              "ld %1, %0\n\t" :
  70                              "=r" (fsr) :
  71                              "m" (fsr_storage));
  72         return fsr;
  73 }
  74 
  75 #endif /* !(__ASSEMBLY__) */
  76 
  77 #endif /* !(__LINUX_SPARC_V8) */
  78 
  79 #ifdef __LINUX_SPARC_V9
  80 
  81 /* The information available in the %psr on the V8 is spread amongst
  82  * a whole bunch of registers on the V9. The main one being PSTATE.
  83  *
  84  *   --------------------------------------------------------
  85  *   |  CLE  | TLE |  MM  | RED | PEF | AM | PRIV | IE | AG |
  86  *   |   9   |  8  |  7-6 |  5  |  4  |  3 |   2  |  1 |  0 |
  87  *   --------------------------------------------------------
  88  *
  89  * Writes and reads to PSTATE are done via 'wrpr' and 'rdpr' instructions.
  90  *
  91  * For example:  wrpr %o2, or'd_bit_pattern, %pstate
  92  *               rdpr %pstate, %o3
  93  */
  94 
  95 #define PSTATE_AG    0x001   /* Alternate Globals             */
  96 #define PSTATE_IE    0x002   /* Interrupt Enable              */
  97 #define PSTATE_PRIV  0x004   /* Current privilege level       */
  98 #define PSTATE_AM    0x008   /* Address mask (data reads can  */
  99                              /* be chosen to be either big or */
 100                              /* little endian on V9).         */
 101 #define PSTATE_PEF   0x010   /* enable floating point         */
 102 #define PSTATE_RED   0x020   /* RED trap state (set if trap   */
 103                              /* trap_level == max_tl).        */
 104 #define PSTATE_MM    0x0c0   /* Memory model (Total Store     */
 105                              /* Order=0, Partial Store Order  */
 106                              /* =1 or Relaxed Memory Order=2) */
 107 #define PSTATE_TLE   0x100   /* Trap Little Endian            */
 108 #define PSTATE_CLE   0x200   /* Current Little Endian         */
 109 
 110 
 111 extern inline unsigned int get_v9_pstate(void)
     /*  */
 112 {
 113         unsigned int pstate;
 114         __asm__ __volatile__("rdpr %pstate, %0\n\t" :
 115                              "=r" (pstate));
 116         return pstate;
 117 }
 118 
 119 extern inline void put_v9_pstate(unsigned int pstate)
     /*  */
 120 {
 121         __asm__ __volatile__("wrpr %0, 0x0, %pstate\n\t" : :
 122                              "r" (pstate));
 123         return;
 124 }
 125 
 126 /* The Version Register holds vendor information for the chip:
 127  *
 128  *  ---------------------------------------------------------------------------
 129  *  | manufacturer | implementation | mask | reserved | maxtl | resv | maxwin |
 130  *  |  63-48       |   47-32        | 31-24|   23-16  | 15-8  | 7-5  |  4-0   |
 131  *  ---------------------------------------------------------------------------
 132  *
 133  */
 134 
 135 #define VERS_MAXWIN  0x000000000000001f     /* 'nwindows' on this chip       */
 136 #define VERS_MAXTL   0x00000000000ff000     /* Maximum Trap-level supported  */
 137 #define VERS_MASK    0x0000000ff0000000     /* impl. dep. chip mask revision */
 138 #define VERS_MANUF   0xffff000000000000     /* Manufacturer ID code          */
 139 
 140 extern inline unsigned int get_v9_version(void)
     /*  */
 141 {
 142         unsigned int vers;
 143         __asm__ __volatile__("rdpr %ver, %0\n\t" :
 144                              "=r" (vers));
 145         return vers;
 146 }
 147 
 148 extern inline unsigned int get_v9_tstate(void)
     /*  */
 149 {
 150         unsigned int tstate;
 151         __asm__ __volatile__("rdpr %tstate, %0\n\t" :
 152                              "=r" (pstate));
 153         return tstate;
 154 }
 155 
 156 extern inline unsigned int get_v9_pil(void)
     /*  */
 157 {
 158         unsigned int pil;
 159         __asm__ __volatile__("rdpr %pil, %0\n\t" :
 160                              "=r" (pstate));
 161         return pil;
 162 }
 163 
 164 extern inline void put_v9_pil(unsigned int pil)
     /*  */
 165 {
 166         __asm__ __volatile__("wrpr %0, 0x0, %pil\n\t" : :
 167                              "r" (pil));
 168         return;
 169 }
 170 
 171 
 172 #endif /* !(__LINUX_SPARC_V9) */
 173 
 174 #endif /* !(__LINUX_SPARC_PSR_H) */
/* */
root/include/asm-sparc/psr.h

INCLUDED FROM

DEFINITIONS
