include/asm-sparc/ross.h

/* */
This source file includes following definitions.
flush_i_page
flush_i_seg
flush_i_region
flush_i_ctx
flush_i_user
flush_whole_icache
get_ross_icr
put_ross_icr
   1 /* $Id: ross.h,v 1.3 1995/11/25 02:32:37 davem Exp $
   2  * ross.h: Ross module specific definitions and defines.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _SPARC_ROSS_H
   8 #define _SPARC_ROSS_H
   9 
  10 /* Ross made Hypersparcs have a %psr 'impl' field of '0001'.  The 'vers'
  11  * field has '1111'.
  12  */
  13 
  14 /* The MMU control register fields on the HyperSparc.
  15  *
  16  * -----------------------------------------------------------------
  17  * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
  18  * -----------------------------------------------------------------
  19  *  31    24 23-22 21  20  19 18-15 14 13 12 11 10  9   8 7-2  1  0
  20  *
  21  * Phew, lots of fields there ;-)
  22  *
  23  * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
  24  * SE: Snoop Enable, turns on bus snooping for cache activity if one.
  25  * WBE: Write Buffer Enable, one turns it on.
  26  * MID: The ModuleID of the chip for MBus transactions.
  27  * BM: Boot-Mode. One indicates the MMU is in boot mode.
  28  * C: Indicates whether accesses are cachable while the MMU is
  29  *    disabled.
  30  * CS: Cache Size -- 0 = 128k, 1 = 256k
  31  * MR: Memory Reflection, one indicates that the memory bus connected
  32  *     to the MBus supports memory reflection.
  33  * CM: Cache Mode -- 0 = write-through, 1 = copy-back
  34  * CE: Cache Enable -- 0 = no caching, 1 = cache is on
  35  * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
  36  *                 1 = faults from supervisor mode do not generate traps
  37  * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
  38  */
  39 
  40 #define HYPERSPARC_CWENABLE   0x00200000
  41 #define HYPERSPARC_SBENABLE   0x00100000
  42 #define HYPERSPARC_WBENABLE   0x00080000
  43 #define HYPERSPARC_MIDMASK    0x00078000
  44 #define HYPERSPARC_BMODE      0x00004000
  45 #define HYPERSPARC_ACENABLE   0x00002000
  46 #define HYPERSPARC_CSIZE      0x00001000
  47 #define HYPERSPARC_MRFLCT     0x00000800
  48 #define HYPERSPARC_CMODE      0x00000400
  49 #define HYPERSPARC_CENABLE    0x00000100
  50 #define HYPERSPARC_NFAULT     0x00000002
  51 #define HYPERSPARC_MENABLE    0x00000001
  52 
  53 /* Flushes which clear out only the on-chip Ross HyperSparc ICACHE. */
  54 extern inline void flush_i_page(unsigned int addr)
     /*  */
  55 {
  56         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  57                              "r" (addr), "i" (ASI_M_IFLUSH_PAGE) :
  58                              "memory");
  59         return;
  60 }
  61 
  62 extern inline void flush_i_seg(unsigned int addr)
     /*  */
  63 {
  64         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  65                              "r" (addr), "i" (ASI_M_IFLUSH_SEG) :
  66                              "memory");
  67         return;
  68 }
  69 
  70 extern inline void flush_i_region(unsigned int addr)
     /*  */
  71 {
  72         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  73                              "r" (addr), "i" (ASI_M_IFLUSH_REGION) :
  74                              "memory");
  75         return;
  76 }
  77 
  78 extern inline void flush_i_ctx(unsigned int addr)
     /*  */
  79 {
  80         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  81                              "r" (addr), "i" (ASI_M_IFLUSH_CTX) :
  82                              "memory");
  83         return;
  84 }
  85 
  86 extern inline void flush_i_user(unsigned int addr)
     /*  */
  87 {
  88         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  89                              "r" (addr), "i" (ASI_M_IFLUSH_USER) :
  90                              "memory");
  91         return;
  92 }
  93 
  94 /* Finally, flush the entire ICACHE. */
  95 extern inline void flush_whole_icache(void)
     /*  */
  96 {
  97         __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
  98                              "i" (ASI_M_FLUSH_IWHOLE));
  99         return;
 100 }
 101 
 102 
 103 /* The ICCR instruction cache register on the HyperSparc.
 104  *
 105  * -----------------------------------------------
 106  * |                                 | FTD | IDC |
 107  * -----------------------------------------------
 108  *  31                                  1     0
 109  *
 110  * This register is accessed using the V8 'wrasr' and 'rdasr'
 111  * opcodes, since not all assemblers understand them and those
 112  * that do use different semantics I will just hard code the
 113  * instruction with a '.word' statement.
 114  *
 115  * FTD:  If set to one flush instructions executed during an
 116  *       instruction cache hit occurs, the corresponding line
 117  *       for said cache-hit is invalidated.  If FTD is zero,
 118  *       an unimplemented 'flush' trap will occur when any
 119  *       flush is executed by the processor.
 120  *
 121  * ICE:  If set to one, the instruction cache is enabled.  If
 122  *       zero, the cache will not be used for instruction fetches.
 123  *
 124  * All other bits are read as zeros, and writes to them have no
 125  * effect.
 126  */
 127 
 128 extern inline unsigned int get_ross_icr(void)
     /*  */
 129 {
 130         unsigned int icreg;
 131 
 132         __asm__ __volatile__(".word 0xbf402000\n\t" : /* rd %iccr, %g1 */
 133                              "=r" (icreg) : :
 134                              "g1", "memory");
 135 
 136         return icreg;
 137 }
 138 
 139 extern inline void put_ross_icr(unsigned int icreg)
     /*  */
 140 {
 141         __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
 142                              ".word 0xbf802000\n\t" /* wr %g1, 0x0, %iccr */
 143                              "nop\n\t"
 144                              "nop\n\t"
 145                              "nop\n\t" : : 
 146                              "r" (icreg) :
 147                              "g1", "memory");
 148 
 149         return;
 150 }
 151 
 152 #endif /* !(_SPARC_ROSS_H) */
/* */
root/include/asm-sparc/ross.h

INCLUDED FROM

DEFINITIONS
