This source file includes following definitions.
- pci_lookup_dev
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
1
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8
9 #include <linux/config.h>
10 #include <linux/ptrace.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/bios32.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16
17 #include <asm/page.h>
18
19 struct pci_bus pci_root;
20 struct pci_dev *pci_devices = 0;
21
22
23
24
25
26
27
28
29
30
31
32 #define DEVICE(vid,did,name) \
33 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
34
35 #define BRIDGE(vid,did,name,bridge) \
36 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
37
38
39
40
41
42
43 struct pci_dev_info dev_info[] = {
44 DEVICE( COMPAQ, COMPAQ_1280, "QVision 1280/p"),
45 DEVICE( NCR, NCR_53C810, "53c810"),
46 DEVICE( NCR, NCR_53C820, "53c820"),
47 DEVICE( NCR, NCR_53C825, "53c825"),
48 DEVICE( NCR, NCR_53C815, "53c815"),
49 DEVICE( ATI, ATI_68800, "68800AX"),
50 DEVICE( ATI, ATI_215CT222, "215CT222"),
51 DEVICE( ATI, ATI_210888CX, "210888CX"),
52 DEVICE( ATI, ATI_210888GX, "210888GX"),
53 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
54 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
55 DEVICE( ADL, ADL_2301, "2301"),
56 DEVICE( NS, NS_87410, "87410"),
57 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
58 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
59 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
60 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
61 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
62 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
63 BRIDGE( DEC, DEC_BRD, "DC21050", 0x00),
64 DEVICE( DEC, DEC_TULIP, "DC21040"),
65 DEVICE( DEC, DEC_TGA, "DC21030"),
66 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
67 DEVICE( DEC, DEC_FDDI, "DEFPA"),
68 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
69 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
70 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
71 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
72 DEVICE( CIRRUS, CIRRUS_5436, "GD 5436"),
73 DEVICE( CIRRUS, CIRRUS_6205, "GD 6205"),
74 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
75 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
76 DEVICE( CIRRUS, CIRRUS_7543, "CL 7543"),
77 DEVICE( WD, WD_7197, "WD 7197"),
78 DEVICE( AMD, AMD_LANCE, "79C970"),
79 DEVICE( AMD, AMD_SCSI, "53C974"),
80 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
81 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
82 DEVICE( TRIDENT, TRIDENT_9660, "TG 9660"),
83 DEVICE( AI, AI_M1435, "M1435"),
84 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
85 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
86 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
87 DEVICE( CT, CT_65545, "65545"),
88 DEVICE( FD, FD_36C70, "TMC-18C30"),
89 DEVICE( SI, SI_6201, "6201"),
90 DEVICE( SI, SI_6202, "6202"),
91 DEVICE( SI, SI_503, "85C503"),
92 DEVICE( SI, SI_501, "85C501"),
93 DEVICE( SI, SI_496, "85C496"),
94 DEVICE( SI, SI_601, "85C601"),
95 DEVICE( SI, SI_5511, "85C5511"),
96 DEVICE( SI, SI_5513, "85C5513"),
97 DEVICE( HP, HP_J2585A, "J2585A"),
98 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
99 DEVICE( DPT, DPT, "SmartCache/Raid"),
100 DEVICE( OPTI, OPTI_82C557, "82C557"),
101 DEVICE( OPTI, OPTI_82C558, "82C558"),
102 DEVICE( OPTI, OPTI_82C621, "82C621"),
103 DEVICE( OPTI, OPTI_82C822, "82C822"),
104 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"BT-946C"),
105 DEVICE( BUSLOGIC, BUSLOGIC_946C, "BT-946C"),
106 DEVICE( BUSLOGIC, BUSLOGIC_930, "BT-930"),
107 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
108 DEVICE( N9, N9_I128, "Imagine 128"),
109 DEVICE( N9, N9_I128_2, "Imagine 128v2"),
110 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
111 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
112 DEVICE( UMC, UMC_UM8886BF, "UM8886BF"),
113 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
114 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
115 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
116 DEVICE( UMC, UMC_UM9017F, "UM9017F"),
117 DEVICE( UMC, UMC_UM8886N, "UM8886N"),
118 DEVICE( UMC, UMC_UM8891N, "UM8891N"),
119 DEVICE( X, X_AGX016, "ITT AGX016"),
120 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
121 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
122 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
123 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
124 DEVICE( CMD, CMD_640, "640 (buggy)"),
125 DEVICE( CMD, CMD_646, "646"),
126 DEVICE( VISION, VISION_QD8500, "QD-8500"),
127 DEVICE( VISION, VISION_QD8580, "QD-8580"),
128 DEVICE( SIERRA, SIERRA_STB, "STB Horizon 64"),
129 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
130 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
131 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
132 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
133 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
134 DEVICE( AL, AL_M1445, "M1445"),
135 DEVICE( AL, AL_M1449, "M1449"),
136 DEVICE( AL, AL_M1451, "M1451"),
137 DEVICE( AL, AL_M1461, "M1461"),
138 DEVICE( AL, AL_M1489, "M1489"),
139 DEVICE( AL, AL_M4803, "M4803"),
140 DEVICE( ASP, ASP_ABP940, "ABP940"),
141 DEVICE( IMS, IMS_8849, "8849"),
142 DEVICE( TEKRAM2, TEKRAM2_690c, "DC690c"),
143 DEVICE( INTERG, INTERG_1680, "IGA-1680"),
144 DEVICE( REALTEK, REALTEK_8029, "8029"),
145 DEVICE( INIT, INIT_320P, "320 P"),
146 DEVICE( VIA, VIA_82C505, "VT 82C505"),
147 DEVICE( VIA, VIA_82C561, "VT 82C561"),
148 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
149 DEVICE( VIA, VIA_82C416, "VT 82C416MV"),
150 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
151 DEVICE( EF, EF_ATM_FPGA, "155P-MF1 (FPGA)"),
152 DEVICE( EF, EF_ATM_ASIC, "155P-MF1 (ASIC)"),
153 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
154 DEVICE( FORE, FORE_PCA200PC, "PCA-200PC"),
155 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge"),
156 DEVICE( ALLIANCE, ALLIANCE_PROMOTIO, "Promotion-6410"),
157 DEVICE( ALLIANCE, ALLIANCE_PROVIDEO, "Provideo"),
158 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
159 DEVICE( ZEITNET, ZEITNET_1221, "1221"),
160 DEVICE( SPECIALIX, SPECIALIX_XIO, "XIO/SIO host"),
161 DEVICE( SPECIALIX, SPECIALIX_RIO, "RIO host"),
162 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
163 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
164 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
165 DEVICE( AVANCE, AVANCE_2302, "ALG-2302"),
166 DEVICE( S3, S3_811, "Trio32/Trio64"),
167 DEVICE( S3, S3_868, "Vision 868"),
168 DEVICE( S3, S3_928, "Vision 928-P"),
169 DEVICE( S3, S3_864_1, "Vision 864-P"),
170 DEVICE( S3, S3_864_2, "Vision 864-P"),
171 DEVICE( S3, S3_964_1, "Vision 964-P"),
172 DEVICE( S3, S3_964_2, "Vision 964-P"),
173 DEVICE( S3, S3_968, "Vision 968"),
174 DEVICE( INTEL, INTEL_82375, "82375EB"),
175 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
176 DEVICE( INTEL, INTEL_82378, "82378IB"),
177 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
178 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
179 DEVICE( INTEL, INTEL_7116, "SAA7116"),
180 DEVICE( INTEL, INTEL_82596, "82596"),
181 DEVICE( INTEL, INTEL_82865, "82865"),
182 DEVICE( INTEL, INTEL_82557, "82557"),
183 DEVICE( INTEL, INTEL_82437, "82437"),
184 DEVICE( INTEL, INTEL_82371_0, "82371 Triton PIIX"),
185 DEVICE( INTEL, INTEL_82371_1, "82371 Triton PIIX"),
186 DEVICE( INTEL, INTEL_P6, "Orion P6"),
187 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
188 DEVICE( ADAPTEC, ADAPTEC_7870, "AIC-7870"),
189 DEVICE( ADAPTEC, ADAPTEC_7871, "AIC-7871"),
190 DEVICE( ADAPTEC, ADAPTEC_7872, "AIC-7872"),
191 DEVICE( ADAPTEC, ADAPTEC_7873, "AIC-7873"),
192 DEVICE( ADAPTEC, ADAPTEC_7874, "AIC-7874"),
193 DEVICE( ADAPTEC, ADAPTEC_7880, "AIC-7880U"),
194 DEVICE( ADAPTEC, ADAPTEC_7881, "AIC-7881U"),
195 DEVICE( ADAPTEC, ADAPTEC_7882, "AIC-7882U"),
196 DEVICE( ADAPTEC, ADAPTEC_7883, "AIC-7883U"),
197 DEVICE( ADAPTEC, ADAPTEC_7884, "AIC-7884U"),
198 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
199 DEVICE( HER, HER_STING, "Stingray"),
200 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV")
201 };
202
203
204 #ifdef CONFIG_PCI_OPTIMIZE
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221 struct optimization_type {
222 const char *type;
223 const char *off;
224 const char *on;
225 } bridge_optimization[] = {
226 {"Cache L2", "write through", "write back"},
227 {"CPU-PCI posted write", "off", "on"},
228 {"CPU-Memory posted write", "off", "on"},
229 {"PCI-Memory posted write", "off", "on"},
230 {"PCI burst", "off", "on"}
231 };
232
233 #define NUM_OPTIMIZATIONS \
234 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
235
236 struct bridge_mapping_type {
237 unsigned char addr;
238 unsigned char mask;
239 unsigned char value;
240 } bridge_mapping[] = {
241
242
243
244
245
246
247
248 {0x0 ,0x02 ,0x02 },
249 {0x53 ,0x02 ,0x02 },
250 {0x53 ,0x01 ,0x01 },
251 {0x54 ,0x01 ,0x01 },
252 {0x54 ,0x02 ,0x02 },
253
254
255
256
257
258 {0x50 ,0x10 ,0x00 },
259 {0x51 ,0x40 ,0x40 },
260 {0x0 ,0x0 ,0x0 },
261 {0x0 ,0x0 ,0x0 },
262 {0x0 ,0x0 ,0x0 },
263
264
265
266
267
268
269 {0x0 ,0x1 ,0x1 },
270 {0x0 ,0x2 ,0x0 },
271 {0x0 ,0x0 ,0x0 },
272 {0x0 ,0x0 ,0x0 },
273 {0x0 ,0x0 ,0x0 }
274 };
275
276 #endif
277
278
279
280
281
282 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
283 {
284 int min = 0,
285 max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
286
287 for ( ; ; )
288 {
289 int i = (min + max) >> 1;
290 long order;
291
292 order = dev_info[i].vendor - (long) vendor;
293 if (!order)
294 order = dev_info[i].device - (long) dev;
295
296 if (order < 0)
297 {
298 min = i + 1;
299 if ( min > max )
300 return 0;
301 continue;
302 }
303
304 if (order > 0)
305 {
306 max = i - 1;
307 if ( min > max )
308 return 0;
309 continue;
310 }
311
312 return & dev_info[ i ];
313 }
314 }
315
316 const char *pci_strclass (unsigned int class)
317 {
318 switch (class >> 8) {
319 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
320 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
321
322 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
323 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
324 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
325 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
326 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
327 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
328
329 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
330 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
331 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
332 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
333 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
334
335 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
336 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
337 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
338
339 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
340 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
341 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
342
343 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
344 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
345 case PCI_CLASS_MEMORY_OTHER: return "Memory";
346
347 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
348 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
349 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
350 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
351 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
352 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
353 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
354 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
355 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
356
357 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
358 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
359 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
360
361 case PCI_CLASS_SYSTEM_PIC: return "PIC";
362 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
363 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
364 case PCI_CLASS_SYSTEM_RTC: return "RTC";
365 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
366
367 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
368 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
369 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
370 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
371
372 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
373 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
374
375 case PCI_CLASS_PROCESSOR_386: return "386";
376 case PCI_CLASS_PROCESSOR_486: return "486";
377 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
378 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
379 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
380 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
381
382 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
383 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
384 case PCI_CLASS_SERIAL_SSA: return "SSA";
385 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
386
387 default: return "Unknown class";
388 }
389 }
390
391
392 const char *pci_strvendor(unsigned int vendor)
393 {
394 switch (vendor) {
395 case PCI_VENDOR_ID_COMPAQ: return "Compaq";
396 case PCI_VENDOR_ID_NCR: return "NCR";
397 case PCI_VENDOR_ID_ATI: return "ATI";
398 case PCI_VENDOR_ID_VLSI: return "VLSI";
399 case PCI_VENDOR_ID_ADL: return "Advance Logic";
400 case PCI_VENDOR_ID_NS: return "NS";
401 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
402 case PCI_VENDOR_ID_WEITEK: return "Weitek";
403 case PCI_VENDOR_ID_DEC: return "DEC";
404 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
405 case PCI_VENDOR_ID_IBM: return "IBM";
406 case PCI_VENDOR_ID_WD: return "Western Digital";
407 case PCI_VENDOR_ID_AMD: return "AMD";
408 case PCI_VENDOR_ID_TRIDENT: return "Trident";
409 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
410 case PCI_VENDOR_ID_MATROX: return "Matrox";
411 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
412 case PCI_VENDOR_ID_FD: return "Future Domain";
413 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
414 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
415 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
416 case PCI_VENDOR_ID_DPT: return "DPT";
417 case PCI_VENDOR_ID_OPTI: return "OPTI";
418 case PCI_VENDOR_ID_SGS: return "SGS Thomson";
419 case PCI_VENDOR_ID_BUSLOGIC: return "BusLogic";
420 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
421 case PCI_VENDOR_ID_N9: return "Number Nine";
422 case PCI_VENDOR_ID_UMC: return "UMC";
423 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
424 case PCI_VENDOR_ID_NEXGEN: return "Nexgen";
425 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
426 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
427 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
428 case PCI_VENDOR_ID_FOREX: return "Forex";
429 case PCI_VENDOR_ID_OLICOM: return "Olicom";
430 case PCI_VENDOR_ID_CMD: return "CMD";
431 case PCI_VENDOR_ID_VISION: return "Vision";
432 case PCI_VENDOR_ID_SIERRA: return "Sierra";
433 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
434 case PCI_VENDOR_ID_WINBOND: return "Winbond";
435 case PCI_VENDOR_ID_3COM: return "3Com";
436 case PCI_VENDOR_ID_AL: return "Acer Labs";
437 case PCI_VENDOR_ID_ASP: return "Advanced System Products";
438 case PCI_VENDOR_ID_IMS: return "IMS";
439 case PCI_VENDOR_ID_TEKRAM2: return "Tekram";
440 case PCI_VENDOR_ID_AMCC: return "AMCC";
441 case PCI_VENDOR_ID_INTERG: return "Intergraphics";
442 case PCI_VENDOR_ID_REALTEK: return "Realtek";
443 case PCI_VENDOR_ID_INIT: return "Initio Corp";
444 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
445 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
446 case PCI_VENDOR_ID_EF: return "Efficient Networks";
447 case PCI_VENDOR_ID_FORE: return "Fore Systems";
448 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
449 case PCI_VENDOR_ID_PLX: return "PLX";
450 case PCI_VENDOR_ID_ALLIANCE: return "Alliance";
451 case PCI_VENDOR_ID_MUTECH: return "Mutech";
452 case PCI_VENDOR_ID_ZEITNET: return "ZeitNet";
453 case PCI_VENDOR_ID_SPECIALIX: return "Specialix";
454 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
455 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
456 case PCI_VENDOR_ID_TEKRAM: return "Tekram";
457 case PCI_VENDOR_ID_AVANCE: return "Avance";
458 case PCI_VENDOR_ID_S3: return "S3 Inc.";
459 case PCI_VENDOR_ID_INTEL: return "Intel";
460 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
461 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
462 case PCI_VENDOR_ID_HER: return "Hercules";
463 default: return "Unknown vendor";
464 }
465 }
466
467
468 const char *pci_strdev(unsigned int vendor, unsigned int device)
469 {
470 struct pci_dev_info *info;
471
472 info = pci_lookup_dev(vendor, device);
473 return info ? info->name : "Unknown device";
474 }
475
476
477
478
479
480
481 static void burst_bridge(unsigned char bus, unsigned char devfn,
482 unsigned char pos, int turn_on)
483 {
484 #ifdef CONFIG_PCI_OPTIMIZE
485 struct bridge_mapping_type *bmap;
486 unsigned char val;
487 int i;
488
489 pos *= NUM_OPTIMIZATIONS;
490 printk("PCI bridge optimization.\n");
491 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
492 printk(" %s: ", bridge_optimization[i].type);
493 bmap = &bridge_mapping[pos + i];
494 if (!bmap->addr) {
495 printk("Not supported.");
496 } else {
497 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
498 if ((val & bmap->mask) == bmap->value) {
499 printk("%s.", bridge_optimization[i].on);
500 if (!turn_on) {
501 pcibios_write_config_byte(bus, devfn,
502 bmap->addr,
503 (val | bmap->mask)
504 - bmap->value);
505 printk("Changed! Now %s.", bridge_optimization[i].off);
506 }
507 } else {
508 printk("%s.", bridge_optimization[i].off);
509 if (turn_on) {
510 pcibios_write_config_byte(bus, devfn,
511 bmap->addr,
512 (val & (0xff - bmap->mask))
513 + bmap->value);
514 printk("Changed! Now %s.", bridge_optimization[i].on);
515 }
516 }
517 }
518 printk("\n");
519 }
520 #endif
521 }
522
523
524
525
526
527
528
529
530 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
531 {
532 unsigned long base;
533 unsigned int l, class_rev, bus, devfn;
534 unsigned short vendor, device, status;
535 unsigned char bist, latency, min_gnt, max_lat;
536 int reg, len = 0;
537 const char *str;
538
539 bus = dev->bus->number;
540 devfn = dev->devfn;
541
542 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
543 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
544 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
545 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
546 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
547 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
548 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
549 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
550 if (len + 80 > size) {
551 return -1;
552 }
553 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
554 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
555
556 if (len + 80 > size) {
557 return -1;
558 }
559 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
560 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
561 pci_strdev(vendor, device), class_rev & 0xff);
562
563 if (!pci_lookup_dev(vendor, device)) {
564 len += sprintf(buf + len,
565 "Vendor id=%x. Device id=%x.\n ",
566 vendor, device);
567 }
568
569 str = 0;
570 switch (status & PCI_STATUS_DEVSEL_MASK) {
571 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
572 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
573 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
574 }
575 if (len + strlen(str) > size) {
576 return -1;
577 }
578 len += sprintf(buf + len, str);
579
580 if (status & PCI_STATUS_FAST_BACK) {
581 # define fast_b2b_capable "Fast back-to-back capable. "
582 if (len + strlen(fast_b2b_capable) > size) {
583 return -1;
584 }
585 len += sprintf(buf + len, fast_b2b_capable);
586 # undef fast_b2b_capable
587 }
588
589 if (bist & PCI_BIST_CAPABLE) {
590 # define BIST_capable "BIST capable. "
591 if (len + strlen(BIST_capable) > size) {
592 return -1;
593 }
594 len += sprintf(buf + len, BIST_capable);
595 # undef BIST_capable
596 }
597
598 if (dev->irq) {
599 if (len + 40 > size) {
600 return -1;
601 }
602 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
603 }
604
605 if (dev->master) {
606 if (len + 80 > size) {
607 return -1;
608 }
609 len += sprintf(buf + len, "Master Capable. ");
610 if (latency)
611 len += sprintf(buf + len, "Latency=%d. ", latency);
612 else
613 len += sprintf(buf + len, "No bursts. ");
614 if (min_gnt)
615 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
616 if (max_lat)
617 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
618 }
619
620 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
621 if (len + 40 > size) {
622 return -1;
623 }
624 pcibios_read_config_dword(bus, devfn, reg, &l);
625 base = l;
626 if (!base) {
627 continue;
628 }
629
630 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
631 len += sprintf(buf + len,
632 "\n I/O at 0x%lx.",
633 base & PCI_BASE_ADDRESS_IO_MASK);
634 } else {
635 const char *pref, *type = "unknown";
636
637 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
638 pref = "P";
639 } else {
640 pref = "Non-p";
641 }
642 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
643 case PCI_BASE_ADDRESS_MEM_TYPE_32:
644 type = "32 bit"; break;
645 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
646 type = "20 bit"; break;
647 case PCI_BASE_ADDRESS_MEM_TYPE_64:
648 type = "64 bit";
649
650 reg += 4;
651 pcibios_read_config_dword(bus, devfn, reg, &l);
652 base |= ((u64) l) << 32;
653 break;
654 }
655 len += sprintf(buf + len,
656 "\n %srefetchable %s memory at "
657 "0x%lx.", pref, type,
658 base & PCI_BASE_ADDRESS_MEM_MASK);
659 }
660 }
661
662 len += sprintf(buf + len, "\n");
663 return len;
664 }
665
666
667
668
669
670
671 int get_pci_list(char *buf)
672 {
673 int nprinted, len, size;
674 struct pci_dev *dev;
675 # define MSG "\nwarning: page-size limit reached!\n"
676
677
678 size = PAGE_SIZE - (strlen(MSG) + 1);
679 len = sprintf(buf, "PCI devices found:\n");
680
681 for (dev = pci_devices; dev; dev = dev->next) {
682 nprinted = sprint_dev_config(dev, buf + len, size - len);
683 if (nprinted < 0) {
684 return len + sprintf(buf + len, MSG);
685 }
686 len += nprinted;
687 }
688 return len;
689 }
690
691
692
693
694
695
696 static void *pci_malloc(long size, unsigned long *mem_startp)
697 {
698 void *mem;
699
700 #ifdef DEBUG
701 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
702 #endif
703 mem = (void*) *mem_startp;
704 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
705 memset(mem, 0, size);
706 return mem;
707 }
708
709
710 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
711 {
712 unsigned int devfn, l, max;
713 unsigned char cmd, tmp, hdr_type = 0;
714 struct pci_dev_info *info;
715 struct pci_dev *dev;
716 struct pci_bus *child;
717
718 #ifdef DEBUG
719 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
720 #endif
721
722 max = bus->secondary;
723 for (devfn = 0; devfn < 0xff; ++devfn) {
724 if (PCI_FUNC(devfn) == 0) {
725 pcibios_read_config_byte(bus->number, devfn,
726 PCI_HEADER_TYPE, &hdr_type);
727 } else if (!(hdr_type & 0x80)) {
728
729 continue;
730 }
731
732 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
733 &l);
734
735 if (l == 0xffffffff || l == 0x00000000) {
736 hdr_type = 0;
737 continue;
738 }
739
740 dev = pci_malloc(sizeof(*dev), mem_startp);
741 dev->bus = bus;
742
743
744
745
746
747 dev->next = pci_devices;
748 pci_devices = dev;
749
750 dev->devfn = devfn;
751 dev->vendor = l & 0xffff;
752 dev->device = (l >> 16) & 0xffff;
753
754
755
756
757
758
759 info = pci_lookup_dev(dev->vendor, dev->device);
760 if (!info) {
761 printk("Warning : Unknown PCI device (%x:%x). Please read include/linux/pci.h \n",
762 dev->vendor, dev->device);
763 } else {
764
765 if (info->bridge_type != 0xff) {
766 burst_bridge(bus->number, devfn,
767 info->bridge_type, 1);
768 }
769 }
770
771
772 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
773 &cmd);
774 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
775 cmd | PCI_COMMAND_MASTER);
776 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
777 &tmp);
778 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
779 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
780 cmd);
781
782
783 pcibios_read_config_byte(bus->number, devfn,
784 PCI_INTERRUPT_LINE, &dev->irq);
785
786
787 pcibios_read_config_dword(bus->number, devfn,
788 PCI_CLASS_REVISION, &l);
789 l = l >> 8;
790 dev->class = l;
791
792
793
794
795 dev->sibling = bus->devices;
796 bus->devices = dev;
797
798 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
799 unsigned int buses;
800 unsigned short cr;
801
802
803
804
805 child = pci_malloc(sizeof(*child), mem_startp);
806 child->next = bus->children;
807 bus->children = child;
808 child->self = dev;
809 child->parent = bus;
810
811
812
813
814
815 child->number = child->secondary = ++max;
816 child->primary = bus->secondary;
817 child->subordinate = 0xff;
818
819
820
821
822 pcibios_read_config_word(bus->number, devfn,
823 PCI_COMMAND, &cr);
824 pcibios_write_config_word(bus->number, devfn,
825 PCI_COMMAND, 0x0000);
826 pcibios_write_config_word(bus->number, devfn,
827 PCI_STATUS, 0xffff);
828
829
830
831 pcibios_read_config_dword(bus->number, devfn, 0x18,
832 &buses);
833 buses &= 0xff000000;
834 buses |= (((unsigned int)(child->primary) << 0) |
835 ((unsigned int)(child->secondary) << 8) |
836 ((unsigned int)(child->subordinate) << 16));
837 pcibios_write_config_dword(bus->number, devfn, 0x18,
838 buses);
839
840
841
842 max = scan_bus(child, mem_startp);
843
844
845
846
847 child->subordinate = max;
848 buses = (buses & 0xff00ffff)
849 | ((unsigned int)(child->subordinate) << 16);
850 pcibios_write_config_dword(bus->number, devfn, 0x18,
851 buses);
852 pcibios_write_config_word(bus->number, devfn,
853 PCI_COMMAND, cr);
854 }
855 }
856
857
858
859
860
861
862
863 return max;
864 }
865
866
867 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
868 {
869 mem_start = pcibios_init(mem_start, mem_end);
870
871 if (!pcibios_present()) {
872 printk("pci_init: no BIOS32 detected\n");
873 return mem_start;
874 }
875
876 printk("Probing PCI hardware.\n");
877
878 memset(&pci_root, 0, sizeof(pci_root));
879 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
880
881
882 mem_start = pcibios_fixup(mem_start, mem_end);
883
884 #ifdef DEBUG
885 {
886 int len = get_pci_list((char*)mem_start);
887 if (len) {
888 ((char *) mem_start)[len] = '\0';
889 printk("%s\n", (char *) mem_start);
890 }
891 }
892 #endif
893 return mem_start;
894 }