drivers/sound/ad1848.c

/* */
This source file includes following definitions.
ad_read
ad_write
wait_for_calibration
ad_mute
ad_unmute
ad_enter_MCE
ad_leave_MCE
ad1848_set_recmask
change_bits
ad1848_mixer_get
ad1848_mixer_set
ad1848_mixer_reset
ad1848_mixer_ioctl
ad1848_open
ad1848_close
set_speed
set_channels
set_format
ad1848_ioctl
ad1848_output_block
ad1848_start_input
ad1848_prepare_for_IO
ad1848_reset
ad1848_halt
ad1848_halt_input
ad1848_halt_output
ad1848_trigger
ad1848_detect
ad1848_init
ad1848_unload
ad1848_interrupt
check_opl3
probe_ms_sound
attach_ms_sound
unload_ms_sound
probe_pnp_ad1848
attach_pnp_ad1848
unload_pnp_ad1848
ad1848_tmr_start
ad1848_tmr_reprogram
ad1848_tmr_disable
ad1848_tmr_restart
ad1848_tmr_install
   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  */
  16 
  17 /*
  18  * Copyright by Hannu Savolainen 1993-1996
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are
  22  * met: 1. Redistributions of source code must retain the above copyright
  23  * notice, this list of conditions and the following disclaimer. 2.
  24  * Redistributions in binary form must reproduce the above copyright notice,
  25  * this list of conditions and the following disclaimer in the documentation
  26  * and/or other materials provided with the distribution.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  29  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  30  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  32  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  */
  40 #include <linux/config.h>
  41 
  42 
  43 #define DEB(x)
  44 #define DEB1(x)
  45 #include "sound_config.h"
  46 
  47 #if defined(CONFIG_AD1848)
  48 
  49 #include "ad1848_mixer.h"
  50 
  51 typedef struct
  52   {
  53     int             base;
  54     int             irq;
  55     int             dual_dma;   /* 1, when two DMA channels allocated */
  56     unsigned char   MCE_bit;
  57     unsigned char   saved_regs[16];
  58 
  59     int             speed;
  60     unsigned char   speed_bits;
  61     int             channels;
  62     int             audio_format;
  63     unsigned char   format_bits;
  64 
  65     int             xfer_count;
  66     int             irq_mode;
  67     int             intr_active;
  68     int             opened;
  69     char           *chip_name;
  70     int             mode;
  71 #define MD_1848         1
  72 #define MD_4231         2
  73 #define MD_4231A        3
  74 #define MD_1845         4
  75 #define MD_4232         5
  76 
  77     /* Mixer parameters */
  78     int             recmask;
  79     int             supported_devices;
  80     int             supported_rec_devices;
  81     unsigned short  levels[32];
  82     int             dev_no;
  83     volatile unsigned long timer_ticks;
  84     int             timer_running;
  85     int             irq_ok;
  86     int            *osp;
  87   }
  88 
  89 ad1848_info;
  90 
  91 static int      nr_ad1848_devs = 0;
  92 static volatile char irq2dev[17] =
  93 {-1, -1, -1, -1, -1, -1, -1, -1,
  94  -1, -1, -1, -1, -1, -1, -1, -1, -1};
  95 
  96 static int      timer_installed = -1;
  97 
  98 static char     mixer2codec[MAX_MIXER_DEV] =
  99 {0};
 100 
 101 static int      ad_format_mask[6 /*devc->mode */ ] =
 102 {
 103   0,
 104   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 105   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 106   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 107   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,     /* AD1845 */
 108   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM
 109 };
 110 
 111 static ad1848_info dev_info[MAX_AUDIO_DEV];
 112 
 113 #define io_Index_Addr(d)        ((d)->base)
 114 #define io_Indexed_Data(d)      ((d)->base+1)
 115 #define io_Status(d)            ((d)->base+2)
 116 #define io_Polled_IO(d)         ((d)->base+3)
 117 
 118 static int      ad1848_open (int dev, int mode);
 119 static void     ad1848_close (int dev);
 120 static int      ad1848_ioctl (int dev, unsigned int cmd, caddr_t arg, int local);
 121 static void     ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 122 static void     ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 123 static int      ad1848_prepare_for_IO (int dev, int bsize, int bcount);
 124 static void     ad1848_reset (int dev);
 125 static void     ad1848_halt (int dev);
 126 static void     ad1848_halt_input (int dev);
 127 static void     ad1848_halt_output (int dev);
 128 static void     ad1848_trigger (int dev, int bits);
 129 static int      ad1848_tmr_install (int dev);
 130 static void     ad1848_tmr_reprogram (int dev);
 131 
 132 static int
 133 ad_read (ad1848_info * devc, int reg)
     /*  */
 134 {
 135   unsigned long   flags;
 136   int             x;
 137   int             timeout = 900000;
 138 
 139   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 140     timeout--;
 141 
 142   save_flags (flags);
 143   cli ();
 144   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 145   x = inb (io_Indexed_Data (devc));
 146   /*  printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
 147   restore_flags (flags);
 148 
 149   return x;
 150 }
 151 
 152 static void
 153 ad_write (ad1848_info * devc, int reg, int data)
     /*  */
 154 {
 155   unsigned long   flags;
 156   int             timeout = 90000;
 157 
 158   while (timeout > 0 &&
 159          inb (devc->base) == 0x80)      /*Are we initializing */
 160     timeout--;
 161 
 162   save_flags (flags);
 163   cli ();
 164   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 165   outb ((unsigned char) (data & 0xff), io_Indexed_Data (devc));
 166   /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
 167   restore_flags (flags);
 168 }
 169 
 170 static void
 171 wait_for_calibration (ad1848_info * devc)
     /*  */
 172 {
 173   int             timeout = 0;
 174 
 175   /*
 176      * Wait until the auto calibration process has finished.
 177      *
 178      * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 179      * 2)       Wait until the ACI bit of I11 gets on and then off.
 180    */
 181 
 182   timeout = 100000;
 183   while (timeout > 0 && inb (devc->base) & 0x80)
 184     timeout--;
 185   if (inb (devc->base) & 0x80)
 186     printk ("ad1848: Auto calibration timed out(1).\n");
 187 
 188   timeout = 100;
 189   while (timeout > 0 && !(ad_read (devc, 11) & 0x20))
 190     timeout--;
 191   if (!(ad_read (devc, 11) & 0x20))
 192     return;
 193 
 194   timeout = 20000;
 195   while (timeout > 0 && ad_read (devc, 11) & 0x20)
 196     timeout--;
 197   if (ad_read (devc, 11) & 0x20)
 198     printk ("ad1848: Auto calibration timed out(3).\n");
 199 }
 200 
 201 static void
 202 ad_mute (ad1848_info * devc)
     /*  */
 203 {
 204   int             i;
 205   unsigned char   prev;
 206 
 207   /*
 208      * Save old register settings and mute output channels
 209    */
 210   for (i = 6; i < 8; i++)
 211     {
 212       prev = devc->saved_regs[i] = ad_read (devc, i);
 213       ad_write (devc, i, prev | 0x80);
 214     }
 215 }
 216 
 217 static void
 218 ad_unmute (ad1848_info * devc)
     /*  */
 219 {
 220   int             i;
 221 
 222   /*
 223      * Restore back old volume registers (unmute)
 224    */
 225   for (i = 6; i < 8; i++)
 226     {
 227       ad_write (devc, i, devc->saved_regs[i] & ~0x80);
 228     }
 229 }
 230 
 231 static void
 232 ad_enter_MCE (ad1848_info * devc)
     /*  */
 233 {
 234   unsigned long   flags;
 235   int             timeout = 1000;
 236   unsigned short  prev;
 237 
 238   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 239     timeout--;
 240 
 241   save_flags (flags);
 242   cli ();
 243 
 244   devc->MCE_bit = 0x40;
 245   prev = inb (io_Index_Addr (devc));
 246   if (prev & 0x40)
 247     {
 248       restore_flags (flags);
 249       return;
 250     }
 251 
 252   outb (devc->MCE_bit, io_Index_Addr (devc));
 253   restore_flags (flags);
 254 }
 255 
 256 static void
 257 ad_leave_MCE (ad1848_info * devc)
     /*  */
 258 {
 259   unsigned long   flags;
 260   unsigned char   prev;
 261   int             timeout = 1000;
 262 
 263   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 264     timeout--;
 265 
 266   save_flags (flags);
 267   cli ();
 268 
 269   devc->MCE_bit = 0x00;
 270   prev = inb (io_Index_Addr (devc));
 271   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 272 
 273   if ((prev & 0x40) == 0)       /* Not in MCE mode */
 274     {
 275       restore_flags (flags);
 276       return;
 277     }
 278 
 279   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 280   wait_for_calibration (devc);
 281   restore_flags (flags);
 282 }
 283 
 284 
 285 static int
 286 ad1848_set_recmask (ad1848_info * devc, int mask)
     /*  */
 287 {
 288   unsigned char   recdev;
 289   int             i, n;
 290 
 291   mask &= devc->supported_rec_devices;
 292 
 293   n = 0;
 294   for (i = 0; i < 32; i++)      /* Count selected device bits */
 295     if (mask & (1 << i))
 296       n++;
 297 
 298   if (n == 0)
 299     mask = SOUND_MASK_MIC;
 300   else if (n != 1)              /* Too many devices selected */
 301     {
 302       mask &= ~devc->recmask;   /* Filter out active settings */
 303 
 304       n = 0;
 305       for (i = 0; i < 32; i++)  /* Count selected device bits */
 306         if (mask & (1 << i))
 307           n++;
 308 
 309       if (n != 1)
 310         mask = SOUND_MASK_MIC;
 311     }
 312 
 313   switch (mask)
 314     {
 315     case SOUND_MASK_MIC:
 316       recdev = 2;
 317       break;
 318 
 319     case SOUND_MASK_LINE:
 320     case SOUND_MASK_LINE3:
 321       recdev = 0;
 322       break;
 323 
 324     case SOUND_MASK_CD:
 325     case SOUND_MASK_LINE1:
 326       recdev = 1;
 327       break;
 328 
 329     case SOUND_MASK_IMIX:
 330       recdev = 3;
 331       break;
 332 
 333     default:
 334       mask = SOUND_MASK_MIC;
 335       recdev = 2;
 336     }
 337 
 338   recdev <<= 6;
 339   ad_write (devc, 0, (ad_read (devc, 0) & 0x3f) | recdev);
 340   ad_write (devc, 1, (ad_read (devc, 1) & 0x3f) | recdev);
 341 
 342   devc->recmask = mask;
 343   return mask;
 344 }
 345 
 346 static void
 347 change_bits (unsigned char *regval, int dev, int chn, int newval)
     /*  */
 348 {
 349   unsigned char   mask;
 350   int             shift;
 351 
 352   if (mix_devices[dev][chn].polarity == 1)      /* Reverse */
 353     newval = 100 - newval;
 354 
 355   mask = (1 << mix_devices[dev][chn].nbits) - 1;
 356   shift = mix_devices[dev][chn].bitpos;
 357   newval = (int) ((newval * mask) + 50) / 100;  /* Scale it */
 358 
 359   *regval &= ~(mask << shift);  /* Clear bits */
 360   *regval |= (newval & mask) << shift;  /* Set new value */
 361 }
 362 
 363 static int
 364 ad1848_mixer_get (ad1848_info * devc, int dev)
     /*  */
 365 {
 366   if (!((1 << dev) & devc->supported_devices))
 367     return -EINVAL;
 368 
 369   return devc->levels[dev];
 370 }
 371 
 372 static int
 373 ad1848_mixer_set (ad1848_info * devc, int dev, int value)
     /*  */
 374 {
 375   int             left = value & 0x000000ff;
 376   int             right = (value & 0x0000ff00) >> 8;
 377   int             retvol;
 378 
 379   int             regoffs;
 380   unsigned char   val;
 381 
 382   if (left > 100)
 383     left = 100;
 384   if (right > 100)
 385     right = 100;
 386 
 387   if (mix_devices[dev][RIGHT_CHN].nbits == 0)   /* Mono control */
 388     right = left;
 389 
 390   retvol = left | (left << 8);
 391 
 392   /* Scale volumes */
 393   left = mix_cvt[left];
 394   right = mix_cvt[right];
 395 
 396   /* Scale it again */
 397   left = mix_cvt[left];
 398   right = mix_cvt[right];
 399 
 400   if (dev > 31)
 401     return -EINVAL;
 402 
 403   if (!(devc->supported_devices & (1 << dev)))
 404     return -EINVAL;
 405 
 406   if (mix_devices[dev][LEFT_CHN].nbits == 0)
 407     return -EINVAL;
 408 
 409   devc->levels[dev] = retvol;
 410 
 411   /*
 412      * Set the left channel
 413    */
 414 
 415   regoffs = mix_devices[dev][LEFT_CHN].regno;
 416   val = ad_read (devc, regoffs);
 417   change_bits (&val, dev, LEFT_CHN, left);
 418   ad_write (devc, regoffs, val);
 419   devc->saved_regs[regoffs] = val;
 420 
 421   /*
 422      * Set the right channel
 423    */
 424 
 425   if (mix_devices[dev][RIGHT_CHN].nbits == 0)
 426     return retvol;              /* Was just a mono channel */
 427 
 428   regoffs = mix_devices[dev][RIGHT_CHN].regno;
 429   val = ad_read (devc, regoffs);
 430   change_bits (&val, dev, RIGHT_CHN, right);
 431   ad_write (devc, regoffs, val);
 432   devc->saved_regs[regoffs] = val;
 433 
 434   return retvol;
 435 }
 436 
 437 static void
 438 ad1848_mixer_reset (ad1848_info * devc)
     /*  */
 439 {
 440   int             i;
 441 
 442   switch (devc->mode)
 443     {
 444     case MD_4231:
 445       devc->supported_devices = MODE2_MIXER_DEVICES;
 446       break;
 447 
 448     case MD_4232:
 449       devc->supported_devices = MODE3_MIXER_DEVICES;
 450       break;
 451 
 452     default:
 453       devc->supported_devices = MODE1_MIXER_DEVICES;
 454     }
 455 
 456   devc->supported_rec_devices = MODE1_REC_DEVICES;
 457 
 458   for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 459     if (devc->supported_devices & (1 << i))
 460       ad1848_mixer_set (devc, i, default_mixer_levels[i]);
 461   ad1848_set_recmask (devc, SOUND_MASK_MIC);
 462 }
 463 
 464 static int
 465 ad1848_mixer_ioctl (int dev, unsigned int cmd, caddr_t arg)
     /*  */
 466 {
 467   ad1848_info    *devc;
 468 
 469   int             codec_dev = mixer2codec[dev];
 470 
 471   if (!codec_dev)
 472     return -ENXIO;
 473 
 474   codec_dev--;
 475 
 476   devc = (ad1848_info *) audio_devs[codec_dev]->devc;
 477 
 478   if (((cmd >> 8) & 0xff) == 'M')
 479     {
 480 
 481       if (_IOC_DIR (cmd) & _IOC_WRITE)
 482         switch (cmd & 0xff)
 483           {
 484           case SOUND_MIXER_RECSRC:
 485             return snd_ioctl_return ((int *) arg, ad1848_set_recmask (devc, get_fs_long ((long *) arg)));
 486             break;
 487 
 488           default:
 489             return snd_ioctl_return ((int *) arg, ad1848_mixer_set (devc, cmd & 0xff, get_fs_long ((long *) arg)));
 490           }
 491       else
 492         switch (cmd & 0xff)     /*
 493                                  * Return parameters
 494                                  */
 495           {
 496 
 497           case SOUND_MIXER_RECSRC:
 498             return snd_ioctl_return ((int *) arg, devc->recmask);
 499             break;
 500 
 501           case SOUND_MIXER_DEVMASK:
 502             return snd_ioctl_return ((int *) arg, devc->supported_devices);
 503             break;
 504 
 505           case SOUND_MIXER_STEREODEVS:
 506             return snd_ioctl_return ((int *) arg, devc->supported_devices & ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX));
 507             break;
 508 
 509           case SOUND_MIXER_RECMASK:
 510             return snd_ioctl_return ((int *) arg, devc->supported_rec_devices);
 511             break;
 512 
 513           case SOUND_MIXER_CAPS:
 514             return snd_ioctl_return ((int *) arg, SOUND_CAP_EXCL_INPUT);
 515             break;
 516 
 517           default:
 518             return snd_ioctl_return ((int *) arg, ad1848_mixer_get (devc, cmd & 0xff));
 519           }
 520     }
 521   else
 522     return -EINVAL;
 523 }
 524 
 525 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
 526 {
 527   {
 528     "Generic AD1848 codec",
 529     DMA_AUTOMODE,
 530     AFMT_U8,                    /* Will be set later */
 531     NULL,
 532     ad1848_open,
 533     ad1848_close,
 534     ad1848_output_block,
 535     ad1848_start_input,
 536     ad1848_ioctl,
 537     ad1848_prepare_for_IO,
 538     ad1848_prepare_for_IO,
 539     ad1848_reset,
 540     ad1848_halt,
 541     NULL,
 542     NULL,
 543     ad1848_halt_input,
 544     ad1848_halt_output,
 545     ad1848_trigger
 546   }};
 547 
 548 static struct mixer_operations ad1848_mixer_operations =
 549 {
 550   "AD1848/CS4248/CS4231",
 551   ad1848_mixer_ioctl
 552 };
 553 
 554 static int
 555 ad1848_open (int dev, int mode)
     /*  */
 556 {
 557   ad1848_info    *devc = NULL;
 558   unsigned long   flags;
 559 
 560   if (dev < 0 || dev >= num_audiodevs)
 561     return -ENXIO;
 562 
 563   devc = (ad1848_info *) audio_devs[dev]->devc;
 564 
 565   save_flags (flags);
 566   cli ();
 567   if (devc->opened)
 568     {
 569       restore_flags (flags);
 570       printk ("ad1848: Already opened\n");
 571       return -EBUSY;
 572     }
 573 
 574 
 575   devc->dual_dma = 0;
 576 
 577   if (audio_devs[dev]->flags & DMA_DUPLEX)
 578     {
 579       devc->dual_dma = 1;
 580     }
 581 
 582   devc->intr_active = 0;
 583   devc->opened = 1;
 584   devc->irq_mode = 0;
 585   ad1848_trigger (dev, 0);
 586   restore_flags (flags);
 587 /*
 588  * Mute output until the playback really starts. This decreases clicking.
 589  */
 590   ad_mute (devc);
 591 
 592   return 0;
 593 }
 594 
 595 static void
 596 ad1848_close (int dev)
     /*  */
 597 {
 598   unsigned long   flags;
 599   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 600 
 601   DEB (printk ("ad1848_close(void)\n"));
 602 
 603   save_flags (flags);
 604   cli ();
 605 
 606   devc->intr_active = 0;
 607   ad1848_reset (dev);
 608 
 609 
 610   devc->opened = 0;
 611   devc->irq_mode = 0;
 612 
 613   ad_unmute (devc);
 614   restore_flags (flags);
 615 }
 616 
 617 static int
 618 set_speed (ad1848_info * devc, int arg)
     /*  */
 619 {
 620   /*
 621      * The sampling speed is encoded in the least significant nible of I8. The
 622      * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
 623      * three bits select the divisor (indirectly):
 624      *
 625      * The available speeds are in the following table. Keep the speeds in
 626      * the increasing order.
 627    */
 628   typedef struct
 629   {
 630     int             speed;
 631     unsigned char   bits;
 632   }
 633   speed_struct;
 634 
 635   static speed_struct speed_table[] =
 636   {
 637     {5510, (0 << 1) | 1},
 638     {5510, (0 << 1) | 1},
 639     {6620, (7 << 1) | 1},
 640     {8000, (0 << 1) | 0},
 641     {9600, (7 << 1) | 0},
 642     {11025, (1 << 1) | 1},
 643     {16000, (1 << 1) | 0},
 644     {18900, (2 << 1) | 1},
 645     {22050, (3 << 1) | 1},
 646     {27420, (2 << 1) | 0},
 647     {32000, (3 << 1) | 0},
 648     {33075, (6 << 1) | 1},
 649     {37800, (4 << 1) | 1},
 650     {44100, (5 << 1) | 1},
 651     {48000, (6 << 1) | 0}
 652   };
 653 
 654   int             i, n, selected = -1;
 655 
 656   n = sizeof (speed_table) / sizeof (speed_struct);
 657 
 658   if (devc->mode == MD_1845)    /* AD1845 has different timer than others */
 659     {
 660       if (arg < 4000)
 661         arg = 4000;
 662       if (arg > 50000)
 663         arg = 50000;
 664 
 665       devc->speed = arg;
 666       devc->speed_bits = speed_table[selected].bits;
 667       return devc->speed;
 668     }
 669 
 670   if (arg < speed_table[0].speed)
 671     selected = 0;
 672   if (arg > speed_table[n - 1].speed)
 673     selected = n - 1;
 674 
 675   for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 676     if (speed_table[i].speed == arg)
 677       selected = i;
 678     else if (speed_table[i].speed > arg)
 679       {
 680         int             diff1, diff2;
 681 
 682         diff1 = arg - speed_table[i - 1].speed;
 683         diff2 = speed_table[i].speed - arg;
 684 
 685         if (diff1 < diff2)
 686           selected = i - 1;
 687         else
 688           selected = i;
 689       }
 690 
 691   if (selected == -1)
 692     {
 693       printk ("ad1848: Can't find speed???\n");
 694       selected = 3;
 695     }
 696 
 697   devc->speed = speed_table[selected].speed;
 698   devc->speed_bits = speed_table[selected].bits;
 699   return devc->speed;
 700 }
 701 
 702 static int
 703 set_channels (ad1848_info * devc, int arg)
     /*  */
 704 {
 705   if (arg != 1 && arg != 2)
 706     return devc->channels;
 707 
 708   devc->channels = arg;
 709   return arg;
 710 }
 711 
 712 static int
 713 set_format (ad1848_info * devc, int arg)
     /*  */
 714 {
 715 
 716   static struct format_tbl
 717   {
 718     int             format;
 719     unsigned char   bits;
 720   }
 721   format2bits[] =
 722   {
 723     {
 724       0, 0
 725     }
 726     ,
 727     {
 728       AFMT_MU_LAW, 1
 729     }
 730     ,
 731     {
 732       AFMT_A_LAW, 3
 733     }
 734     ,
 735     {
 736       AFMT_IMA_ADPCM, 5
 737     }
 738     ,
 739     {
 740       AFMT_U8, 0
 741     }
 742     ,
 743     {
 744       AFMT_S16_LE, 2
 745     }
 746     ,
 747     {
 748       AFMT_S16_BE, 6
 749     }
 750     ,
 751     {
 752       AFMT_S8, 0
 753     }
 754     ,
 755     {
 756       AFMT_U16_LE, 0
 757     }
 758     ,
 759     {
 760       AFMT_U16_BE, 0
 761     }
 762   };
 763   int             i, n = sizeof (format2bits) / sizeof (struct format_tbl);
 764 
 765   if (!(arg & ad_format_mask[devc->mode]))
 766     arg = AFMT_U8;
 767 
 768   devc->audio_format = arg;
 769 
 770   for (i = 0; i < n; i++)
 771     if (format2bits[i].format == arg)
 772       {
 773         if ((devc->format_bits = format2bits[i].bits) == 0)
 774           return devc->audio_format = AFMT_U8;  /* Was not supported */
 775 
 776         return arg;
 777       }
 778 
 779   /* Still hanging here. Something must be terribly wrong */
 780   devc->format_bits = 0;
 781   return devc->audio_format = AFMT_U8;
 782 }
 783 
 784 static int
 785 ad1848_ioctl (int dev, unsigned int cmd, caddr_t arg, int local)
     /*  */
 786 {
 787   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 788 
 789   switch (cmd)
 790     {
 791     case SOUND_PCM_WRITE_RATE:
 792       if (local)
 793         return set_speed (devc, (int) arg);
 794       return snd_ioctl_return ((int *) arg, set_speed (devc, get_fs_long ((long *) arg)));
 795 
 796     case SOUND_PCM_READ_RATE:
 797       if (local)
 798         return devc->speed;
 799       return snd_ioctl_return ((int *) arg, devc->speed);
 800 
 801     case SNDCTL_DSP_STEREO:
 802       if (local)
 803         return set_channels (devc, (int) arg + 1) - 1;
 804       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg) + 1) - 1);
 805 
 806     case SOUND_PCM_WRITE_CHANNELS:
 807       if (local)
 808         return set_channels (devc, (int) arg);
 809       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg)));
 810 
 811     case SOUND_PCM_READ_CHANNELS:
 812       if (local)
 813         return devc->channels;
 814       return snd_ioctl_return ((int *) arg, devc->channels);
 815 
 816     case SNDCTL_DSP_SAMPLESIZE:
 817       if (local)
 818         return set_format (devc, (int) arg);
 819       return snd_ioctl_return ((int *) arg, set_format (devc, get_fs_long ((long *) arg)));
 820 
 821     case SOUND_PCM_READ_BITS:
 822       if (local)
 823         return devc->audio_format;
 824       return snd_ioctl_return ((int *) arg, devc->audio_format);
 825 
 826     default:;
 827     }
 828   return -EINVAL;
 829 }
 830 
 831 static void
 832 ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 833 {
 834   unsigned long   flags, cnt;
 835   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 836 
 837   cnt = count;
 838 
 839   if (devc->audio_format == AFMT_IMA_ADPCM)
 840     {
 841       cnt /= 4;
 842     }
 843   else
 844     {
 845       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 846         cnt >>= 1;
 847     }
 848   if (devc->channels > 1)
 849     cnt >>= 1;
 850   cnt--;
 851 
 852   if (devc->irq_mode & PCM_ENABLE_OUTPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 853       intrflag &&
 854       cnt == devc->xfer_count)
 855     {
 856       devc->irq_mode |= PCM_ENABLE_OUTPUT;
 857       devc->intr_active = 1;
 858       return;                   /*
 859                                  * Auto DMA mode on. No need to react
 860                                  */
 861     }
 862   save_flags (flags);
 863   cli ();
 864 
 865   if (dma_restart)
 866     {
 867       /* ad1848_halt (dev); */
 868       DMAbuf_start_dma (dev, buf, count, DMA_MODE_WRITE);
 869     }
 870 
 871   ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 872   ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 873 
 874   /* ad_write (devc, 9, ad_read (devc, 9) | 0x01); *//* Playback enable */
 875   ad_unmute (devc);
 876 
 877   devc->xfer_count = cnt;
 878   devc->irq_mode |= PCM_ENABLE_OUTPUT;
 879   devc->intr_active = 1;
 880   restore_flags (flags);
 881 }
 882 
 883 static void
 884 ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 885 {
 886   unsigned long   flags, cnt;
 887   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 888 
 889   cnt = count;
 890   if (devc->audio_format == AFMT_IMA_ADPCM)
 891     {
 892       cnt /= 4;
 893     }
 894   else
 895     {
 896       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 897         cnt >>= 1;
 898     }
 899   if (devc->channels > 1)
 900     cnt >>= 1;
 901   cnt--;
 902 
 903   if (devc->irq_mode & PCM_ENABLE_INPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 904       intrflag &&
 905       cnt == devc->xfer_count)
 906     {
 907       devc->irq_mode |= PCM_ENABLE_INPUT;
 908       devc->intr_active = 1;
 909       return;                   /*
 910                                  * Auto DMA mode on. No need to react
 911                                  */
 912     }
 913   save_flags (flags);
 914   cli ();
 915 
 916   if (dma_restart)
 917     {
 918       /* ad1848_halt (dev); */
 919       DMAbuf_start_dma (dev, buf, count, DMA_MODE_READ);
 920     }
 921 
 922   if (devc->mode == MD_1848 || !devc->dual_dma)         /* Single DMA channel mode */
 923     {
 924       ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 925       ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 926     }
 927   else
 928     /* Dual DMA channel mode */
 929     {
 930       ad_write (devc, 31, (unsigned char) (cnt & 0xff));
 931       ad_write (devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
 932     }
 933 
 934   /*  ad_write (devc, 9, ad_read (devc, 9) | 0x02); *//* Capture enable */
 935   ad_unmute (devc);
 936 
 937   devc->xfer_count = cnt;
 938   devc->irq_mode |= PCM_ENABLE_INPUT;
 939   devc->intr_active = 1;
 940   restore_flags (flags);
 941 }
 942 
 943 static int
 944 ad1848_prepare_for_IO (int dev, int bsize, int bcount)
     /*  */
 945 {
 946   int             timeout;
 947   unsigned char   fs, old_fs;
 948   unsigned long   flags;
 949   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 950 
 951   if (devc->irq_mode)
 952     return 0;
 953 
 954   save_flags (flags);
 955   cli ();
 956   fs = devc->speed_bits | (devc->format_bits << 5);
 957 
 958   if (devc->channels > 1)
 959     fs |= 0x10;
 960 
 961   if (devc->mode == MD_1845)    /* Use alternate speed select registers */
 962     {
 963       fs &= 0xf0;               /* Mask off the rate select bits */
 964 
 965       ad_write (devc, 22, (devc->speed >> 8) & 0xff);   /* Speed MSB */
 966       ad_write (devc, 23, devc->speed & 0xff);  /* Speed LSB */
 967     }
 968 
 969   if (fs == (old_fs = ad_read (devc, 8)))       /* No change */
 970     {
 971       restore_flags (flags);
 972       devc->xfer_count = 0;
 973       return 0;
 974     }
 975 
 976   ad_enter_MCE (devc);          /* Enables changes to the format select reg */
 977   ad_write (devc, 8, fs);
 978   /*
 979    * Write to I8 starts resyncronization. Wait until it completes.
 980    */
 981   timeout = 10000;
 982   while (timeout > 0 && inb (devc->base) == 0x80)
 983     timeout--;
 984 
 985   /*
 986      * If mode == 2 (CS4231), set I28 also. It's the capture format register.
 987    */
 988   if (devc->mode != MD_1848)
 989     {
 990       ad_write (devc, 28, fs);
 991 
 992       /*
 993          * Write to I28 starts resyncronization. Wait until it completes.
 994        */
 995       timeout = 10000;
 996       while (timeout > 0 && inb (devc->base) == 0x80)
 997         timeout--;
 998 
 999     }
1000 
1001   ad_leave_MCE (devc);          /*
1002                                  * Starts the calibration process.
1003                                  */
1004   restore_flags (flags);
1005   devc->xfer_count = 0;
1006 
1007 #ifdef CONFIG_SEQUENCER
1008   if (dev == timer_installed && devc->timer_running)
1009     if ((fs & 0x01) != (old_fs & 0x01))
1010       {
1011         ad1848_tmr_reprogram (dev);
1012       }
1013 #endif
1014   return 0;
1015 }
1016 
1017 static void
1018 ad1848_reset (int dev)
     /*  */
1019 {
1020   ad1848_halt (dev);
1021 }
1022 
1023 static void
1024 ad1848_halt (int dev)
     /*  */
1025 {
1026   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1027   unsigned long   flags;
1028   int             timeout;
1029 
1030   save_flags (flags);
1031   cli ();
1032 
1033   ad_mute (devc);
1034   ad_enter_MCE (devc);
1035   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1036   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1037 
1038   ad_write (devc, 15, 0);       /* Clear DMA counter */
1039   ad_write (devc, 14, 0);       /* Clear DMA counter */
1040 
1041   if (devc->mode != MD_1848)
1042     {
1043       ad_write (devc, 30, 0);   /* Clear DMA counter */
1044       ad_write (devc, 31, 0);   /* Clear DMA counter */
1045     }
1046 
1047   for (timeout = 0; timeout < 1000 && !(inb (io_Status (devc)) & 0x80);
1048        timeout++);              /* Wait for interrupt */
1049 
1050   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1051   outb (0, io_Status (devc));   /* Clear interrupt status */
1052   outb (0, io_Status (devc));   /* Clear interrupt status */
1053   devc->irq_mode = 0;
1054   ad_leave_MCE (devc);
1055 
1056   /* DMAbuf_reset_dma (dev); */
1057   restore_flags (flags);
1058 }
1059 
1060 static void
1061 ad1848_halt_input (int dev)
     /*  */
1062 {
1063   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1064   unsigned long   flags;
1065 
1066   if (devc->mode == MD_1848)
1067     {
1068       ad1848_halt (dev);
1069       return;
1070     }
1071 
1072   save_flags (flags);
1073   cli ();
1074 
1075   ad_mute (devc);
1076   ad_write (devc, 9, ad_read (devc, 9) & ~0x02);        /* Stop capture */
1077 
1078 
1079   devc->irq_mode &= ~PCM_ENABLE_INPUT;
1080 
1081   restore_flags (flags);
1082 }
1083 
1084 static void
1085 ad1848_halt_output (int dev)
     /*  */
1086 {
1087   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1088   unsigned long   flags;
1089 
1090   if (devc->mode == MD_1848)
1091     {
1092       ad1848_halt (dev);
1093       return;
1094     }
1095 
1096   save_flags (flags);
1097   cli ();
1098 
1099   ad_mute (devc);
1100   ad_write (devc, 9, ad_read (devc, 9) & ~0x01);        /* Stop playback */
1101 
1102 
1103   devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1104 
1105   restore_flags (flags);
1106 }
1107 
1108 static void
1109 ad1848_trigger (int dev, int state)
     /*  */
1110 {
1111   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1112   unsigned long   flags;
1113   unsigned char   tmp;
1114 
1115   save_flags (flags);
1116   cli ();
1117   state &= devc->irq_mode;
1118 
1119   tmp = ad_read (devc, 9) & ~0x03;
1120   if (state & PCM_ENABLE_INPUT)
1121     tmp |= 0x02;
1122   if (state & PCM_ENABLE_OUTPUT)
1123     tmp |= 0x01;
1124   ad_write (devc, 9, tmp);
1125 
1126   restore_flags (flags);
1127 }
1128 
1129 int
1130 ad1848_detect (int io_base, int *ad_flags, int *osp)
     /*  */
1131 {
1132 
1133   unsigned char   tmp;
1134   int             i;
1135   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1136   unsigned char   tmp1 = 0xff, tmp2 = 0xff;
1137 
1138   DDB (printk ("ad1848_detect(%x)\n", io_base));
1139 
1140   if (ad_flags)
1141     *ad_flags = 0;
1142 
1143   if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1144     {
1145       DDB (printk ("ad1848 detect error - step 0\n"));
1146       return 0;
1147     }
1148   if (check_region (io_base, 4))
1149     {
1150       printk ("\n\nad1848.c: Port %x not free.\n\n", io_base);
1151       return 0;
1152     }
1153 
1154   devc->base = io_base;
1155   devc->irq_ok = 0;
1156   devc->timer_running = 0;
1157   devc->MCE_bit = 0x40;
1158   devc->irq = 0;
1159   devc->opened = 0;
1160   devc->chip_name = "AD1848";
1161   devc->mode = MD_1848;         /* AD1848 or CS4248 */
1162   devc->osp = osp;
1163 
1164   /*
1165      * Check that the I/O address is in use.
1166      *
1167      * The bit 0x80 of the base I/O port is known to be 0 after the
1168      * chip has performed it's power on initialization. Just assume
1169      * this has happened before the OS is starting.
1170      *
1171      * If the I/O address is unused, it typically returns 0xff.
1172    */
1173 
1174   DDB (printk ("ad1848_detect() - step A\n"));
1175   if ((inb (devc->base) & 0x80) != 0x00)        /* Not a AD1848 */
1176     {
1177       DDB (printk ("ad1848 detect error - step A (%02x)\n",
1178                    inb (devc->base)));
1179       return 0;
1180     }
1181 
1182   /*
1183      * Test if it's possible to change contents of the indirect registers.
1184      * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1185      * so try to avoid using it.
1186    */
1187 
1188   DDB (printk ("ad1848_detect() - step B\n"));
1189   ad_write (devc, 0, 0xaa);
1190   ad_write (devc, 1, 0x45);     /* 0x55 with bit 0x10 clear */
1191 
1192   if ((tmp1 = ad_read (devc, 0)) != 0xaa || (tmp2 = ad_read (devc, 1)) != 0x45)
1193     {
1194       DDB (printk ("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1195       return 0;
1196     }
1197 
1198   DDB (printk ("ad1848_detect() - step C\n"));
1199   ad_write (devc, 0, 0x45);
1200   ad_write (devc, 1, 0xaa);
1201 
1202   if ((tmp1 = ad_read (devc, 0)) != 0x45 || (tmp2 = ad_read (devc, 1)) != 0xaa)
1203     {
1204       DDB (printk ("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1205       return 0;
1206     }
1207 
1208   /*
1209      * The indirect register I12 has some read only bits. Lets
1210      * try to change them.
1211    */
1212 
1213   DDB (printk ("ad1848_detect() - step D\n"));
1214   tmp = ad_read (devc, 12);
1215   ad_write (devc, 12, (~tmp) & 0x0f);
1216 
1217   if ((tmp & 0x0f) != ((tmp1 = ad_read (devc, 12)) & 0x0f))
1218     {
1219       DDB (printk ("ad1848 detect error - step D (%x)\n", tmp1));
1220       return 0;
1221     }
1222 
1223   /*
1224      * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1225      *   0x01=RevB and 0x0A=RevC.
1226    */
1227 
1228   /*
1229      * The original AD1848/CS4248 has just 15 indirect registers. This means
1230      * that I0 and I16 should return the same value (etc.).
1231      * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1232      * with CS4231.
1233    */
1234 
1235   DDB (printk ("ad1848_detect() - step F\n"));
1236   ad_write (devc, 12, 0);       /* Mode2=disabled */
1237 
1238   for (i = 0; i < 16; i++)
1239     if ((tmp1 = ad_read (devc, i)) != (tmp2 = ad_read (devc, i + 16)))
1240       {
1241         DDB (printk ("ad1848 detect error - step F(%d/%x/%x)\n", i, tmp1, tmp2));
1242         return 0;
1243       }
1244 
1245   /*
1246      * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1247      * The bit 0x80 is always 1 in CS4248 and CS4231.
1248    */
1249 
1250   DDB (printk ("ad1848_detect() - step G\n"));
1251   ad_write (devc, 12, 0x40);    /* Set mode2, clear 0x80 */
1252 
1253   tmp1 = ad_read (devc, 12);
1254   if (tmp1 & 0x80)
1255     {
1256       if (ad_flags)
1257         *ad_flags |= AD_F_CS4248;
1258 
1259       devc->chip_name = "CS4248";       /* Our best knowledge just now */
1260     }
1261 
1262   if ((tmp1 & 0xc0) == (0x80 | 0x40))
1263     {
1264       /*
1265          *      CS4231 detected - is it?
1266          *
1267          *      Verify that setting I0 doesn't change I16.
1268        */
1269       DDB (printk ("ad1848_detect() - step H\n"));
1270       ad_write (devc, 16, 0);   /* Set I16 to known value */
1271 
1272       ad_write (devc, 0, 0x45);
1273       if ((tmp1 = ad_read (devc, 16)) != 0x45)  /* No change -> CS4231? */
1274         {
1275 
1276           ad_write (devc, 0, 0xaa);
1277           if ((tmp1 = ad_read (devc, 16)) == 0xaa)      /* Rotten bits? */
1278             {
1279               DDB (printk ("ad1848 detect error - step H(%x)\n", tmp1));
1280               return 0;
1281             }
1282 
1283           /*
1284              * Verify that some bits of I25 are read only.
1285            */
1286 
1287           DDB (printk ("ad1848_detect() - step I\n"));
1288           tmp1 = ad_read (devc, 25);    /* Original bits */
1289           ad_write (devc, 25, ~tmp1);   /* Invert all bits */
1290           if ((ad_read (devc, 25) & 0xe7) == (tmp1 & 0xe7))
1291             {
1292               int             id;
1293 
1294               /*
1295                *      It's at least CS4231
1296                */
1297               devc->chip_name = "CS4231";
1298 
1299               devc->mode = MD_4231;
1300 
1301               /*
1302                * It could be an AD1845 or CS4231A as well.
1303                * CS4231 and AD1845 report the same revision info in I25
1304                * while the CS4231A reports different.
1305                */
1306 
1307               DDB (printk ("ad1848_detect() - step I\n"));
1308               id = ad_read (devc, 25) & 0xe7;
1309 
1310               switch (id)
1311                 {
1312 
1313                 case 0xa0:
1314                   devc->chip_name = "CS4231A";
1315                   devc->mode = MD_4231A;
1316                   break;
1317 
1318                 case 0xa2:
1319                   devc->chip_name = "CS4232";
1320                   devc->mode = MD_4232;
1321                   break;
1322 
1323                 case 0xb2:
1324                   devc->chip_name = "CS4232A";
1325                   devc->mode = MD_4232;
1326                   break;
1327 
1328                 case 0x80:
1329                   {
1330                     /* 
1331                      * It must be a CS4231 or AD1845. The register I23 of
1332                      * CS4231 is undefined and it appears to be read only.
1333                      * AD1845 uses I23 for setting sample rate. Assume
1334                      * the chip is AD1845 if I23 is changeable.
1335                      */
1336 
1337                     unsigned char   tmp = ad_read (devc, 23);
1338 
1339                     ad_write (devc, 23, ~tmp);
1340                     if (ad_read (devc, 23) != tmp)      /* AD1845 ? */
1341                       {
1342                         devc->chip_name = "AD1845";
1343                         devc->mode = MD_1845;
1344                       }
1345 
1346                     ad_write (devc, 23, tmp);   /* Restore */
1347                   }
1348                   break;
1349 
1350                 default:        /* Assume CS4231 */
1351                   devc->mode = MD_4231;
1352 
1353                 }
1354             }
1355           ad_write (devc, 25, tmp1);    /* Restore bits */
1356 
1357           DDB (printk ("ad1848_detect() - step K\n"));
1358         }
1359     }
1360 
1361   DDB (printk ("ad1848_detect() - step L\n"));
1362   if (ad_flags)
1363     {
1364       if (devc->mode != MD_1848)
1365         *ad_flags |= AD_F_CS4231;
1366     }
1367 
1368   DDB (printk ("ad1848_detect() - Detected OK\n"));
1369   return 1;
1370 }
1371 
1372 void
1373 ad1848_init (char *name, int io_base, int irq, int dma_playback, int dma_capture, int share_dma, int *osp)
     /*  */
1374 {
1375   /*
1376      * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1377      *   so that this driver doesn't need to allocate/deallocate it.
1378      *   The actually used IRQ is ABS(irq).
1379    */
1380 
1381   /*
1382      * Initial values for the indirect registers of CS4248/AD1848.
1383    */
1384   static int      init_values[] =
1385   {
1386     0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x80, 0x80,
1387     0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1388 
1389   /* Positions 16 to 31 just for CS4231 */
1390     0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1391     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1392   };
1393   int             i, my_dev;
1394 
1395   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1396 
1397   if (!ad1848_detect (io_base, NULL, osp))
1398     return;
1399 
1400   request_region (devc->base, 4, devc->chip_name);
1401 
1402   devc->irq = (irq > 0) ? irq : 0;
1403   devc->opened = 0;
1404   devc->timer_ticks = 0;
1405   devc->osp = osp;
1406 
1407   if (nr_ad1848_devs != 0)
1408     {
1409       memcpy ((char *) &ad1848_pcm_operations[nr_ad1848_devs],
1410               (char *) &ad1848_pcm_operations[0],
1411               sizeof (struct audio_operations));
1412     }
1413 
1414   for (i = 0; i < 16; i++)
1415     ad_write (devc, i, init_values[i]);
1416 
1417   ad_mute (devc);               /* Initialize some variables */
1418   ad_unmute (devc);             /* Leave it unmuted now */
1419 
1420   if (devc->mode > MD_1848)
1421     {
1422       if (dma_capture == dma_playback || dma_capture == -1 || dma_playback == -1)
1423         {
1424           ad_write (devc, 9, ad_read (devc, 9) | 0x04);         /* Single DMA mode */
1425           ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1426         }
1427       else
1428         {
1429           ad_write (devc, 9, ad_read (devc, 9) & ~0x04);        /* Dual DMA mode */
1430           ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_DUPLEX;
1431         }
1432 
1433       ad_write (devc, 12, ad_read (devc, 12) | 0x40);   /* Mode2 = enabled */
1434       for (i = 16; i < 32; i++)
1435         ad_write (devc, i, init_values[i]);
1436 
1437       if (devc->mode == MD_4231A || devc->mode == MD_4232)
1438         ad_write (devc, 9, init_values[9] | 0x18);      /* Enable full calibration */
1439 
1440       if (devc->mode == MD_1845)
1441         ad_write (devc, 27, init_values[27] | 0x08);    /* Alternate freq select enabled */
1442     }
1443   else
1444     {
1445       ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1446       ad_write (devc, 9, ad_read (devc, 9) | 0x04);     /* Single DMA mode */
1447     }
1448 
1449   outb (0, io_Status (devc));   /* Clear pending interrupts */
1450 
1451   if (name != NULL && name[0] != 0)
1452     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1453              "%s (%s)", name, devc->chip_name);
1454   else
1455     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1456              "Generic audio codec (%s)", devc->chip_name);
1457 
1458   conf_printf2 (ad1848_pcm_operations[nr_ad1848_devs].name,
1459                 devc->base, devc->irq, dma_playback, dma_capture);
1460 
1461   if (num_audiodevs < MAX_AUDIO_DEV)
1462     {
1463       audio_devs[my_dev = num_audiodevs++] = &ad1848_pcm_operations[nr_ad1848_devs];
1464       if (irq > 0)
1465         {
1466           audio_devs[my_dev]->devc = devc;
1467           irq2dev[irq] = my_dev;
1468           if (snd_set_irq_handler (devc->irq, ad1848_interrupt,
1469                                    audio_devs[my_dev]->name,
1470                                    devc->osp) < 0)
1471             {
1472               printk ("ad1848: IRQ in use\n");
1473             }
1474 
1475 #ifdef NO_IRQ_TEST
1476           if (devc->mode != MD_1848)
1477             {
1478               int             x;
1479               unsigned char   tmp = ad_read (devc, 16);
1480 
1481               devc->timer_ticks = 0;
1482 
1483               ad_write (devc, 21, 0x00);        /* Timer msb */
1484               ad_write (devc, 20, 0x10);        /* Timer lsb */
1485 
1486               ad_write (devc, 16, tmp | 0x40);  /* Enable timer */
1487               for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1488               ad_write (devc, 16, tmp & ~0x40);         /* Disable timer */
1489 
1490               if (devc->timer_ticks == 0)
1491                 printk ("[IRQ conflict???]");
1492               else
1493                 devc->irq_ok = 1;
1494 
1495             }
1496           else
1497             devc->irq_ok = 1;   /* Couldn't test. assume it's OK */
1498 #else
1499           devc->irq_ok = 1;
1500 #endif
1501         }
1502       else if (irq < 0)
1503         irq2dev[-irq] = devc->dev_no = my_dev;
1504 
1505       audio_devs[my_dev]->dmachan1 = dma_playback;
1506       audio_devs[my_dev]->dmachan2 = dma_capture;
1507       audio_devs[my_dev]->buffsize = DSP_BUFFSIZE;
1508       audio_devs[my_dev]->devc = devc;
1509       audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1510       nr_ad1848_devs++;
1511 
1512 #ifdef CONFIG_SEQUENCER
1513       if (devc->mode != MD_1848 && devc->irq_ok)
1514         ad1848_tmr_install (my_dev);
1515 #endif
1516 
1517       if (!share_dma)
1518         {
1519           if (sound_alloc_dma (dma_playback, "Sound System"))
1520             printk ("ad1848.c: Can't allocate DMA%d\n", dma_playback);
1521 
1522           if (dma_capture != dma_playback)
1523             if (sound_alloc_dma (dma_capture, "Sound System (capture)"))
1524               printk ("ad1848.c: Can't allocate DMA%d\n", dma_capture);
1525         }
1526 
1527       /*
1528          * Toggle the MCE bit. It completes the initialization phase.
1529        */
1530 
1531       ad_enter_MCE (devc);      /* In case the bit was off */
1532       ad_leave_MCE (devc);
1533 
1534       if (num_mixers < MAX_MIXER_DEV)
1535         {
1536           mixer2codec[num_mixers] = my_dev + 1;
1537           audio_devs[my_dev]->mixer_dev = num_mixers;
1538           mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1539           ad1848_mixer_reset (devc);
1540         }
1541     }
1542   else
1543     printk ("AD1848: Too many PCM devices available\n");
1544 }
1545 
1546 void
1547 ad1848_unload (int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
     /*  */
1548 {
1549   int             i, dev = 0;
1550   ad1848_info    *devc = NULL;
1551 
1552   for (i = 0; devc == NULL && nr_ad1848_devs; i++)
1553     if (dev_info[i].base == io_base)
1554       {
1555         devc = &dev_info[i];
1556         dev = devc->dev_no;
1557       }
1558 
1559   if (devc != NULL)
1560     {
1561       release_region (devc->base, 4);
1562 
1563       if (!share_dma)
1564         {
1565           if (irq > 0)
1566             snd_release_irq (devc->irq);
1567 
1568           sound_free_dma (audio_devs[dev]->dmachan1);
1569 
1570           if (audio_devs[dev]->dmachan2 != audio_devs[dev]->dmachan1)
1571             sound_free_dma (audio_devs[dev]->dmachan2);
1572         }
1573     }
1574   else
1575     printk ("ad1848: Can't find device to be undoaded. Base=%x\n",
1576             io_base);
1577 }
1578 
1579 void
1580 ad1848_interrupt (int irq, struct pt_regs *dummy)
     /*  */
1581 {
1582   unsigned char   status;
1583   ad1848_info    *devc;
1584   int             dev;
1585   int             alt_stat = 0xff;
1586 
1587   if (irq < 0 || irq > 15)
1588     {
1589       dev = -1;
1590     }
1591   else
1592     dev = irq2dev[irq];
1593 
1594   if (dev < 0 || dev >= num_audiodevs)
1595     {
1596       for (irq = 0; irq < 17; irq++)
1597         if (irq2dev[irq] != -1)
1598           break;
1599 
1600       if (irq > 15)
1601         {
1602           printk ("ad1848.c: Bogus interrupt %d\n", irq);
1603           return;
1604         }
1605 
1606       dev = irq2dev[irq];
1607       devc = (ad1848_info *) audio_devs[dev]->devc;
1608     }
1609   else
1610     devc = (ad1848_info *) audio_devs[dev]->devc;
1611 
1612   status = inb (io_Status (devc));
1613 
1614   if (status == 0x80)
1615     printk ("ad1848_interrupt: Why?\n");
1616 
1617   if (status & 0x01)
1618     {
1619 
1620       if (devc->mode != MD_1848)
1621         alt_stat = ad_read (devc, 24);
1622 
1623       if (devc->opened && devc->irq_mode & PCM_ENABLE_INPUT && alt_stat & 0x20)
1624         {
1625           DMAbuf_inputintr (dev);
1626         }
1627 
1628       if (devc->opened && devc->irq_mode & PCM_ENABLE_OUTPUT &&
1629           alt_stat & 0x10)
1630         {
1631           DMAbuf_outputintr (dev, 1);
1632         }
1633 
1634       if (devc->mode != MD_1848 && alt_stat & 0x40)     /* Timer interrupt */
1635         {
1636           devc->timer_ticks++;
1637 #ifdef CONFIG_SEQUENCER
1638           if (timer_installed == dev && devc->timer_running)
1639             sound_timer_interrupt ();
1640 #endif
1641         }
1642     }
1643 
1644   if (devc->mode != MD_1848)
1645     ad_write (devc, 24, ad_read (devc, 24) & ~alt_stat);        /* Selective ack */
1646   else
1647     outb (0, io_Status (devc)); /* Clear interrupt status */
1648 }
1649 
1650 /*
1651  * Some extra code for the MS Sound System
1652  */
1653 
1654 void
1655 check_opl3 (int base, struct address_info *hw_config)
     /*  */
1656 {
1657 
1658 #ifdef CONFIG_YM3812
1659   if (check_region (base, 4))
1660     {
1661       printk ("\n\nopl3.c: I/O port %x already in use\n\n", base);
1662       return;
1663     }
1664 
1665   if (!opl3_detect (base, hw_config->osp))
1666     return;
1667 
1668   opl3_init (0, base, hw_config->osp);
1669   request_region (base, 4, "OPL3/OPL2");
1670 #endif
1671 }
1672 
1673 int
1674 probe_ms_sound (struct address_info *hw_config)
     /*  */
1675 {
1676   unsigned char   tmp;
1677 
1678   DDB (printk ("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
1679 
1680   if (check_region (hw_config->io_base, 8))
1681     {
1682       printk ("MSS: I/O port conflict\n");
1683       return 0;
1684     }
1685 
1686   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1687     {
1688       /* check_opl3(0x388, hw_config); */
1689       return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1690     }
1691 
1692   /*
1693      * Check if the IO port returns valid signature. The original MS Sound
1694      * system returns 0x04 while some cards (AudioTriX Pro for example)
1695      * return 0x00 or 0x0f.
1696    */
1697 
1698   if ((tmp = inb (hw_config->io_base + 3)) == 0xff)     /* Bus float */
1699     {
1700       DDB (printk ("I/O address is inactive (%x)\n", tmp));
1701       return 0;
1702     }
1703   if ((tmp & 0x3f) != 0x04 &&
1704       (tmp & 0x3f) != 0x0f &&
1705       (tmp & 0x3f) != 0x00)
1706     {
1707       DDB (printk ("No MSS signature detected on port 0x%x (0x%x)\n",
1708                    hw_config->io_base, inb (hw_config->io_base + 3)));
1709       return 0;
1710     }
1711 
1712   if (hw_config->irq > 11)
1713     {
1714       printk ("MSS: Bad IRQ %d\n", hw_config->irq);
1715       return 0;
1716     }
1717 
1718   if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
1719     {
1720       printk ("MSS: Bad DMA %d\n", hw_config->dma);
1721       return 0;
1722     }
1723 
1724   /*
1725      * Check that DMA0 is not in use with a 8 bit board.
1726    */
1727 
1728   if (hw_config->dma == 0 && inb (hw_config->io_base + 3) & 0x80)
1729     {
1730       printk ("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1731       return 0;
1732     }
1733 
1734   if (hw_config->irq > 7 && hw_config->irq != 9 && inb (hw_config->io_base + 3) & 0x80)
1735     {
1736       printk ("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1737       return 0;
1738     }
1739 
1740   return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1741 }
1742 
1743 long
1744 attach_ms_sound (long mem_start, struct address_info *hw_config)
     /*  */
1745 {
1746   static char     interrupt_bits[12] =
1747   {
1748     -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1749   };
1750   char            bits;
1751 
1752   static char     dma_bits[4] =
1753   {
1754     1, 2, 0, 3
1755   };
1756 
1757   int             config_port = hw_config->io_base + 0;
1758   int             version_port = hw_config->io_base + 3;
1759 
1760   if (!ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp))
1761     return mem_start;
1762 
1763   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1764     {
1765       ad1848_init ("MS Sound System", hw_config->io_base + 4,
1766                    hw_config->irq,
1767                    hw_config->dma,
1768                    hw_config->dma2, 0, hw_config->osp);
1769       request_region (hw_config->io_base, 4, "WSS config");
1770       return mem_start;
1771     }
1772 
1773   /*
1774      * Set the IRQ and DMA addresses.
1775    */
1776 
1777   bits = interrupt_bits[hw_config->irq];
1778   if (bits == -1)
1779     return mem_start;
1780 
1781   outb (bits | 0x40, config_port);
1782   if ((inb (version_port) & 0x40) == 0)
1783     printk ("[IRQ Conflict?]");
1784 
1785   outb (bits | dma_bits[hw_config->dma], config_port);  /* Write IRQ+DMA setup */
1786 
1787   ad1848_init ("MS Sound System", hw_config->io_base + 4,
1788                hw_config->irq,
1789                hw_config->dma,
1790                hw_config->dma, 0, hw_config->osp);
1791   request_region (hw_config->io_base, 4, "WSS config");
1792   return mem_start;
1793 }
1794 
1795 void
1796 unload_ms_sound (struct address_info *hw_config)
     /*  */
1797 {
1798   ad1848_unload (hw_config->io_base + 4,
1799                  hw_config->irq,
1800                  hw_config->dma,
1801                  hw_config->dma, 0);
1802   release_region (hw_config->io_base, 4);
1803 }
1804 
1805 /*
1806  * WSS compatible PnP codec support
1807  */
1808 
1809 int
1810 probe_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1811 {
1812   return ad1848_detect (hw_config->io_base, NULL, hw_config->osp);
1813 }
1814 
1815 long
1816 attach_pnp_ad1848 (long mem_start, struct address_info *hw_config)
     /*  */
1817 {
1818 
1819   ad1848_init (hw_config->name, hw_config->io_base,
1820                hw_config->irq,
1821                hw_config->dma,
1822                hw_config->dma2, 0, hw_config->osp);
1823   return mem_start;
1824 }
1825 
1826 void
1827 unload_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1828 {
1829   ad1848_unload (hw_config->io_base,
1830                  hw_config->irq,
1831                  hw_config->dma,
1832                  hw_config->dma2, 0);
1833   release_region (hw_config->io_base, 4);
1834 }
1835 
1836 #ifdef CONFIG_SEQUENCER
1837 /*
1838  * Timer stuff (for /dev/music).
1839  */
1840 
1841 static unsigned int current_interval = 0;
1842 
1843 static unsigned int
1844 ad1848_tmr_start (int dev, unsigned int usecs)
     /*  */
1845 {
1846   unsigned long   flags;
1847   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1848   unsigned long   xtal_nsecs;   /* nanoseconds per xtal oscillaror tick */
1849   unsigned long   divider;
1850 
1851   save_flags (flags);
1852   cli ();
1853 
1854 /*
1855  * Length of the timer interval (in nanoseconds) depends on the
1856  * selected crystal oscillator. Check this from bit 0x01 of I8.
1857  *
1858  * AD1845 has just one oscillator which has cycle time of 10.050 us
1859  * (when a 24.576 MHz xtal oscillator is used).
1860  *
1861  * Convert requested interval to nanoseconds before computing
1862  * the timer divider.
1863  */
1864 
1865   if (devc->mode == MD_1845)
1866     xtal_nsecs = 10050;
1867   else if (ad_read (devc, 8) & 0x01)
1868     xtal_nsecs = 9920;
1869   else
1870     xtal_nsecs = 9969;
1871 
1872   divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
1873 
1874   if (divider < 100)            /* Don't allow shorter intervals than about 1ms */
1875     divider = 100;
1876 
1877   if (divider > 65535)          /* Overflow check */
1878     divider = 65535;
1879 
1880   ad_write (devc, 21, (divider >> 8) & 0xff);   /* Set upper bits */
1881   ad_write (devc, 20, divider & 0xff);  /* Set lower bits */
1882   ad_write (devc, 16, ad_read (devc, 16) | 0x40);       /* Start the timer */
1883   devc->timer_running = 1;
1884   restore_flags (flags);
1885 
1886   return current_interval = (divider * xtal_nsecs + 500) / 1000;
1887 }
1888 
1889 static void
1890 ad1848_tmr_reprogram (int dev)
     /*  */
1891 {
1892 /*
1893  *    Audio driver has changed sampling rate so that a different xtal
1894  *      oscillator was selected. We have to reprogram the timer rate.
1895  */
1896 
1897   ad1848_tmr_start (dev, current_interval);
1898   sound_timer_syncinterval (current_interval);
1899 }
1900 
1901 static void
1902 ad1848_tmr_disable (int dev)
     /*  */
1903 {
1904   unsigned long   flags;
1905   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1906 
1907   save_flags (flags);
1908   cli ();
1909   ad_write (devc, 16, ad_read (devc, 16) & ~0x40);
1910   devc->timer_running = 0;
1911   restore_flags (flags);
1912 }
1913 
1914 static void
1915 ad1848_tmr_restart (int dev)
     /*  */
1916 {
1917   unsigned long   flags;
1918   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1919 
1920   if (current_interval == 0)
1921     return;
1922 
1923   save_flags (flags);
1924   cli ();
1925   ad_write (devc, 16, ad_read (devc, 16) | 0x40);
1926   devc->timer_running = 1;
1927   restore_flags (flags);
1928 }
1929 
1930 static struct sound_lowlev_timer ad1848_tmr =
1931 {
1932   0,
1933   ad1848_tmr_start,
1934   ad1848_tmr_disable,
1935   ad1848_tmr_restart
1936 };
1937 
1938 static int
1939 ad1848_tmr_install (int dev)
     /*  */
1940 {
1941 
1942   if (timer_installed != -1)
1943     return 0;                   /* Don't install another timer */
1944 
1945   timer_installed = ad1848_tmr.dev = dev;
1946   sound_timer_init (&ad1848_tmr, audio_devs[dev]->name);
1947 
1948   return 1;
1949 }
1950 #endif
1951 #endif
/* */
root/drivers/sound/ad1848.c

DEFINITIONS
