This source file includes following definitions.
- xchg_u32
- xchg_u64
- __xchg
1 #ifndef __ALPHA_SYSTEM_H
2 #define __ALPHA_SYSTEM_H
3
4 #include <asm/pal.h>
5
6
7
8
9
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12
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15
16
17
18 #define BOOT_PCB 0x20000000
19 #define BOOT_ADDR 0x20000000
20 #define BOOT_SIZE (16*1024)
21
22 #define KERNEL_START 0xfffffc0000300000
23 #define SWAPPER_PGD 0xfffffc0000300000
24 #define INIT_STACK 0xfffffc0000302000
25 #define EMPTY_PGT 0xfffffc0000304000
26 #define EMPTY_PGE 0xfffffc0000308000
27 #define ZERO_PGE 0xfffffc000030A000
28
29 #define START_ADDR 0xfffffc0000310000
30 #define START_SIZE (2*1024*1024)
31
32 #ifndef __ASSEMBLY__
33
34
35
36
37
38 struct el_common {
39 unsigned int size;
40 int sbz1 : 31;
41 char retry : 1;
42 unsigned int proc_offset;
43 unsigned int sys_offset;
44 };
45
46 extern void wrent(void *, unsigned long);
47 extern void wrkgp(unsigned long);
48 extern void wrusp(unsigned long);
49 extern unsigned long rdusp(void);
50 extern unsigned long rdmces (void);
51 extern void wrmces (unsigned long);
52
53 #define halt() __asm__ __volatile__ ("call_pal %0" : : "i" (PAL_halt) : "memory")
54
55 extern void alpha_switch_to(unsigned long pctxp);
56
57 #define switch_to(p) do { \
58 current_set[0] = p; \
59 alpha_switch_to((unsigned long) &(p)->tss - 0xfffffc0000000000); \
60 } while (0)
61
62 extern void imb(void);
63
64 #define mb() \
65 __asm__ __volatile__("mb": : :"memory")
66
67 #define draina() \
68 __asm__ __volatile__ ("call_pal %0" : : "i" (PAL_draina) : "memory")
69
70 #define getipl() \
71 ({ unsigned long __old_ipl; \
72 __asm__ __volatile__( \
73 "call_pal 54\n\t" \
74 "bis $0,$0,%0" \
75 : "=r" (__old_ipl) \
76 : : "$0", "$1", "$16", "$22", "$23", "$24", "$25"); \
77 __old_ipl; })
78
79 #define setipl(__new_ipl) \
80 __asm__ __volatile__( \
81 "bis %0,%0,$16\n\t" \
82 "call_pal 53" \
83 : : "r" (__new_ipl) \
84 : "$0", "$1", "$16", "$22", "$23", "$24", "$25", "memory")
85
86 #define swpipl(__new_ipl) \
87 ({ unsigned long __old_ipl; \
88 __asm__ __volatile__( \
89 "bis %1,%1,$16\n\t" \
90 "call_pal 53\n\t" \
91 "bis $0,$0,%0" \
92 : "=r" (__old_ipl) \
93 : "r" (__new_ipl) \
94 : "$0", "$1", "$16", "$22", "$23", "$24", "$25", "memory"); \
95 __old_ipl; })
96
97 #define cli() setipl(7)
98 #define sti() setipl(0)
99 #define save_flags(flags) do { flags = getipl(); } while (0)
100 #define restore_flags(flags) setipl(flags)
101
102
103
104
105 extern void tbi(long type, ...);
106
107 #define tbisi(x) tbi(1,(x))
108 #define tbisd(x) tbi(2,(x))
109 #define tbis(x) tbi(3,(x))
110 #define tbiap() tbi(-1)
111 #define tbia() tbi(-2)
112
113
114
115
116 extern __inline__ unsigned long xchg_u32 (volatile int * m, unsigned long val);
117 extern __inline__ unsigned long xchg_u64 (volatile long * m, unsigned long val);
118
119 extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
120 {
121 unsigned long dummy, dummy2;
122
123 __asm__ __volatile__(
124 "\n1:\t"
125 "ldl_l %0,0(%1)\n\t"
126 "bis %2,%2,%3\n\t"
127 "stl_c %3,0(%1)\n\t"
128 "beq %3,1b\n"
129 : "=r" (val), "=r" (m), "=r" (dummy), "=r" (dummy2)
130 : "1" (m), "2" (val)
131 : "memory");
132 return val;
133 }
134
135 extern __inline__ unsigned long xchg_u64(volatile long * m, unsigned long val)
136 {
137 unsigned long dummy, dummy2;
138
139 __asm__ __volatile__(
140 "\n1:\t"
141 "ldq_l %0,0(%1)\n\t"
142 "bis %2,%2,%3\n\t"
143 "stq_c %3,0(%1)\n\t"
144 "beq %3,1b\n"
145 : "=r" (val), "=r" (m), "=r" (dummy), "=r" (dummy2)
146 : "1" (m), "2" (val)
147 : "memory");
148 return val;
149 }
150
151 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
152 #define tas(ptr) (xchg((ptr),1))
153
154
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160
161
162 extern void __xchg_called_with_bad_pointer(void);
163
164 static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
165 {
166 switch (size) {
167 case 4:
168 return xchg_u32(ptr, x);
169 case 8:
170 return xchg_u64(ptr, x);
171 }
172 __xchg_called_with_bad_pointer();
173 return x;
174 }
175
176 #endif
177
178 #endif