include/asm-alpha/fpu.h

/* */
   1 #ifndef __ASM_ALPHA_FPU_H
   2 #define __ASM_ALPHA_FPU_H
   3 
   4 /*
   5  * Alpha floating-point control register defines:
   6  */
   7 #define FPCR_INVD       (1UL<<49)       /* invalid op disable (opt.) */
   8 #define FPCR_DZED       (1UL<<50)       /* division by zero disable (opt.) */
   9 #define FPCR_OVFD       (1UL<<51)       /* overflow disable (optional) */
  10 #define FPCR_INV        (1UL<<52)       /* invalid operation */
  11 #define FPCR_DZE        (1UL<<53)       /* division by zero */
  12 #define FPCR_OVF        (1UL<<54)       /* overflow */
  13 #define FPCR_UNF        (1UL<<55)       /* underflow */
  14 #define FPCR_INE        (1UL<<56)       /* inexact */
  15 #define FPCR_IOV        (1UL<<57)       /* integer overflow */
  16 #define FPCR_UNDZ       (1UL<<60)       /* underflow to zero (opt.) */
  17 #define FPCR_UNFD       (1UL<<61)       /* underflow disable (opt.) */
  18 #define FPCR_INED       (1UL<<62)       /* inexact disable (opt.) */
  19 #define FPCR_SUM        (1UL<<63)       /* summary bit */
  20 
  21 #define FPCR_DYN_SHIFT  58              /* first dynamic rounding mode bit */
  22 #define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT)      /* towards 0 */
  23 #define FPCR_DYN_MINUS   (0x1UL << FPCR_DYN_SHIFT)      /* towards -INF */
  24 #define FPCR_DYN_NORMAL  (0x2UL << FPCR_DYN_SHIFT)      /* towards nearest */
  25 #define FPCR_DYN_PLUS    (0x3UL << FPCR_DYN_SHIFT)      /* towards +INF */
  26 #define FPCR_DYN_MASK    (0x3UL << FPCR_DYN_SHIFT)
  27 
  28 #define FPCR_MASK       0xfffe000000000000
  29 
  30 /*
  31  * IEEE trap enables are implemented in software.  These per-thread
  32  * bits are stored in the "flags" field of "struct thread_struct".
  33  * Thus, the bits are defined so as not to conflict with the
  34  * floating-point enable bit (which is architected).  On top of that,
  35  * we want to make these bits compatible with OSF/1 so
  36  * ieee_set_fp_control() etc. can be implemented easily and
  37  * compatibly.  The corresponding definitions are in
  38  * /usr/include/machine/fpu.h under OSF/1.
  39  */
  40 #define IEEE_TRAP_ENABLE_INV    (1<<1)  /* invalid op */
  41 #define IEEE_TRAP_ENABLE_DZE    (1<<2)  /* division by zero */
  42 #define IEEE_TRAP_ENABLE_OVF    (1<<3)  /* overflow */
  43 #define IEEE_TRAP_ENABLE_UNF    (1<<4)  /* underflow */
  44 #define IEEE_TRAP_ENABLE_INE    (1<<5)  /* inexact */
  45 #define IEEE_TRAP_ENABLE_MASK   (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\
  46                                  IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\
  47                                  IEEE_TRAP_ENABLE_INE)
  48 
  49 /* status bits coming from fpcr: */
  50 #define IEEE_STATUS_INV         (1<<17)
  51 #define IEEE_STATUS_DZE         (1<<18)
  52 #define IEEE_STATUS_OVF         (1<<19)
  53 #define IEEE_STATUS_UNF         (1<<20)
  54 #define IEEE_STATUS_INE         (1<<21)
  55 
  56 #define IEEE_STATUS_MASK        (IEEE_STATUS_INV | IEEE_STATUS_DZE |    \
  57                                  IEEE_STATUS_OVF | IEEE_STATUS_UNF |    \
  58                                  IEEE_STATUS_INE)
  59 
  60 #define IEEE_STATUS_TO_EXCSUM_SHIFT     16
  61 
  62 #define IEEE_INHERIT    (1UL<<63)       /* inherit on thread create? */
  63 
  64 #endif /* __ASM_ALPHA_FPU_H */
/* */
root/include/asm-alpha/fpu.h

INCLUDED FROM
