root/drivers/net/ibmtr.h

/* */

INCLUDED FROM

   1 /* Definitions for an IBM Token Ring card. */
   2 /* This file is distributed under the GNU GPL   */
   3 
   4 #define TR_RETRY_INTERVAL 500
   5 #define TR_ISA 1
   6 #define TR_MCA 2
   7 #define TR_ISAPNP 3
   8 #define NOTOK 0
   9 #define TOKDEBUG 1
  10 
  11 /* Mike Eckhoff -- 96/02/08 */
  12 /* This defines the minimum timeout. If a transmission takes */
  13 /* longer then TX_TIMEOUT to send, we will wait and retry. */
  14 /* On large networks, this value may need to be increased. */
  15 /* We will start at .2s because that is what most drivers seem to be doing */
  16 /* now and the original value of .05s was not nearly enough for large nets. */
  17 
  18 #define TX_TIMEOUT (HZ/5)
  19 
  20 
  21 #ifndef IBMTR_SHARED_RAM_BASE
  22 #define IBMTR_SHARED_RAM_BASE 0xD0
  23 #define IBMTR_SHARED_RAM_SIZE 0x10
  24 #endif
  25 
  26 #define CHANNEL_ID      0X1F30
  27 #define AIP             0X1F00
  28 #define AIPCHKSUM1      0X1F60
  29 #define AIPCHKSUM2      0X1FF0
  30 #define AIPADAPTYPE     0X1FA0
  31 #define AIPDATARATE     0X1FA2
  32 #define AIPEARLYTOKEN   0X1FA4
  33 #define AIPAVAILSHRAM   0X1FA6
  34 #define AIPSHRAMPAGE    0X1FA8
  35 #define AIP4MBDHB       0X1FAA
  36 #define AIP16MBDHB      0X1FAC
  37 #define AIPFID          0X1FBA
  38 
  39 /* Note, 0xA20 == 0x220 since motherboard decodes 10 bits.  I left everything
  40    the way my documentation had it, ie: 0x0A20.     */
  41 #define ADAPTINTCNTRL   0x02f0  /* Adapter interrupt control */
  42 #define ADAPTRESET      0x1     /* Control Adapter reset (add to base) */
  43 #define ADAPTRESETREL   0x2     /* Release Adapter from reset ( """)  */
  44 #define ADAPTINTREL     0x3     /* Adapter interrupt release */
  45 
  46 #define MMIOStartLocP   0x0a20  /* Primary adapter's starting MMIO area */
  47 #define MMIOStartLocA   0x0a24  /* Alternate adapter's starting MMIO area */
  48 
  49 #define TR_IO_EXTENT    4       /* size of used IO range */
  50 
  51 #define GLOBAL_INT_ENABLE 0x02f0
  52 
  53 /* MMIO bits 0-4 select register */
  54 #define RRR_EVEN        0x00    /* Shared RAM relocation registers - even and odd */
  55 /* Used to set the starting address of shared RAM  */
  56 /* Bits 1 through 7 of this register map to bits 13 through 19 of the shared RAM address.*/
  57 /* ie: 0x02 sets RAM address to ...ato!  issy su wazzoo !! GODZILLA!!! */
  58 #define RRR_ODD         0x01
  59 /* Bits 2 and 3 of this register can be read to determine shared RAM size */
  60 /* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k  */
  61 #define WRBR_EVEN       0x02    /* Write region base registers - even and odd */
  62 #define WRBR_ODD        0x03
  63 #define WWCR_EVEN       0x04    /* Write window close registers - even and odd */
  64 #define WWCR_ODD        0x05
  65 #define WWOR_EVEN       0x06    /* Write window open registers - even and odd */
  66 #define WWOR_ODD        0x07
  67 
  68 /* Interrupt status registers - PC system  - even and odd */
  69 #define ISRP_EVEN       0x08
  70 
  71 #define TCR_INT 0x10    /* Bit 4 - Timer interrupt.  The TVR_EVEN timer has
  72                                                                    expired. */
  73 #define ERR_INT 0x08    /* Bit 3 - Error interrupt.  The adapter has had an
  74                                                                    internal error. */
  75 #define ACCESS_INT 0x04    /* Bit 2 - Access interrupt.  You have attempted to
  76                                                            write to an invalid area of shared RAM or an invalid
  77                                                                    register within the MMIO. */
  78 /*      In addition, the following bits within ISRP_EVEN can be turned on or off by you */
  79 /*      to control the interrupt processing:   */
  80 #define INT_IRQ 0x80    /* Bit 7 - If 0 the adapter will issue a CHCK, if 1 and
  81                                                               IRQ.  This should normally be set (by you) to 1.  */
  82 #define INT_ENABLE 0x40 /* Bit 6 - Interrupt enable.  If 0, no interrupts will
  83                                                                    occur.  If 1, interrupts will occur normally.
  84                                                                    Normally set to 1.  */
  85 /* Bit 0 - Primary or alternate adapter.  Set to zero if this adapter is the primary adapter,*/
  86 /*         1 if this adapter is the alternate adapter. */
  87 
  88 
  89 #define ISRP_ODD        0x09
  90 
  91 #define ADAP_CHK_INT 0x40 /* Bit 6 - Adapter check.  the adapter has
  92                              encountered a serious problem and has closed
  93                              itself.  Whoa.  */
  94 #define SRB_RESP_INT 0x20 /* Bit 5 - SRB response.  The adapter has accepted
  95                              an SRB request and set the return code withing
  96                              the SRB. */
  97 #define ASB_FREE_INT 0x10 /* Bit 4 - ASB free.  The adapter has read the ASB
  98                                                                           and this area can be safely reused. This interrupt
  99                                                                           is only used if your application has set the ASB
 100                                                                           free request bit in ISRA_ODD or if an error was
 101                                                                 detected in your response. */
 102 #define ARB_CMD_INT  0x08 /* Bit 3 - ARB command.  The adapter has given you a
 103                                                                           command for action.  The command is located in the
 104                                                                           ARB area of shared memory. */
 105 #define SSB_RESP_INT 0x04 /* Bit 2 - SSB response.  The adapter has posted a
 106                                                                           response to your SRB (the response is located in
 107                                                                           the SSB area of shared memory). */
 108 /* Bit 1 - Bridge frame forward complete. */
 109 
 110 
 111 
 112 #define ISRA_EVEN       0x0A    /* Interrupt status registers - adapter  - even and odd */
 113 /* Bit 7 - Internal parity error (on adapter's internal bus) */
 114 /* Bit 6 - Timer interrupt pending */
 115 /* Bit 5 - Access interrupt (attempt by adapter to access illegal address) */
 116 /* Bit 4 - Adapter microcode problem (microcode dead-man timer expired) */
 117 /* Bit 3 - Adapter processor check status */
 118 /* Bit 2 - Reserved */
 119 /* Bit 1 - Adapter hardware interrupt mask (prevents internal interrupts) */
 120 /* Bit 0 - Adapter software interrupt mask (prevents internal software interrupts) */
 121 
 122 #define ISRA_ODD        0x0B
 123 #define CMD_IN_SRB 0x20 /* Bit 5  - Indicates that you have placed a new
 124                            command in the SRB and are ready for the adapter to
 125                            process the command. */
 126 #define RESP_IN_ASB 0x10 /* Bit 4 - Indicates that you have placed a response
 127                                                                     (an ASB) in the shared RAM which is available for
 128                                                                          the adapter's use. */
 129 /* Bit 3 - Indicates that you are ready to ut an SRB in the shared RAM, but that a previous */
 130 /*         command is still pending.  The adapter will then interrupt you when the previous */
 131 /*         command is completed */
 132 /* Bit 2 - Indicates that you are ready to put an ASB in the shared RAM, but that a previous */
 133 /*         ASB is still pending.  The adapter will then interrupt you when the previous ASB */
 134 /*         is copied.  */
 135 #define ARB_FREE 0x2
 136 #define SSB_FREE 0x1
 137 
 138 #define TCR_EVEN        0x0C    /* Timer control registers - even and odd */
 139 #define TCR_ODD         0x0D
 140 #define TVR_EVEN        0x0E    /* Timer value registers - even and odd */
 141 #define TVR_ODD         0x0F
 142 #define SRPR_EVEN       0x10    /* Shared RAM paging registers - even and odd */
 143 #define SRPR_ENABLE_PAGING 0xc0
 144 #define SRPR_ODD        0x11 /* Not used. */
 145 #define TOKREAD         0x60
 146 #define TOKOR           0x40
 147 #define TOKAND          0x20
 148 #define TOKWRITE        0x00
 149 
 150 /* MMIO bits 5-6 select operation */
 151 /* 00 is used to write to a register */
 152 /* 01 is used to bitwise AND a byte with a register */
 153 /* 10 is used to bitwise OR a byte with a register  */
 154 /* 11 is used to read from a register */
 155 
 156 /* MMIO bits 7-8 select area of interest.. see below */
 157 /* 00 selects attachment control area. */
 158 /* 01 is reserved. */
 159 /* 10 selects adapter identification area A containing the adapter encoded address. */
 160 /* 11 selects the adapter identification area B containing test patterns. */
 161 
 162 #define PCCHANNELID 5049434F3631313039393020
 163 #define MCCHANNELID 4D4152533633583435313820
 164 
 165 #define ACA_OFFSET 0x1e00
 166 #define ACA_SET 0x40
 167 #define ACA_RESET 0x20
 168 #define ACA_RW 0x00
 169 
 170 #ifdef ENABLE_PAGING
 171 #define SET_PAGE(x) (*(unsigned char *) \
 172                          (ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN)\
 173                                                 = (x>>8)&ti.page_mask)
 174 #else
 175 #define SET_PAGE(x)
 176 #endif
 177 
 178 typedef enum { IN_PROGRESS, SUCCES, FAILURE, CLOSED } open_state;
 179 
 180 struct tok_info {
 181         unsigned char irq;
 182         unsigned char *mmio;
 183         unsigned char hw_address[32];
 184         unsigned char adapter_type;
 185         unsigned char data_rate;
 186         unsigned char token_release;
 187         unsigned char avail_shared_ram;
 188         unsigned char shared_ram_paging;
 189         unsigned char dhb_size4mb;
 190         unsigned char dhb_size16mb;
 191 /* Additions by David Morris       */
 192         unsigned char do_tok_int;
 193 #define FIRST_INT 1
 194 #define NOT_FIRST 2
 195         struct wait_queue *wait_for_tok_int;
 196         struct wait_queue *wait_for_reset;
 197         unsigned char sram_base;
 198 /* Additions by Peter De Schrijver */
 199         unsigned char page_mask;     /* mask to select RAM page to Map*/
 200         unsigned char mapped_ram_size;  /* size of RAM page */
 201         unsigned char *sram; /* Shared memory base address */
 202         unsigned char *init_srb;  /* Initial System Request Block address */
 203         unsigned char *srb;  /* System Request Block address */
 204         unsigned char *ssb;  /* System Status Block address */
 205         unsigned char *arb;  /* Adapter Request Block address */
 206         unsigned char *asb;  /* Adapter Status Block address */
 207         unsigned short exsap_station_id;
 208         unsigned short global_int_enable;
 209         struct sk_buff *current_skb;
 210         struct tr_statistics tr_stats;
 211         unsigned char auto_ringspeedsave;
 212         open_state open_status;
 213         
 214 };
 215 
 216 struct srb_init_response {
 217         unsigned char command;
 218         unsigned char init_status;
 219         unsigned char init_status_2;
 220         unsigned char reserved[3];
 221         unsigned short bring_up_code;
 222         unsigned short encoded_address;
 223         unsigned short level_address;
 224         unsigned short adapter_address;
 225         unsigned short parms_address;
 226         unsigned short mac_address;
 227 };
 228 
 229 #define DIR_OPEN_ADAPTER 0x03
 230 
 231 struct dir_open_adapter {
 232         unsigned char command;
 233         char reserved[7];
 234         unsigned short open_options;
 235         unsigned char node_address[6];
 236         unsigned char group_address[4];
 237         unsigned char funct_address[4];
 238         unsigned short num_rcv_buf;
 239         unsigned short rcv_buf_len;
 240         unsigned short dhb_length;
 241         unsigned char num_dhb;
 242         char reserved2;
 243         unsigned char dlc_max_sap;
 244         unsigned char dlc_max_sta;
 245         unsigned char dlc_max_gsap;
 246         unsigned char dlc_max_gmem;
 247         unsigned char dlc_t1_tick_1;
 248         unsigned char dlc_t2_tick_1;
 249         unsigned char dlc_ti_tick_1;
 250         unsigned char dlc_t1_tick_2;
 251         unsigned char dlc_t2_tick_2;
 252         unsigned char dlc_ti_tick_2;
 253         unsigned char product_id[18];
 254 };
 255 
 256 struct srb_open_response {
 257         unsigned char command;
 258         unsigned char reserved1;
 259         unsigned char ret_code;
 260         unsigned char reserved2[3];
 261         unsigned short error_code;
 262         unsigned short asb_addr;
 263         unsigned short srb_addr;
 264         unsigned short arb_addr;
 265         unsigned short ssb_addr;
 266 };
 267 
 268 /* DIR_OPEN_ADAPTER options */
 269 
 270 #define OPEN_PASS_BCON_MAC 0x0100
 271 #define NUM_RCV_BUF 16
 272 #define RCV_BUF_LEN 136
 273 #define DHB_LENGTH 2048
 274 #define NUM_DHB 2
 275 #define DLC_MAX_SAP 2
 276 #define DLC_MAX_STA 1
 277 
 278 #define DLC_OPEN_SAP 0x15
 279 
 280 struct dlc_open_sap {
 281         unsigned char command;
 282         unsigned char reserved1;
 283         unsigned char ret_code;
 284         unsigned char reserved2;
 285         unsigned short station_id;
 286         unsigned char timer_t1;
 287         unsigned char timer_t2;
 288         unsigned char timer_ti;
 289         unsigned char maxout;
 290         unsigned char maxin;
 291         unsigned char maxout_incr;
 292         unsigned char max_retry_count;
 293         unsigned char gsap_max_mem;
 294         unsigned short max_i_field;
 295         unsigned char sap_value;
 296         unsigned char sap_options;
 297         unsigned char station_count;
 298         unsigned char sap_gsap_mem;
 299         unsigned char gsap[0];
 300 };
 301 
 302 /* DLC_OPEN_SAP options */
 303 
 304 #define MAX_I_FIELD 0x0088
 305 #define SAP_OPEN_IND_SAP 0x04
 306 #define SAP_OPEN_PRIORITY 0x20
 307 #define SAP_OPEN_STATION_CNT 0x1
 308 
 309 #define XMIT_DIR_FRAME 0x0a
 310 #define XMIT_UI_FRAME  0x0d
 311 #define XMIT_XID_CMD   0x0e
 312 #define XMIT_TEST_CMD  0x11
 313 
 314 struct srb_xmit {
 315         unsigned char command;
 316         unsigned char cmd_corr;
 317         unsigned char ret_code;
 318         unsigned char reserved1;
 319         unsigned short station_id;
 320 };
 321 
 322 #define DIR_INTERRUPT 0x00
 323 struct srb_interrupt {
 324         unsigned char command;
 325         unsigned char cmd_corr;
 326         unsigned char ret_code;
 327 };
 328 
 329 #define DIR_READ_LOG 0x08
 330 struct srb_read_log {
 331         unsigned char command;
 332         unsigned char reserved1;
 333         unsigned char ret_code;
 334         unsigned char reserved2;
 335         unsigned char line_errors;
 336         unsigned char internal_errors;
 337         unsigned char burst_errors;
 338         unsigned char A_C_errors;
 339         unsigned char abort_delimiters;
 340         unsigned char reserved3;
 341         unsigned char lost_frames;
 342         unsigned char recv_congest_count;
 343         unsigned char frame_copied_errors;
 344         unsigned char frequency_errors;
 345         unsigned char token_errors;
 346 };
 347 
 348 struct asb_xmit_resp {
 349         unsigned char command;
 350         unsigned char cmd_corr;
 351         unsigned char ret_code;
 352         unsigned char reserved;
 353         unsigned short station_id;
 354         unsigned short frame_length;
 355         unsigned char hdr_length;
 356         unsigned        char rsap_value;
 357 };
 358 
 359 #define XMIT_DATA_REQ 0x82
 360 struct arb_xmit_req {
 361         unsigned char command;
 362         unsigned char cmd_corr;
 363         unsigned char reserved1[2];
 364         unsigned short station_id;
 365         unsigned short dhb_address;
 366 };
 367 
 368 #define REC_DATA 0x81
 369 struct arb_rec_req {
 370         unsigned char command;
 371         unsigned char reserved1[3];
 372         unsigned short station_id;
 373         unsigned short rec_buf_addr;
 374         unsigned char lan_hdr_len;
 375         unsigned char dlc_hdr_len;
 376         unsigned short frame_len;
 377         unsigned char msg_type;
 378 };
 379 
 380 #define DATA_LOST 0x20
 381 struct asb_rec {
 382         unsigned char command;
 383         unsigned char reserved1;
 384         unsigned char ret_code;
 385         unsigned char reserved2;
 386         unsigned short station_id;
 387         unsigned short rec_buf_addr;
 388 };
 389 
 390 struct rec_buf {
 391         unsigned char reserved1[2];
 392         unsigned short buf_ptr;
 393         unsigned char reserved2;
 394         unsigned short buf_len;
 395         unsigned char data[0];
 396 };
 397 
 398 #define DLC_STATUS          0x83
 399 struct arb_dlc_status {
 400         unsigned char command;
 401         unsigned char reserved1[3];
 402         unsigned short station_id;
 403         unsigned short status;
 404         unsigned char frmr_data[5];
 405         unsigned char access_prio;
 406         unsigned char rem_addr[TR_ALEN];
 407         unsigned        char rsap_value;
 408 };
 409 
 410 #define RING_STAT_CHANGE    0x84
 411 struct arb_ring_stat_change {
 412         unsigned char command;
 413         unsigned char reserved1[5];
 414         unsigned short ring_status;
 415 };
 416 
 417 #define DIR_CLOSE_ADAPTER   0x04
 418 struct srb_close_adapter {
 419         unsigned char command;
 420         unsigned char reserved1;
 421         unsigned char ret_code;
 422 };
 423 
 424 #define DIR_MOD_OPEN_PARAMS 0x01
 425 #define DIR_SET_GRP_ADDR    0x06
 426 #define DIR_SET_FUNC_ADDR   0x07
 427 #define DLC_CLOSE_SAP       0x16
 428 
 429 
 430 #define SIGNAL_LOSS  0x8000
 431 #define HARD_ERROR   0x4000
 432 #define XMIT_BEACON  0x1000
 433 #define LOBE_FAULT   0x0800
 434 #define AUTO_REMOVAL 0x0400
 435 #define REMOVE_RECV  0x0100
 436 #define LOG_OVERFLOW 0x0080
 437 #define RING_RECOVER 0x0020
 438 

/* */