drivers/sound/ad1848.c

/* */
This source file includes following definitions.
ad_read
ad_write
wait_for_calibration
ad_mute
ad_unmute
ad_enter_MCE
ad_leave_MCE
ad1848_set_recmask
change_bits
ad1848_mixer_get
ad1848_mixer_set
ad1848_mixer_reset
ad1848_mixer_ioctl
ad1848_open
ad1848_close
set_speed
set_channels
set_format
ad1848_ioctl
ad1848_output_block
ad1848_start_input
ad1848_prepare_for_IO
ad1848_reset
ad1848_halt
ad1848_halt_input
ad1848_halt_output
ad1848_trigger
ad1848_detect
ad1848_init
ad1848_unload
ad1848_interrupt
check_opl3
probe_ms_sound
attach_ms_sound
unload_ms_sound
probe_pnp_ad1848
attach_pnp_ad1848
unload_pnp_ad1848
ad1848_tmr_start
ad1848_tmr_reprogram
ad1848_tmr_disable
ad1848_tmr_restart
ad1848_tmr_install
   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  */
  16 
  17 /*
  18  * Copyright by Hannu Savolainen 1993-1996
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are
  22  * met: 1. Redistributions of source code must retain the above copyright
  23  * notice, this list of conditions and the following disclaimer. 2.
  24  * Redistributions in binary form must reproduce the above copyright notice,
  25  * this list of conditions and the following disclaimer in the documentation
  26  * and/or other materials provided with the distribution.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  29  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  30  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  32  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  */
  40 #include <linux/config.h>
  41 
  42 
  43 #define DEB(x)
  44 #define DEB1(x)
  45 #include "sound_config.h"
  46 
  47 #if defined(CONFIG_AD1848)
  48 
  49 #include "ad1848_mixer.h"
  50 
  51 typedef struct
  52   {
  53     int             base;
  54     int             irq;
  55     int             dual_dma;   /* 1, when two DMA channels allocated */
  56     unsigned char   MCE_bit;
  57     unsigned char   saved_regs[16];
  58     int             debug_flag;
  59 
  60     int             speed;
  61     unsigned char   speed_bits;
  62     int             channels;
  63     int             audio_format;
  64     unsigned char   format_bits;
  65 
  66     int             xfer_count;
  67     int             irq_mode;
  68     int             intr_active;
  69     int             opened;
  70     char           *chip_name;
  71     int             mode;
  72 #define MD_1848         1
  73 #define MD_4231         2
  74 #define MD_4231A        3
  75 #define MD_1845         4
  76 #define MD_4232         5
  77 
  78     /* Mixer parameters */
  79     int             recmask;
  80     int             supported_devices;
  81     int             supported_rec_devices;
  82     unsigned short  levels[32];
  83     int             dev_no;
  84     volatile unsigned long timer_ticks;
  85     int             timer_running;
  86     int             irq_ok;
  87     int            *osp;
  88   }
  89 
  90 ad1848_info;
  91 
  92 static int      nr_ad1848_devs = 0;
  93 static volatile char irq2dev[17] =
  94 {-1, -1, -1, -1, -1, -1, -1, -1,
  95  -1, -1, -1, -1, -1, -1, -1, -1, -1};
  96 
  97 static int      timer_installed = -1;
  98 
  99 static char     mixer2codec[MAX_MIXER_DEV] =
 100 {0};
 101 
 102 static int      ad_format_mask[6 /*devc->mode */ ] =
 103 {
 104   0,
 105   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 106   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 107   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 108   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,     /* AD1845 */
 109   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM
 110 };
 111 
 112 static ad1848_info dev_info[MAX_AUDIO_DEV];
 113 
 114 #define io_Index_Addr(d)        ((d)->base)
 115 #define io_Indexed_Data(d)      ((d)->base+1)
 116 #define io_Status(d)            ((d)->base+2)
 117 #define io_Polled_IO(d)         ((d)->base+3)
 118 
 119 static int      ad1848_open (int dev, int mode);
 120 static void     ad1848_close (int dev);
 121 static int      ad1848_ioctl (int dev, unsigned int cmd, caddr_t arg, int local);
 122 static void     ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 123 static void     ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 124 static int      ad1848_prepare_for_IO (int dev, int bsize, int bcount);
 125 static void     ad1848_reset (int dev);
 126 static void     ad1848_halt (int dev);
 127 static void     ad1848_halt_input (int dev);
 128 static void     ad1848_halt_output (int dev);
 129 static void     ad1848_trigger (int dev, int bits);
 130 static int      ad1848_tmr_install (int dev);
 131 static void     ad1848_tmr_reprogram (int dev);
 132 
 133 static int
 134 ad_read (ad1848_info * devc, int reg)
     /*  */
 135 {
 136   unsigned long   flags;
 137   int             x;
 138   int             timeout = 900000;
 139 
 140   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 141     timeout--;
 142 
 143   save_flags (flags);
 144   cli ();
 145   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 146   x = inb (io_Indexed_Data (devc));
 147   /*  printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
 148   restore_flags (flags);
 149 
 150   return x;
 151 }
 152 
 153 static void
 154 ad_write (ad1848_info * devc, int reg, int data)
     /*  */
 155 {
 156   unsigned long   flags;
 157   int             timeout = 90000;
 158 
 159   while (timeout > 0 &&
 160          inb (devc->base) == 0x80)      /*Are we initializing */
 161     timeout--;
 162 
 163   save_flags (flags);
 164   cli ();
 165   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 166   outb ((unsigned char) (data & 0xff), io_Indexed_Data (devc));
 167   /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
 168   restore_flags (flags);
 169 }
 170 
 171 static void
 172 wait_for_calibration (ad1848_info * devc)
     /*  */
 173 {
 174   int             timeout = 0;
 175 
 176   /*
 177      * Wait until the auto calibration process has finished.
 178      *
 179      * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 180      * 2)       Wait until the ACI bit of I11 gets on and then off.
 181    */
 182 
 183   timeout = 100000;
 184   while (timeout > 0 && inb (devc->base) & 0x80)
 185     timeout--;
 186   if (inb (devc->base) & 0x80)
 187     printk ("ad1848: Auto calibration timed out(1).\n");
 188 
 189   timeout = 100;
 190   while (timeout > 0 && !(ad_read (devc, 11) & 0x20))
 191     timeout--;
 192   if (!(ad_read (devc, 11) & 0x20))
 193     return;
 194 
 195   timeout = 20000;
 196   while (timeout > 0 && ad_read (devc, 11) & 0x20)
 197     timeout--;
 198   if (ad_read (devc, 11) & 0x20)
 199     printk ("ad1848: Auto calibration timed out(3).\n");
 200 }
 201 
 202 static void
 203 ad_mute (ad1848_info * devc)
     /*  */
 204 {
 205   int             i;
 206   unsigned char   prev;
 207 
 208   /*
 209      * Save old register settings and mute output channels
 210    */
 211   for (i = 6; i < 8; i++)
 212     {
 213       prev = devc->saved_regs[i] = ad_read (devc, i);
 214       ad_write (devc, i, prev | 0x80);
 215     }
 216 }
 217 
 218 static void
 219 ad_unmute (ad1848_info * devc)
     /*  */
 220 {
 221   int             i;
 222 
 223   /*
 224      * Restore back old volume registers (unmute)
 225    */
 226   for (i = 6; i < 8; i++)
 227     {
 228       ad_write (devc, i, devc->saved_regs[i] & ~0x80);
 229     }
 230 }
 231 
 232 static void
 233 ad_enter_MCE (ad1848_info * devc)
     /*  */
 234 {
 235   unsigned long   flags;
 236   int             timeout = 1000;
 237   unsigned short  prev;
 238 
 239   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 240     timeout--;
 241 
 242   save_flags (flags);
 243   cli ();
 244 
 245   devc->MCE_bit = 0x40;
 246   prev = inb (io_Index_Addr (devc));
 247   if (prev & 0x40)
 248     {
 249       restore_flags (flags);
 250       return;
 251     }
 252 
 253   outb (devc->MCE_bit, io_Index_Addr (devc));
 254   restore_flags (flags);
 255 }
 256 
 257 static void
 258 ad_leave_MCE (ad1848_info * devc)
     /*  */
 259 {
 260   unsigned long   flags;
 261   unsigned char   prev;
 262   int             timeout = 1000;
 263 
 264   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 265     timeout--;
 266 
 267   save_flags (flags);
 268   cli ();
 269 
 270   devc->MCE_bit = 0x00;
 271   prev = inb (io_Index_Addr (devc));
 272   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 273 
 274   if ((prev & 0x40) == 0)       /* Not in MCE mode */
 275     {
 276       restore_flags (flags);
 277       return;
 278     }
 279 
 280   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 281   wait_for_calibration (devc);
 282   restore_flags (flags);
 283 }
 284 
 285 
 286 static int
 287 ad1848_set_recmask (ad1848_info * devc, int mask)
     /*  */
 288 {
 289   unsigned char   recdev;
 290   int             i, n;
 291 
 292   mask &= devc->supported_rec_devices;
 293 
 294   n = 0;
 295   for (i = 0; i < 32; i++)      /* Count selected device bits */
 296     if (mask & (1 << i))
 297       n++;
 298 
 299   if (n == 0)
 300     mask = SOUND_MASK_MIC;
 301   else if (n != 1)              /* Too many devices selected */
 302     {
 303       mask &= ~devc->recmask;   /* Filter out active settings */
 304 
 305       n = 0;
 306       for (i = 0; i < 32; i++)  /* Count selected device bits */
 307         if (mask & (1 << i))
 308           n++;
 309 
 310       if (n != 1)
 311         mask = SOUND_MASK_MIC;
 312     }
 313 
 314   switch (mask)
 315     {
 316     case SOUND_MASK_MIC:
 317       recdev = 2;
 318       break;
 319 
 320     case SOUND_MASK_LINE:
 321     case SOUND_MASK_LINE3:
 322       recdev = 0;
 323       break;
 324 
 325     case SOUND_MASK_CD:
 326     case SOUND_MASK_LINE1:
 327       recdev = 1;
 328       break;
 329 
 330     case SOUND_MASK_IMIX:
 331       recdev = 3;
 332       break;
 333 
 334     default:
 335       mask = SOUND_MASK_MIC;
 336       recdev = 2;
 337     }
 338 
 339   recdev <<= 6;
 340   ad_write (devc, 0, (ad_read (devc, 0) & 0x3f) | recdev);
 341   ad_write (devc, 1, (ad_read (devc, 1) & 0x3f) | recdev);
 342 
 343   devc->recmask = mask;
 344   return mask;
 345 }
 346 
 347 static void
 348 change_bits (unsigned char *regval, int dev, int chn, int newval)
     /*  */
 349 {
 350   unsigned char   mask;
 351   int             shift;
 352 
 353   if (mix_devices[dev][chn].polarity == 1)      /* Reverse */
 354     newval = 100 - newval;
 355 
 356   mask = (1 << mix_devices[dev][chn].nbits) - 1;
 357   shift = mix_devices[dev][chn].bitpos;
 358   newval = (int) ((newval * mask) + 50) / 100;  /* Scale it */
 359 
 360   *regval &= ~(mask << shift);  /* Clear bits */
 361   *regval |= (newval & mask) << shift;  /* Set new value */
 362 }
 363 
 364 static int
 365 ad1848_mixer_get (ad1848_info * devc, int dev)
     /*  */
 366 {
 367   if (!((1 << dev) & devc->supported_devices))
 368     return -EINVAL;
 369 
 370   return devc->levels[dev];
 371 }
 372 
 373 static int
 374 ad1848_mixer_set (ad1848_info * devc, int dev, int value)
     /*  */
 375 {
 376   int             left = value & 0x000000ff;
 377   int             right = (value & 0x0000ff00) >> 8;
 378   int             retvol;
 379 
 380   int             regoffs;
 381   unsigned char   val;
 382 
 383   if (left > 100)
 384     left = 100;
 385   if (right > 100)
 386     right = 100;
 387 
 388   if (mix_devices[dev][RIGHT_CHN].nbits == 0)   /* Mono control */
 389     right = left;
 390 
 391   retvol = left | (left << 8);
 392 
 393   /* Scale volumes */
 394   left = mix_cvt[left];
 395   right = mix_cvt[right];
 396 
 397   /* Scale it again */
 398   left = mix_cvt[left];
 399   right = mix_cvt[right];
 400 
 401   if (dev > 31)
 402     return -EINVAL;
 403 
 404   if (!(devc->supported_devices & (1 << dev)))
 405     return -EINVAL;
 406 
 407   if (mix_devices[dev][LEFT_CHN].nbits == 0)
 408     return -EINVAL;
 409 
 410   devc->levels[dev] = retvol;
 411 
 412   /*
 413      * Set the left channel
 414    */
 415 
 416   regoffs = mix_devices[dev][LEFT_CHN].regno;
 417   val = ad_read (devc, regoffs);
 418   change_bits (&val, dev, LEFT_CHN, left);
 419   ad_write (devc, regoffs, val);
 420   devc->saved_regs[regoffs] = val;
 421 
 422   /*
 423      * Set the right channel
 424    */
 425 
 426   if (mix_devices[dev][RIGHT_CHN].nbits == 0)
 427     return retvol;              /* Was just a mono channel */
 428 
 429   regoffs = mix_devices[dev][RIGHT_CHN].regno;
 430   val = ad_read (devc, regoffs);
 431   change_bits (&val, dev, RIGHT_CHN, right);
 432   ad_write (devc, regoffs, val);
 433   devc->saved_regs[regoffs] = val;
 434 
 435   return retvol;
 436 }
 437 
 438 static void
 439 ad1848_mixer_reset (ad1848_info * devc)
     /*  */
 440 {
 441   int             i;
 442 
 443   switch (devc->mode)
 444     {
 445     case MD_4231:
 446       devc->supported_devices = MODE2_MIXER_DEVICES;
 447       break;
 448 
 449     case MD_4232:
 450       devc->supported_devices = MODE3_MIXER_DEVICES;
 451       break;
 452 
 453     default:
 454       devc->supported_devices = MODE1_MIXER_DEVICES;
 455     }
 456 
 457   devc->supported_rec_devices = MODE1_REC_DEVICES;
 458 
 459   for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 460     if (devc->supported_devices & (1 << i))
 461       ad1848_mixer_set (devc, i, default_mixer_levels[i]);
 462   ad1848_set_recmask (devc, SOUND_MASK_MIC);
 463 }
 464 
 465 static int
 466 ad1848_mixer_ioctl (int dev, unsigned int cmd, caddr_t arg)
     /*  */
 467 {
 468   ad1848_info    *devc;
 469 
 470   int             codec_dev = mixer2codec[dev];
 471 
 472   if (!codec_dev)
 473     return -ENXIO;
 474 
 475   codec_dev--;
 476 
 477   devc = (ad1848_info *) audio_devs[codec_dev]->devc;
 478 
 479   if (((cmd >> 8) & 0xff) == 'M')
 480     {
 481 
 482       if (_IOC_DIR (cmd) & _IOC_WRITE)
 483         switch (cmd & 0xff)
 484           {
 485           case SOUND_MIXER_RECSRC:
 486             return snd_ioctl_return ((int *) arg, ad1848_set_recmask (devc, get_fs_long ((long *) arg)));
 487             break;
 488 
 489           default:
 490             return snd_ioctl_return ((int *) arg, ad1848_mixer_set (devc, cmd & 0xff, get_fs_long ((long *) arg)));
 491           }
 492       else
 493         switch (cmd & 0xff)     /*
 494                                  * Return parameters
 495                                  */
 496           {
 497 
 498           case SOUND_MIXER_RECSRC:
 499             return snd_ioctl_return ((int *) arg, devc->recmask);
 500             break;
 501 
 502           case SOUND_MIXER_DEVMASK:
 503             return snd_ioctl_return ((int *) arg, devc->supported_devices);
 504             break;
 505 
 506           case SOUND_MIXER_STEREODEVS:
 507             return snd_ioctl_return ((int *) arg, devc->supported_devices & ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX));
 508             break;
 509 
 510           case SOUND_MIXER_RECMASK:
 511             return snd_ioctl_return ((int *) arg, devc->supported_rec_devices);
 512             break;
 513 
 514           case SOUND_MIXER_CAPS:
 515             return snd_ioctl_return ((int *) arg, SOUND_CAP_EXCL_INPUT);
 516             break;
 517 
 518           default:
 519             return snd_ioctl_return ((int *) arg, ad1848_mixer_get (devc, cmd & 0xff));
 520           }
 521     }
 522   else
 523     return -EINVAL;
 524 }
 525 
 526 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
 527 {
 528   {
 529     "Generic AD1848 codec",
 530     DMA_AUTOMODE,
 531     AFMT_U8,                    /* Will be set later */
 532     NULL,
 533     ad1848_open,
 534     ad1848_close,
 535     ad1848_output_block,
 536     ad1848_start_input,
 537     ad1848_ioctl,
 538     ad1848_prepare_for_IO,
 539     ad1848_prepare_for_IO,
 540     ad1848_reset,
 541     ad1848_halt,
 542     NULL,
 543     NULL,
 544     ad1848_halt_input,
 545     ad1848_halt_output,
 546     ad1848_trigger
 547   }};
 548 
 549 static struct mixer_operations ad1848_mixer_operations =
 550 {
 551   "AD1848/CS4248/CS4231",
 552   ad1848_mixer_ioctl
 553 };
 554 
 555 static int
 556 ad1848_open (int dev, int mode)
     /*  */
 557 {
 558   ad1848_info    *devc = NULL;
 559   unsigned long   flags;
 560 
 561   if (dev < 0 || dev >= num_audiodevs)
 562     return -ENXIO;
 563 
 564   devc = (ad1848_info *) audio_devs[dev]->devc;
 565 
 566 
 567   save_flags (flags);
 568   cli ();
 569   if (devc->opened)
 570     {
 571       restore_flags (flags);
 572       printk ("ad1848: Already opened\n");
 573       return -EBUSY;
 574     }
 575 
 576 
 577   devc->dual_dma = 0;
 578 
 579   if (audio_devs[dev]->flags & DMA_DUPLEX)
 580     {
 581       devc->dual_dma = 1;
 582     }
 583 
 584   devc->intr_active = 0;
 585   devc->opened = 1;
 586   devc->irq_mode = 0;
 587   ad1848_trigger (dev, 0);
 588   restore_flags (flags);
 589 /*
 590  * Mute output until the playback really starts. This decreases clicking.
 591  */
 592   ad_mute (devc);
 593 
 594   return 0;
 595 }
 596 
 597 static void
 598 ad1848_close (int dev)
     /*  */
 599 {
 600   unsigned long   flags;
 601   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 602 
 603   DEB (printk ("ad1848_close(void)\n"));
 604 
 605   save_flags (flags);
 606   cli ();
 607 
 608   devc->intr_active = 0;
 609   ad1848_reset (dev);
 610 
 611 
 612   devc->opened = 0;
 613   devc->irq_mode = 0;
 614 
 615   ad_unmute (devc);
 616   restore_flags (flags);
 617 }
 618 
 619 static int
 620 set_speed (ad1848_info * devc, int arg)
     /*  */
 621 {
 622   /*
 623      * The sampling speed is encoded in the least significant nible of I8. The
 624      * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
 625      * three bits select the divisor (indirectly):
 626      *
 627      * The available speeds are in the following table. Keep the speeds in
 628      * the increasing order.
 629    */
 630   typedef struct
 631   {
 632     int             speed;
 633     unsigned char   bits;
 634   }
 635   speed_struct;
 636 
 637   static speed_struct speed_table[] =
 638   {
 639     {5510, (0 << 1) | 1},
 640     {5510, (0 << 1) | 1},
 641     {6620, (7 << 1) | 1},
 642     {8000, (0 << 1) | 0},
 643     {9600, (7 << 1) | 0},
 644     {11025, (1 << 1) | 1},
 645     {16000, (1 << 1) | 0},
 646     {18900, (2 << 1) | 1},
 647     {22050, (3 << 1) | 1},
 648     {27420, (2 << 1) | 0},
 649     {32000, (3 << 1) | 0},
 650     {33075, (6 << 1) | 1},
 651     {37800, (4 << 1) | 1},
 652     {44100, (5 << 1) | 1},
 653     {48000, (6 << 1) | 0}
 654   };
 655 
 656   int             i, n, selected = -1;
 657 
 658   n = sizeof (speed_table) / sizeof (speed_struct);
 659 
 660   if (devc->mode == MD_1845)    /* AD1845 has different timer than others */
 661     {
 662       if (arg < 4000)
 663         arg = 4000;
 664       if (arg > 50000)
 665         arg = 50000;
 666 
 667       devc->speed = arg;
 668       devc->speed_bits = speed_table[3].bits;
 669       return devc->speed;
 670     }
 671 
 672   if (arg < speed_table[0].speed)
 673     selected = 0;
 674   if (arg > speed_table[n - 1].speed)
 675     selected = n - 1;
 676 
 677   for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 678     if (speed_table[i].speed == arg)
 679       selected = i;
 680     else if (speed_table[i].speed > arg)
 681       {
 682         int             diff1, diff2;
 683 
 684         diff1 = arg - speed_table[i - 1].speed;
 685         diff2 = speed_table[i].speed - arg;
 686 
 687         if (diff1 < diff2)
 688           selected = i - 1;
 689         else
 690           selected = i;
 691       }
 692 
 693   if (selected == -1)
 694     {
 695       printk ("ad1848: Can't find speed???\n");
 696       selected = 3;
 697     }
 698 
 699   devc->speed = speed_table[selected].speed;
 700   devc->speed_bits = speed_table[selected].bits;
 701   return devc->speed;
 702 }
 703 
 704 static int
 705 set_channels (ad1848_info * devc, int arg)
     /*  */
 706 {
 707   if (arg != 1 && arg != 2)
 708     return devc->channels;
 709 
 710   devc->channels = arg;
 711   return arg;
 712 }
 713 
 714 static int
 715 set_format (ad1848_info * devc, int arg)
     /*  */
 716 {
 717 
 718   static struct format_tbl
 719   {
 720     int             format;
 721     unsigned char   bits;
 722   }
 723   format2bits[] =
 724   {
 725     {
 726       0, 0
 727     }
 728     ,
 729     {
 730       AFMT_MU_LAW, 1
 731     }
 732     ,
 733     {
 734       AFMT_A_LAW, 3
 735     }
 736     ,
 737     {
 738       AFMT_IMA_ADPCM, 5
 739     }
 740     ,
 741     {
 742       AFMT_U8, 0
 743     }
 744     ,
 745     {
 746       AFMT_S16_LE, 2
 747     }
 748     ,
 749     {
 750       AFMT_S16_BE, 6
 751     }
 752     ,
 753     {
 754       AFMT_S8, 0
 755     }
 756     ,
 757     {
 758       AFMT_U16_LE, 0
 759     }
 760     ,
 761     {
 762       AFMT_U16_BE, 0
 763     }
 764   };
 765   int             i, n = sizeof (format2bits) / sizeof (struct format_tbl);
 766 
 767   if (!(arg & ad_format_mask[devc->mode]))
 768     arg = AFMT_U8;
 769 
 770   devc->audio_format = arg;
 771 
 772   for (i = 0; i < n; i++)
 773     if (format2bits[i].format == arg)
 774       {
 775         if ((devc->format_bits = format2bits[i].bits) == 0)
 776           return devc->audio_format = AFMT_U8;  /* Was not supported */
 777 
 778         return arg;
 779       }
 780 
 781   /* Still hanging here. Something must be terribly wrong */
 782   devc->format_bits = 0;
 783   return devc->audio_format = AFMT_U8;
 784 }
 785 
 786 static int
 787 ad1848_ioctl (int dev, unsigned int cmd, caddr_t arg, int local)
     /*  */
 788 {
 789   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 790 
 791   switch (cmd)
 792     {
 793     case SOUND_PCM_WRITE_RATE:
 794       if (local)
 795         return set_speed (devc, (int) arg);
 796       return snd_ioctl_return ((int *) arg, set_speed (devc, get_fs_long ((long *) arg)));
 797 
 798     case SOUND_PCM_READ_RATE:
 799       if (local)
 800         return devc->speed;
 801       return snd_ioctl_return ((int *) arg, devc->speed);
 802 
 803     case SNDCTL_DSP_STEREO:
 804       if (local)
 805         return set_channels (devc, (int) arg + 1) - 1;
 806       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg) + 1) - 1);
 807 
 808     case SOUND_PCM_WRITE_CHANNELS:
 809       if (local)
 810         return set_channels (devc, (int) arg);
 811       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg)));
 812 
 813     case SOUND_PCM_READ_CHANNELS:
 814       if (local)
 815         return devc->channels;
 816       return snd_ioctl_return ((int *) arg, devc->channels);
 817 
 818     case SNDCTL_DSP_SAMPLESIZE:
 819       if (local)
 820         return set_format (devc, (int) arg);
 821       return snd_ioctl_return ((int *) arg, set_format (devc, get_fs_long ((long *) arg)));
 822 
 823     case SOUND_PCM_READ_BITS:
 824       if (local)
 825         return devc->audio_format;
 826       return snd_ioctl_return ((int *) arg, devc->audio_format);
 827 
 828     default:;
 829     }
 830   return -EINVAL;
 831 }
 832 
 833 static void
 834 ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 835 {
 836   unsigned long   flags, cnt;
 837   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 838 
 839   cnt = count;
 840 
 841   if (devc->audio_format == AFMT_IMA_ADPCM)
 842     {
 843       cnt /= 4;
 844     }
 845   else
 846     {
 847       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 848         cnt >>= 1;
 849     }
 850   if (devc->channels > 1)
 851     cnt >>= 1;
 852   cnt--;
 853 
 854   if (devc->irq_mode & PCM_ENABLE_OUTPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 855       intrflag &&
 856       cnt == devc->xfer_count)
 857     {
 858       devc->irq_mode |= PCM_ENABLE_OUTPUT;
 859       devc->intr_active = 1;
 860       return;                   /*
 861                                  * Auto DMA mode on. No need to react
 862                                  */
 863     }
 864   save_flags (flags);
 865   cli ();
 866 
 867   if (dma_restart)
 868     {
 869       ad_write (devc, 9, ad_read (devc, 9) & ~0x01);    /* Playback disable */
 870       /* ad1848_halt (dev); */
 871       DMAbuf_start_dma (dev, buf, count, DMA_MODE_WRITE);
 872     }
 873 
 874   ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 875   ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 876 
 877   ad_unmute (devc);
 878 
 879   devc->xfer_count = cnt;
 880   devc->irq_mode |= PCM_ENABLE_OUTPUT;
 881   devc->intr_active = 1;
 882   restore_flags (flags);
 883 }
 884 
 885 static void
 886 ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 887 {
 888   unsigned long   flags, cnt;
 889   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 890 
 891   cnt = count;
 892   if (devc->audio_format == AFMT_IMA_ADPCM)
 893     {
 894       cnt /= 4;
 895     }
 896   else
 897     {
 898       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 899         cnt >>= 1;
 900     }
 901   if (devc->channels > 1)
 902     cnt >>= 1;
 903   cnt--;
 904 
 905   if (devc->irq_mode & PCM_ENABLE_INPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 906       intrflag &&
 907       cnt == devc->xfer_count)
 908     {
 909       devc->irq_mode |= PCM_ENABLE_INPUT;
 910       devc->intr_active = 1;
 911       return;                   /*
 912                                  * Auto DMA mode on. No need to react
 913                                  */
 914     }
 915   save_flags (flags);
 916   cli ();
 917 
 918   if (dma_restart)
 919     {
 920       /* ad1848_halt (dev); */
 921       ad_write (devc, 9, ad_read (devc, 9) & ~0x02);    /* Capture disable */
 922       DMAbuf_start_dma (dev, buf, count, DMA_MODE_READ);
 923     }
 924 
 925   if (devc->mode == MD_1848 || !devc->dual_dma)         /* Single DMA channel mode */
 926     {
 927       ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 928       ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 929     }
 930   else
 931     /* Dual DMA channel mode */
 932     {
 933       ad_write (devc, 31, (unsigned char) (cnt & 0xff));
 934       ad_write (devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
 935     }
 936 
 937   ad_unmute (devc);
 938 
 939   devc->xfer_count = cnt;
 940   devc->irq_mode |= PCM_ENABLE_INPUT;
 941   devc->intr_active = 1;
 942   restore_flags (flags);
 943 }
 944 
 945 static int
 946 ad1848_prepare_for_IO (int dev, int bsize, int bcount)
     /*  */
 947 {
 948   int             timeout;
 949   unsigned char   fs, old_fs;
 950   unsigned long   flags;
 951   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 952 
 953   if (devc->irq_mode)
 954     return 0;
 955 
 956   save_flags (flags);
 957   cli ();
 958   fs = devc->speed_bits | (devc->format_bits << 5);
 959 
 960   if (devc->channels > 1)
 961     fs |= 0x10;
 962 
 963   if (devc->mode == MD_1845)    /* Use alternate speed select registers */
 964     {
 965       fs &= 0xf0;               /* Mask off the rate select bits */
 966 
 967       ad_write (devc, 22, (devc->speed >> 8) & 0xff);   /* Speed MSB */
 968       ad_write (devc, 23, devc->speed & 0xff);  /* Speed LSB */
 969     }
 970 
 971   old_fs = ad_read (devc, 8);
 972 
 973   if (fs == old_fs)             /* No change */
 974     {
 975       restore_flags (flags);
 976       devc->xfer_count = 0;
 977       return 0;
 978     }
 979 
 980   ad_enter_MCE (devc);          /* Enables changes to the format select reg */
 981 
 982   ad_write (devc, 8, fs);
 983   /*
 984    * Write to I8 starts resyncronization. Wait until it completes.
 985    */
 986   timeout = 10000;
 987   while (timeout > 0 && inb (devc->base) == 0x80)
 988     timeout--;
 989 
 990   /*
 991      * If mode == 2 (CS4231), set I28 also. It's the capture format register.
 992    */
 993   if (devc->mode != MD_1848)
 994     {
 995       ad_write (devc, 28, fs);
 996 
 997       /*
 998          * Write to I28 starts resyncronization. Wait until it completes.
 999        */
1000       timeout = 10000;
1001       while (timeout > 0 && inb (devc->base) == 0x80)
1002         timeout--;
1003 
1004     }
1005 
1006   ad_leave_MCE (devc);          /*
1007                                  * Starts the calibration process.
1008                                  */
1009   restore_flags (flags);
1010   devc->xfer_count = 0;
1011 
1012 #ifdef CONFIG_SEQUENCER
1013   if (dev == timer_installed && devc->timer_running)
1014     if ((fs & 0x01) != (old_fs & 0x01))
1015       {
1016         ad1848_tmr_reprogram (dev);
1017       }
1018 #endif
1019   return 0;
1020 }
1021 
1022 static void
1023 ad1848_reset (int dev)
     /*  */
1024 {
1025   ad1848_halt (dev);
1026 }
1027 
1028 static void
1029 ad1848_halt (int dev)
     /*  */
1030 {
1031   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1032   unsigned long   flags;
1033   int             timeout;
1034 
1035 
1036   save_flags (flags);
1037   cli ();
1038 
1039   ad_mute (devc);
1040   ad_enter_MCE (devc);
1041   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1042   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1043 
1044   ad_write (devc, 15, 4);       /* Clear DMA counter */
1045   ad_write (devc, 14, 0);       /* Clear DMA counter */
1046 
1047   if (devc->mode != MD_1848)
1048     {
1049       ad_write (devc, 30, 4);   /* Clear DMA counter */
1050       ad_write (devc, 31, 0);   /* Clear DMA counter */
1051     }
1052 
1053   for (timeout = 0; timeout < 10000 && !(inb (io_Status (devc)) & 0x80);
1054        timeout++);              /* Wait for interrupt */
1055 
1056   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1057   outb (0, io_Status (devc));   /* Clear interrupt status */
1058   outb (0, io_Status (devc));   /* Clear interrupt status */
1059   devc->irq_mode = 0;
1060   ad_leave_MCE (devc);
1061 
1062   /* DMAbuf_reset_dma (dev); */
1063   restore_flags (flags);
1064 }
1065 
1066 static void
1067 ad1848_halt_input (int dev)
     /*  */
1068 {
1069   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1070   unsigned long   flags;
1071 
1072   if (devc->mode == MD_1848)
1073     {
1074       ad1848_halt (dev);
1075       return;
1076     }
1077 
1078   save_flags (flags);
1079   cli ();
1080 
1081   ad_mute (devc);
1082   ad_write (devc, 9, ad_read (devc, 9) & ~0x02);        /* Stop capture */
1083 
1084 
1085   outb (0, io_Status (devc));   /* Clear interrupt status */
1086   outb (0, io_Status (devc));   /* Clear interrupt status */
1087 
1088   devc->irq_mode &= ~PCM_ENABLE_INPUT;
1089 
1090   restore_flags (flags);
1091 }
1092 
1093 static void
1094 ad1848_halt_output (int dev)
     /*  */
1095 {
1096   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1097   unsigned long   flags;
1098 
1099   if (devc->mode == MD_1848)
1100     {
1101       ad1848_halt (dev);
1102       return;
1103     }
1104 
1105   save_flags (flags);
1106   cli ();
1107 
1108   ad_mute (devc);
1109   ad_write (devc, 9, ad_read (devc, 9) & ~0x01);        /* Stop playback */
1110 
1111 
1112   outb (0, io_Status (devc));   /* Clear interrupt status */
1113   outb (0, io_Status (devc));   /* Clear interrupt status */
1114 
1115   devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1116 
1117   restore_flags (flags);
1118 }
1119 
1120 static void
1121 ad1848_trigger (int dev, int state)
     /*  */
1122 {
1123   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1124   unsigned long   flags;
1125   unsigned char   tmp;
1126 
1127   save_flags (flags);
1128   cli ();
1129   state &= devc->irq_mode;
1130 
1131   tmp = ad_read (devc, 9) & ~0x03;
1132   if (state & PCM_ENABLE_INPUT)
1133     tmp |= 0x02;
1134   if (state & PCM_ENABLE_OUTPUT)
1135     tmp |= 0x01;
1136   ad_write (devc, 9, tmp);
1137 
1138   restore_flags (flags);
1139 }
1140 
1141 int
1142 ad1848_detect (int io_base, int *ad_flags, int *osp)
     /*  */
1143 {
1144 
1145   unsigned char   tmp;
1146   int             i;
1147   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1148   unsigned char   tmp1 = 0xff, tmp2 = 0xff;
1149 
1150   DDB (printk ("ad1848_detect(%x)\n", io_base));
1151 
1152   if (ad_flags)
1153     *ad_flags = 0;
1154 
1155   if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1156     {
1157       DDB (printk ("ad1848 detect error - step 0\n"));
1158       return 0;
1159     }
1160   if (check_region (io_base, 4))
1161     {
1162       printk ("\n\nad1848.c: Port %x not free.\n\n", io_base);
1163       return 0;
1164     }
1165 
1166   devc->base = io_base;
1167   devc->irq_ok = 0;
1168   devc->timer_running = 0;
1169   devc->MCE_bit = 0x40;
1170   devc->irq = 0;
1171   devc->opened = 0;
1172   devc->chip_name = "AD1848";
1173   devc->mode = MD_1848;         /* AD1848 or CS4248 */
1174   devc->osp = osp;
1175   devc->debug_flag = 0;
1176 
1177   /*
1178      * Check that the I/O address is in use.
1179      *
1180      * The bit 0x80 of the base I/O port is known to be 0 after the
1181      * chip has performed it's power on initialization. Just assume
1182      * this has happened before the OS is starting.
1183      *
1184      * If the I/O address is unused, it typically returns 0xff.
1185    */
1186 
1187   DDB (printk ("ad1848_detect() - step A\n"));
1188   if ((inb (devc->base) & 0x80) != 0x00)        /* Not a AD1848 */
1189     {
1190       DDB (printk ("ad1848 detect error - step A (%02x)\n",
1191                    inb (devc->base)));
1192       return 0;
1193     }
1194 
1195   /*
1196      * Test if it's possible to change contents of the indirect registers.
1197      * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1198      * so try to avoid using it.
1199    */
1200 
1201   DDB (printk ("ad1848_detect() - step B\n"));
1202   ad_write (devc, 0, 0xaa);
1203   ad_write (devc, 1, 0x45);     /* 0x55 with bit 0x10 clear */
1204 
1205   if ((tmp1 = ad_read (devc, 0)) != 0xaa || (tmp2 = ad_read (devc, 1)) != 0x45)
1206     {
1207       DDB (printk ("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1208       return 0;
1209     }
1210 
1211   DDB (printk ("ad1848_detect() - step C\n"));
1212   ad_write (devc, 0, 0x45);
1213   ad_write (devc, 1, 0xaa);
1214 
1215   if ((tmp1 = ad_read (devc, 0)) != 0x45 || (tmp2 = ad_read (devc, 1)) != 0xaa)
1216     {
1217       DDB (printk ("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1218       return 0;
1219     }
1220 
1221   /*
1222      * The indirect register I12 has some read only bits. Lets
1223      * try to change them.
1224    */
1225 
1226   DDB (printk ("ad1848_detect() - step D\n"));
1227   tmp = ad_read (devc, 12);
1228   ad_write (devc, 12, (~tmp) & 0x0f);
1229 
1230   if ((tmp & 0x0f) != ((tmp1 = ad_read (devc, 12)) & 0x0f))
1231     {
1232       DDB (printk ("ad1848 detect error - step D (%x)\n", tmp1));
1233       return 0;
1234     }
1235 
1236   /*
1237      * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1238      *   0x01=RevB and 0x0A=RevC.
1239    */
1240 
1241   /*
1242      * The original AD1848/CS4248 has just 15 indirect registers. This means
1243      * that I0 and I16 should return the same value (etc.).
1244      * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1245      * with CS4231.
1246    */
1247 
1248   DDB (printk ("ad1848_detect() - step F\n"));
1249   ad_write (devc, 12, 0);       /* Mode2=disabled */
1250 
1251   for (i = 0; i < 16; i++)
1252     if ((tmp1 = ad_read (devc, i)) != (tmp2 = ad_read (devc, i + 16)))
1253       {
1254         DDB (printk ("ad1848 detect error - step F(%d/%x/%x)\n", i, tmp1, tmp2));
1255         return 0;
1256       }
1257 
1258   /*
1259      * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1260      * The bit 0x80 is always 1 in CS4248 and CS4231.
1261    */
1262 
1263   DDB (printk ("ad1848_detect() - step G\n"));
1264   ad_write (devc, 12, 0x40);    /* Set mode2, clear 0x80 */
1265 
1266   tmp1 = ad_read (devc, 12);
1267   if (tmp1 & 0x80)
1268     {
1269       if (ad_flags)
1270         *ad_flags |= AD_F_CS4248;
1271 
1272       devc->chip_name = "CS4248";       /* Our best knowledge just now */
1273     }
1274 
1275   if ((tmp1 & 0xc0) == (0x80 | 0x40))
1276     {
1277       /*
1278          *      CS4231 detected - is it?
1279          *
1280          *      Verify that setting I0 doesn't change I16.
1281        */
1282       DDB (printk ("ad1848_detect() - step H\n"));
1283       ad_write (devc, 16, 0);   /* Set I16 to known value */
1284 
1285       ad_write (devc, 0, 0x45);
1286       if ((tmp1 = ad_read (devc, 16)) != 0x45)  /* No change -> CS4231? */
1287         {
1288 
1289           ad_write (devc, 0, 0xaa);
1290           if ((tmp1 = ad_read (devc, 16)) == 0xaa)      /* Rotten bits? */
1291             {
1292               DDB (printk ("ad1848 detect error - step H(%x)\n", tmp1));
1293               return 0;
1294             }
1295 
1296           /*
1297              * Verify that some bits of I25 are read only.
1298            */
1299 
1300           DDB (printk ("ad1848_detect() - step I\n"));
1301           tmp1 = ad_read (devc, 25);    /* Original bits */
1302           ad_write (devc, 25, ~tmp1);   /* Invert all bits */
1303           if ((ad_read (devc, 25) & 0xe7) == (tmp1 & 0xe7))
1304             {
1305               int             id;
1306 
1307               /*
1308                *      It's at least CS4231
1309                */
1310               devc->chip_name = "CS4231";
1311 
1312               devc->mode = MD_4231;
1313 
1314               /*
1315                * It could be an AD1845 or CS4231A as well.
1316                * CS4231 and AD1845 report the same revision info in I25
1317                * while the CS4231A reports different.
1318                */
1319 
1320               DDB (printk ("ad1848_detect() - step I\n"));
1321               id = ad_read (devc, 25) & 0xe7;
1322 
1323               switch (id)
1324                 {
1325 
1326                 case 0xa0:
1327                   devc->chip_name = "CS4231A";
1328                   devc->mode = MD_4231A;
1329                   break;
1330 
1331                 case 0xa2:
1332                   devc->chip_name = "CS4232";
1333                   devc->mode = MD_4232;
1334                   break;
1335 
1336                 case 0xb2:
1337                   devc->chip_name = "CS4232A";
1338                   devc->mode = MD_4232;
1339                   break;
1340 
1341                 case 0x80:
1342                   {
1343                     /* 
1344                      * It must be a CS4231 or AD1845. The register I23 of
1345                      * CS4231 is undefined and it appears to be read only.
1346                      * AD1845 uses I23 for setting sample rate. Assume
1347                      * the chip is AD1845 if I23 is changeable.
1348                      */
1349 
1350                     unsigned char   tmp = ad_read (devc, 23);
1351 
1352                     ad_write (devc, 23, ~tmp);
1353                     if (ad_read (devc, 23) != tmp)      /* AD1845 ? */
1354                       {
1355                         devc->chip_name = "AD1845";
1356                         devc->mode = MD_1845;
1357                       }
1358 
1359                     ad_write (devc, 23, tmp);   /* Restore */
1360                   }
1361                   break;
1362 
1363                 default:        /* Assume CS4231 */
1364                   devc->mode = MD_4231;
1365 
1366                 }
1367             }
1368           ad_write (devc, 25, tmp1);    /* Restore bits */
1369 
1370           DDB (printk ("ad1848_detect() - step K\n"));
1371         }
1372     }
1373 
1374   DDB (printk ("ad1848_detect() - step L\n"));
1375   if (ad_flags)
1376     {
1377       if (devc->mode != MD_1848)
1378         *ad_flags |= AD_F_CS4231;
1379     }
1380 
1381   DDB (printk ("ad1848_detect() - Detected OK\n"));
1382   return 1;
1383 }
1384 
1385 void
1386 ad1848_init (char *name, int io_base, int irq, int dma_playback, int dma_capture, int share_dma, int *osp)
     /*  */
1387 {
1388   /*
1389      * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1390      *   so that this driver doesn't need to allocate/deallocate it.
1391      *   The actually used IRQ is ABS(irq).
1392    */
1393 
1394   /*
1395      * Initial values for the indirect registers of CS4248/AD1848.
1396    */
1397   static int      init_values[] =
1398   {
1399     0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x80, 0x80,
1400     0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1401 
1402   /* Positions 16 to 31 just for CS4231 */
1403     0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1404     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1405   };
1406   int             i, my_dev;
1407 
1408   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1409 
1410   if (!ad1848_detect (io_base, NULL, osp))
1411     return;
1412 
1413   request_region (devc->base, 4, devc->chip_name);
1414 
1415   devc->irq = (irq > 0) ? irq : 0;
1416   devc->opened = 0;
1417   devc->timer_ticks = 0;
1418   devc->osp = osp;
1419 
1420   if (nr_ad1848_devs != 0)
1421     {
1422       memcpy ((char *) &ad1848_pcm_operations[nr_ad1848_devs],
1423               (char *) &ad1848_pcm_operations[0],
1424               sizeof (struct audio_operations));
1425     }
1426 
1427   for (i = 0; i < 16; i++)
1428     ad_write (devc, i, init_values[i]);
1429 
1430   ad_mute (devc);               /* Initialize some variables */
1431   ad_unmute (devc);             /* Leave it unmuted now */
1432 
1433   if (devc->mode > MD_1848)
1434     {
1435       if (dma_capture == dma_playback || dma_capture == -1 || dma_playback == -1)
1436         {
1437           ad_write (devc, 9, ad_read (devc, 9) | 0x04);         /* Single DMA mode */
1438           ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1439         }
1440       else
1441         {
1442           ad_write (devc, 9, ad_read (devc, 9) & ~0x04);        /* Dual DMA mode */
1443           ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_DUPLEX;
1444         }
1445 
1446       ad_write (devc, 12, ad_read (devc, 12) | 0x40);   /* Mode2 = enabled */
1447       for (i = 16; i < 32; i++)
1448         ad_write (devc, i, init_values[i]);
1449 
1450 
1451       if (devc->mode == MD_1845)
1452         ad_write (devc, 27, ad_read (devc, 27) | 0x08);         /* Alternate freq select enabled */
1453     }
1454   else
1455     {
1456       ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1457       ad_write (devc, 9, ad_read (devc, 9) | 0x04);     /* Single DMA mode */
1458     }
1459 
1460   outb (0, io_Status (devc));   /* Clear pending interrupts */
1461 
1462   if (name != NULL && name[0] != 0)
1463     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1464              "%s (%s)", name, devc->chip_name);
1465   else
1466     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1467              "Generic audio codec (%s)", devc->chip_name);
1468 
1469   conf_printf2 (ad1848_pcm_operations[nr_ad1848_devs].name,
1470                 devc->base, devc->irq, dma_playback, dma_capture);
1471 
1472   if (num_audiodevs < MAX_AUDIO_DEV)
1473     {
1474       audio_devs[my_dev = num_audiodevs++] = &ad1848_pcm_operations[nr_ad1848_devs];
1475       if (irq > 0)
1476         {
1477           audio_devs[my_dev]->devc = devc;
1478           irq2dev[irq] = devc->dev_no = my_dev;
1479           if (snd_set_irq_handler (devc->irq, ad1848_interrupt,
1480                                    audio_devs[my_dev]->name,
1481                                    devc->osp) < 0)
1482             {
1483               printk ("ad1848: IRQ in use\n");
1484             }
1485 
1486 #ifdef NO_IRQ_TEST
1487           if (devc->mode != MD_1848)
1488             {
1489               int             x;
1490               unsigned char   tmp = ad_read (devc, 16);
1491 
1492               devc->timer_ticks = 0;
1493 
1494               ad_write (devc, 21, 0x00);        /* Timer msb */
1495               ad_write (devc, 20, 0x10);        /* Timer lsb */
1496 
1497               ad_write (devc, 16, tmp | 0x40);  /* Enable timer */
1498               for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1499               ad_write (devc, 16, tmp & ~0x40);         /* Disable timer */
1500 
1501               if (devc->timer_ticks == 0)
1502                 printk ("[IRQ conflict???]");
1503               else
1504                 devc->irq_ok = 1;
1505 
1506             }
1507           else
1508             devc->irq_ok = 1;   /* Couldn't test. assume it's OK */
1509 #else
1510           devc->irq_ok = 1;
1511 #endif
1512         }
1513       else if (irq < 0)
1514         irq2dev[-irq] = devc->dev_no = my_dev;
1515 
1516       audio_devs[my_dev]->dmachan1 = dma_playback;
1517       audio_devs[my_dev]->dmachan2 = dma_capture;
1518       audio_devs[my_dev]->buffsize = DSP_BUFFSIZE;
1519       audio_devs[my_dev]->devc = devc;
1520       audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1521       nr_ad1848_devs++;
1522 
1523 #ifdef CONFIG_SEQUENCER
1524       if (devc->mode != MD_1848 && devc->irq_ok)
1525         ad1848_tmr_install (my_dev);
1526 #endif
1527 
1528       if (!share_dma)
1529         {
1530           if (sound_alloc_dma (dma_playback, "Sound System"))
1531             printk ("ad1848.c: Can't allocate DMA%d\n", dma_playback);
1532 
1533           if (dma_capture != dma_playback)
1534             if (sound_alloc_dma (dma_capture, "Sound System (capture)"))
1535               printk ("ad1848.c: Can't allocate DMA%d\n", dma_capture);
1536         }
1537 
1538       /*
1539          * Toggle the MCE bit. It completes the initialization phase.
1540        */
1541 
1542       ad_enter_MCE (devc);      /* In case the bit was off */
1543       ad_leave_MCE (devc);
1544 
1545       if (num_mixers < MAX_MIXER_DEV)
1546         {
1547           mixer2codec[num_mixers] = my_dev + 1;
1548           audio_devs[my_dev]->mixer_dev = num_mixers;
1549           mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1550           ad1848_mixer_reset (devc);
1551         }
1552     }
1553   else
1554     printk ("AD1848: Too many PCM devices available\n");
1555 }
1556 
1557 void
1558 ad1848_unload (int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
     /*  */
1559 {
1560   int             i, dev = 0;
1561   ad1848_info    *devc = NULL;
1562 
1563   for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
1564     if (dev_info[i].base == io_base)
1565       {
1566         devc = &dev_info[i];
1567         dev = devc->dev_no;
1568       }
1569 
1570   if (devc != NULL)
1571     {
1572       release_region (devc->base, 4);
1573 
1574       if (!share_dma)
1575         {
1576           if (irq > 0)
1577             snd_release_irq (devc->irq);
1578 
1579           sound_free_dma (audio_devs[dev]->dmachan1);
1580 
1581           if (audio_devs[dev]->dmachan2 != audio_devs[dev]->dmachan1)
1582             sound_free_dma (audio_devs[dev]->dmachan2);
1583         }
1584     }
1585   else
1586     printk ("ad1848: Can't find device to be undoaded. Base=%x\n",
1587             io_base);
1588 }
1589 
1590 void
1591 ad1848_interrupt (int irq, struct pt_regs *dummy)
     /*  */
1592 {
1593   unsigned char   status;
1594   ad1848_info    *devc;
1595   int             dev;
1596   int             alt_stat = 0xff;
1597 
1598   if (irq < 0 || irq > 15)
1599     {
1600       dev = -1;
1601     }
1602   else
1603     dev = irq2dev[irq];
1604 
1605   if (dev < 0 || dev >= num_audiodevs)
1606     {
1607       for (irq = 0; irq < 17; irq++)
1608         if (irq2dev[irq] != -1)
1609           break;
1610 
1611       if (irq > 15)
1612         {
1613           printk ("ad1848.c: Bogus interrupt %d\n", irq);
1614           return;
1615         }
1616 
1617       dev = irq2dev[irq];
1618       devc = (ad1848_info *) audio_devs[dev]->devc;
1619     }
1620   else
1621     devc = (ad1848_info *) audio_devs[dev]->devc;
1622 
1623   status = inb (io_Status (devc));
1624 
1625   if (status == 0x80)
1626     printk ("ad1848_interrupt: Why?\n");
1627 
1628   if (status & 0x01)
1629     {
1630 
1631       if (devc->mode != MD_1848)
1632         alt_stat = ad_read (devc, 24);
1633 
1634       if (devc->opened && devc->irq_mode & PCM_ENABLE_INPUT && alt_stat & 0x20)
1635         {
1636           DMAbuf_inputintr (dev);
1637         }
1638 
1639       if (devc->opened && devc->irq_mode & PCM_ENABLE_OUTPUT &&
1640           alt_stat & 0x10)
1641         {
1642           DMAbuf_outputintr (dev, 1);
1643         }
1644 
1645       if (devc->mode != MD_1848 && alt_stat & 0x40)     /* Timer interrupt */
1646         {
1647           devc->timer_ticks++;
1648 #ifdef CONFIG_SEQUENCER
1649           if (timer_installed == dev && devc->timer_running)
1650             sound_timer_interrupt ();
1651 #endif
1652         }
1653     }
1654 
1655   if (devc->mode != MD_1848)
1656     ad_write (devc, 24, ad_read (devc, 24) & ~alt_stat);        /* Selective ack */
1657   else
1658     outb (0, io_Status (devc)); /* Clear interrupt status */
1659 }
1660 
1661 /*
1662  * Some extra code for the MS Sound System
1663  */
1664 
1665 void
1666 check_opl3 (int base, struct address_info *hw_config)
     /*  */
1667 {
1668 
1669 #ifdef CONFIG_YM3812
1670   if (check_region (base, 4))
1671     {
1672       printk ("\n\nopl3.c: I/O port %x already in use\n\n", base);
1673       return;
1674     }
1675 
1676   if (!opl3_detect (base, hw_config->osp))
1677     return;
1678 
1679   opl3_init (0, base, hw_config->osp);
1680   request_region (base, 4, "OPL3/OPL2");
1681 #endif
1682 }
1683 
1684 int
1685 probe_ms_sound (struct address_info *hw_config)
     /*  */
1686 {
1687   unsigned char   tmp;
1688 
1689   DDB (printk ("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
1690 
1691   if (check_region (hw_config->io_base, 8))
1692     {
1693       printk ("MSS: I/O port conflict\n");
1694       return 0;
1695     }
1696 
1697   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1698     {
1699       /* check_opl3(0x388, hw_config); */
1700       return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1701     }
1702 
1703   /*
1704      * Check if the IO port returns valid signature. The original MS Sound
1705      * system returns 0x04 while some cards (AudioTriX Pro for example)
1706      * return 0x00 or 0x0f.
1707    */
1708 
1709   if ((tmp = inb (hw_config->io_base + 3)) == 0xff)     /* Bus float */
1710     {
1711       DDB (printk ("I/O address is inactive (%x)\n", tmp));
1712       return 0;
1713     }
1714   if ((tmp & 0x3f) != 0x04 &&
1715       (tmp & 0x3f) != 0x0f &&
1716       (tmp & 0x3f) != 0x00)
1717     {
1718       DDB (printk ("No MSS signature detected on port 0x%x (0x%x)\n",
1719                    hw_config->io_base, inb (hw_config->io_base + 3)));
1720       return 0;
1721     }
1722 
1723   if (hw_config->irq > 11)
1724     {
1725       printk ("MSS: Bad IRQ %d\n", hw_config->irq);
1726       return 0;
1727     }
1728 
1729   if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
1730     {
1731       printk ("MSS: Bad DMA %d\n", hw_config->dma);
1732       return 0;
1733     }
1734 
1735   /*
1736      * Check that DMA0 is not in use with a 8 bit board.
1737    */
1738 
1739   if (hw_config->dma == 0 && inb (hw_config->io_base + 3) & 0x80)
1740     {
1741       printk ("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1742       return 0;
1743     }
1744 
1745   if (hw_config->irq > 7 && hw_config->irq != 9 && inb (hw_config->io_base + 3) & 0x80)
1746     {
1747       printk ("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1748       return 0;
1749     }
1750 
1751   return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1752 }
1753 
1754 long
1755 attach_ms_sound (long mem_start, struct address_info *hw_config)
     /*  */
1756 {
1757   static char     interrupt_bits[12] =
1758   {
1759     -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1760   };
1761   char            bits;
1762 
1763   static char     dma_bits[4] =
1764   {
1765     1, 2, 0, 3
1766   };
1767 
1768   int             config_port = hw_config->io_base + 0;
1769   int             version_port = hw_config->io_base + 3;
1770 
1771   if (!ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp))
1772     return mem_start;
1773 
1774   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1775     {
1776       ad1848_init ("MS Sound System", hw_config->io_base + 4,
1777                    hw_config->irq,
1778                    hw_config->dma,
1779                    hw_config->dma2, 0, hw_config->osp);
1780       request_region (hw_config->io_base, 4, "WSS config");
1781       return mem_start;
1782     }
1783 
1784   /*
1785      * Set the IRQ and DMA addresses.
1786    */
1787 
1788   bits = interrupt_bits[hw_config->irq];
1789   if (bits == -1)
1790     return mem_start;
1791 
1792   outb (bits | 0x40, config_port);
1793   if ((inb (version_port) & 0x40) == 0)
1794     printk ("[IRQ Conflict?]");
1795 
1796   outb (bits | dma_bits[hw_config->dma], config_port);  /* Write IRQ+DMA setup */
1797 
1798   ad1848_init ("MS Sound System", hw_config->io_base + 4,
1799                hw_config->irq,
1800                hw_config->dma,
1801                hw_config->dma, 0, hw_config->osp);
1802   request_region (hw_config->io_base, 4, "WSS config");
1803   return mem_start;
1804 }
1805 
1806 void
1807 unload_ms_sound (struct address_info *hw_config)
     /*  */
1808 {
1809   ad1848_unload (hw_config->io_base + 4,
1810                  hw_config->irq,
1811                  hw_config->dma,
1812                  hw_config->dma, 0);
1813   release_region (hw_config->io_base, 4);
1814 }
1815 
1816 /*
1817  * WSS compatible PnP codec support
1818  */
1819 
1820 int
1821 probe_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1822 {
1823   return ad1848_detect (hw_config->io_base, NULL, hw_config->osp);
1824 }
1825 
1826 long
1827 attach_pnp_ad1848 (long mem_start, struct address_info *hw_config)
     /*  */
1828 {
1829 
1830   ad1848_init (hw_config->name, hw_config->io_base,
1831                hw_config->irq,
1832                hw_config->dma,
1833                hw_config->dma2, 0, hw_config->osp);
1834   return mem_start;
1835 }
1836 
1837 void
1838 unload_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1839 {
1840   ad1848_unload (hw_config->io_base,
1841                  hw_config->irq,
1842                  hw_config->dma,
1843                  hw_config->dma2, 0);
1844   release_region (hw_config->io_base, 4);
1845 }
1846 
1847 #ifdef CONFIG_SEQUENCER
1848 /*
1849  * Timer stuff (for /dev/music).
1850  */
1851 
1852 static unsigned int current_interval = 0;
1853 
1854 static unsigned int
1855 ad1848_tmr_start (int dev, unsigned int usecs)
     /*  */
1856 {
1857   unsigned long   flags;
1858   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1859   unsigned long   xtal_nsecs;   /* nanoseconds per xtal oscillaror tick */
1860   unsigned long   divider;
1861 
1862   save_flags (flags);
1863   cli ();
1864 
1865 /*
1866  * Length of the timer interval (in nanoseconds) depends on the
1867  * selected crystal oscillator. Check this from bit 0x01 of I8.
1868  *
1869  * AD1845 has just one oscillator which has cycle time of 10.050 us
1870  * (when a 24.576 MHz xtal oscillator is used).
1871  *
1872  * Convert requested interval to nanoseconds before computing
1873  * the timer divider.
1874  */
1875 
1876   if (devc->mode == MD_1845)
1877     xtal_nsecs = 10050;
1878   else if (ad_read (devc, 8) & 0x01)
1879     xtal_nsecs = 9920;
1880   else
1881     xtal_nsecs = 9969;
1882 
1883   divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
1884 
1885   if (divider < 100)            /* Don't allow shorter intervals than about 1ms */
1886     divider = 100;
1887 
1888   if (divider > 65535)          /* Overflow check */
1889     divider = 65535;
1890 
1891   ad_write (devc, 21, (divider >> 8) & 0xff);   /* Set upper bits */
1892   ad_write (devc, 20, divider & 0xff);  /* Set lower bits */
1893   ad_write (devc, 16, ad_read (devc, 16) | 0x40);       /* Start the timer */
1894   devc->timer_running = 1;
1895   restore_flags (flags);
1896 
1897   return current_interval = (divider * xtal_nsecs + 500) / 1000;
1898 }
1899 
1900 static void
1901 ad1848_tmr_reprogram (int dev)
     /*  */
1902 {
1903 /*
1904  *    Audio driver has changed sampling rate so that a different xtal
1905  *      oscillator was selected. We have to reprogram the timer rate.
1906  */
1907 
1908   ad1848_tmr_start (dev, current_interval);
1909   sound_timer_syncinterval (current_interval);
1910 }
1911 
1912 static void
1913 ad1848_tmr_disable (int dev)
     /*  */
1914 {
1915   unsigned long   flags;
1916   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1917 
1918   save_flags (flags);
1919   cli ();
1920   ad_write (devc, 16, ad_read (devc, 16) & ~0x40);
1921   devc->timer_running = 0;
1922   restore_flags (flags);
1923 }
1924 
1925 static void
1926 ad1848_tmr_restart (int dev)
     /*  */
1927 {
1928   unsigned long   flags;
1929   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1930 
1931   if (current_interval == 0)
1932     return;
1933 
1934   save_flags (flags);
1935   cli ();
1936   ad_write (devc, 16, ad_read (devc, 16) | 0x40);
1937   devc->timer_running = 1;
1938   restore_flags (flags);
1939 }
1940 
1941 static struct sound_lowlev_timer ad1848_tmr =
1942 {
1943   0,
1944   ad1848_tmr_start,
1945   ad1848_tmr_disable,
1946   ad1848_tmr_restart
1947 };
1948 
1949 static int
1950 ad1848_tmr_install (int dev)
     /*  */
1951 {
1952 
1953   if (timer_installed != -1)
1954     return 0;                   /* Don't install another timer */
1955 
1956   timer_installed = ad1848_tmr.dev = dev;
1957   sound_timer_init (&ad1848_tmr, audio_devs[dev]->name);
1958 
1959   return 1;
1960 }
1961 #endif
1962 #endif
/* */
root/drivers/sound/ad1848.c

DEFINITIONS
