This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- get_hw_addr
- EISA_signature
- ewrk3_ioctl
- init_module
- cleanup_module
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138 static const char *version = "ewrk3.c:v0.41 96/1/20 davies@wanton.lkg.dec.com\n";
139
140 #include <linux/module.h>
141
142 #include <linux/kernel.h>
143 #include <linux/sched.h>
144 #include <linux/string.h>
145 #include <linux/ptrace.h>
146 #include <linux/errno.h>
147 #include <linux/ioport.h>
148 #include <linux/malloc.h>
149 #include <linux/interrupt.h>
150 #include <linux/delay.h>
151 #include <asm/bitops.h>
152 #include <asm/io.h>
153 #include <asm/dma.h>
154 #include <asm/segment.h>
155
156 #include <linux/netdevice.h>
157 #include <linux/etherdevice.h>
158 #include <linux/skbuff.h>
159
160 #include <linux/time.h>
161 #include <linux/types.h>
162 #include <linux/unistd.h>
163
164 #include "ewrk3.h"
165
166 #ifdef EWRK3_DEBUG
167 static int ewrk3_debug = EWRK3_DEBUG;
168 #else
169 static int ewrk3_debug = 1;
170 #endif
171
172 #define EWRK3_NDA 0xffe0
173
174 #define PROBE_LENGTH 32
175 #define ETH_PROM_SIG 0xAA5500FFUL
176
177 #ifndef EWRK3_SIGNATURE
178 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
179 #define EWRK3_STRLEN 8
180 #endif
181
182 #ifndef EWRK3_RAM_BASE_ADDRESSES
183 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
184 #endif
185
186
187
188
189 #define EWRK3_IO_BASE 0x100
190 #define EWRK3_IOP_INC 0x20
191 #define EWRK3_TOTAL_SIZE 0x20
192
193 #ifndef MAX_NUM_EWRK3S
194 #define MAX_NUM_EWRK3S 21
195 #endif
196
197 #ifndef EWRK3_EISA_IO_PORTS
198 #define EWRK3_EISA_IO_PORTS 0x0c00
199 #endif
200
201 #ifndef MAX_EISA_SLOTS
202 #define MAX_EISA_SLOTS 16
203 #define EISA_SLOT_INC 0x1000
204 #endif
205
206 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
207 #define CRC_POLYNOMIAL_LE 0xedb88320UL
208
209 #define QUEUE_PKT_TIMEOUT (1*HZ)
210
211
212
213
214 #define IO_ONLY 0x00
215 #define SHMEM_2K 0x800
216 #define SHMEM_32K 0x8000
217 #define SHMEM_64K 0x10000
218
219
220
221
222 #define ENABLE_IRQs { \
223 icr |= lp->irq_mask;\
224 outb(icr, EWRK3_ICR); \
225 }
226
227 #define DISABLE_IRQs { \
228 icr = inb(EWRK3_ICR);\
229 icr &= ~lp->irq_mask;\
230 outb(icr, EWRK3_ICR); \
231 }
232
233
234
235
236 #define START_EWRK3 { \
237 csr = inb(EWRK3_CSR);\
238 csr &= ~(CSR_TXD|CSR_RXD);\
239 outb(csr, EWRK3_CSR); \
240 }
241
242 #define STOP_EWRK3 { \
243 csr = (CSR_TXD|CSR_RXD);\
244 outb(csr, EWRK3_CSR); \
245 }
246
247
248
249
250 #define EWRK3_PKT_STAT_SZ 16
251 #define EWRK3_PKT_BIN_SZ 128
252
253
254 struct ewrk3_private {
255 char adapter_name[80];
256 u_long shmem_base;
257 u_long shmem_length;
258 struct enet_statistics stats;
259 struct {
260 u32 bins[EWRK3_PKT_STAT_SZ];
261 u32 unicast;
262 u32 multicast;
263 u32 broadcast;
264 u32 excessive_collisions;
265 u32 tx_underruns;
266 u32 excessive_underruns;
267 } pktStats;
268 u_char irq_mask;
269 u_char mPage;
270 u_char lemac;
271 u_char hard_strapped;
272 u_char lock;
273 u_char txc;
274 u_char *mctbl;
275 };
276
277
278
279
280 #define FORCE_2K_MODE { \
281 shmem_length = SHMEM_2K;\
282 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
283 }
284
285
286
287
288 static int ewrk3_open(struct device *dev);
289 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
290 static void ewrk3_interrupt(int irq, void *dev_id, struct pt_regs *regs);
291 static int ewrk3_close(struct device *dev);
292 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
293 static void set_multicast_list(struct device *dev);
294 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
295
296
297
298
299 static int ewrk3_hw_init(struct device *dev, u_long iobase);
300 static void ewrk3_init(struct device *dev);
301 static int ewrk3_rx(struct device *dev);
302 static int ewrk3_tx(struct device *dev);
303
304 static void EthwrkSignature(char * name, char *eeprom_image);
305 static int DevicePresent(u_long iobase);
306 static void SetMulticastFilter(struct device *dev);
307 static int EISA_signature(char *name, s32 eisa_id);
308
309 static int Read_EEPROM(u_long iobase, u_char eaddr);
310 static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
311 static u_char get_hw_addr (struct device *dev, u_char *eeprom_image, char chipType);
312
313 static void isa_probe(struct device *dev, u_long iobase);
314 static void eisa_probe(struct device *dev, u_long iobase);
315 static struct device *alloc_device(struct device *dev, u_long iobase);
316
317
318 #ifdef MODULE
319 int init_module(void);
320 void cleanup_module(void);
321 static int autoprobed = 1, loading_module = 1;
322
323 # else
324 static u_char irq[] = {5,0,10,3,11,9,15,12};
325 static int autoprobed = 0, loading_module = 0;
326
327 #endif
328
329 static char name[EWRK3_STRLEN + 1];
330 static int num_ewrk3s = 0, num_eth = 0;
331
332
333
334
335 #define INIT_EWRK3 {\
336 outb(EEPROM_INIT, EWRK3_IOPR);\
337 udelay(1000);\
338 }
339
340
341
342
343 int ewrk3_probe(struct device *dev)
344 {
345 int tmp = num_ewrk3s, status = -ENODEV;
346 u_long iobase = dev->base_addr;
347
348 if ((iobase == 0) && loading_module){
349 printk("Autoprobing is not supported when loading a module based driver.\n");
350 status = -EIO;
351 } else {
352
353 isa_probe(dev, iobase);
354 eisa_probe(dev, iobase);
355
356 if ((tmp == num_ewrk3s) && (iobase != 0) && loading_module) {
357 printk("%s: ewrk3_probe() cannot find device at 0x%04lx.\n", dev->name,
358 iobase);
359 }
360
361
362
363
364
365 for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
366
367 if (dev->priv) status = 0;
368 if (iobase == 0) autoprobed = 1;
369 }
370
371 return status;
372 }
373
374 static int
375 ewrk3_hw_init(struct device *dev, u_long iobase)
376 {
377 struct ewrk3_private *lp;
378 int i, status=0;
379 u_long mem_start, shmem_length;
380 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
381 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
382
383
384
385
386
387 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
388 INIT_EWRK3;
389
390 nicsr = inb(EWRK3_CSR);
391
392 icr = inb(EWRK3_ICR);
393 icr &= 0x70;
394 outb(icr, EWRK3_ICR);
395
396 if (nicsr == CSR_TXD|CSR_RXD) {
397
398
399 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
400 union {
401 short val;
402 char c[2];
403 } tmp;
404
405 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
406 eeprom_image[i] = tmp.c[0];
407 eeprom_image[i+1] = tmp.c[1];
408 chksum += eeprom_image[i] + eeprom_image[i+1];
409 }
410
411 if (chksum != 0) {
412 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
413 status = -ENXIO;
414 } else {
415 EthwrkSignature(name, eeprom_image);
416 if (*name != '\0') {
417 dev->base_addr = iobase;
418
419 if (iobase > 0x400) {
420 outb(eisa_cr, EISA_CR);
421 }
422
423 lemac = eeprom_image[EEPROM_CHIPVER];
424 cmr = inb(EWRK3_CMR);
425
426 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
427 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
428 printk("%s: %s at %#4lx", dev->name, name, iobase);
429 hard_strapped = 1;
430 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
431
432 printk("%s: %s at %#4lx (EISA slot %ld)",
433 dev->name, name, iobase, ((iobase>>12)&0x0f));
434 } else {
435 printk("%s: %s at %#4lx", dev->name, name, iobase);
436 }
437
438 if (!status) {
439 printk(", h/w address ");
440 if (lemac!=LeMAC2) DevicePresent(iobase);
441 status = get_hw_addr(dev, eeprom_image, lemac);
442 for (i = 0; i < ETH_ALEN - 1; i++) {
443 printk("%2.2x:", dev->dev_addr[i]);
444 }
445 printk("%2.2x,\n", dev->dev_addr[i]);
446
447 if (status) {
448 printk(" which has an EEPROM CRC error.\n");
449 status = -ENXIO;
450 } else {
451 if (lemac == LeMAC2) {
452 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
453 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= CMR_RA;
454 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= CMR_WB;
455 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= CMR_POLARITY;
456 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= CMR_LINK;
457 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= CMR_0WS;
458 }
459 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= CMR_DRAM;
460 outb(cmr, EWRK3_CMR);
461
462 cr = inb(EWRK3_CR);
463 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
464 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
465 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
466 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
467 outb(cr, EWRK3_CR);
468
469
470
471
472
473 mem_start = inb(EWRK3_MBR);
474 shmem_length = 0;
475 if (mem_start != 0) {
476 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
477 mem_start *= SHMEM_64K;
478 shmem_length = SHMEM_64K;
479 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
480 mem_start *= SHMEM_32K;
481 shmem_length = SHMEM_32K;
482 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
483 mem_start = mem_start * SHMEM_2K + 0x80000;
484 shmem_length = SHMEM_2K;
485 } else {
486 status = -ENXIO;
487 }
488 }
489
490
491
492
493
494
495
496 if (!status) {
497 if (hard_strapped) {
498 printk(" is hard strapped.\n");
499 } else if (mem_start) {
500 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
501 printk(" at 0x%.5lx", mem_start);
502 } else {
503 printk(" is in I/O only mode");
504 }
505
506
507 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
508 GFP_KERNEL);
509 if (dev->priv == NULL) {
510 return -ENOMEM;
511 }
512 lp = (struct ewrk3_private *)dev->priv;
513 memset(dev->priv, 0, sizeof(struct ewrk3_private));
514 lp->shmem_base = mem_start;
515 lp->shmem_length = shmem_length;
516 lp->lemac = lemac;
517 lp->hard_strapped = hard_strapped;
518
519 lp->mPage = 64;
520 if (cmr & CMR_DRAM) lp->mPage <<= 1 ;
521
522 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
523 request_region(iobase, EWRK3_TOTAL_SIZE, lp->adapter_name);
524
525 lp->irq_mask = ICR_TNEM|ICR_TXDM|ICR_RNEM|ICR_RXDM;
526
527 if (!hard_strapped) {
528
529
530
531 icr |= ICR_IE;
532 outb(icr, EWRK3_ICR);
533
534
535 dev->dma = 0;
536
537
538
539 if (dev->irq < 2) {
540 #ifndef MODULE
541 u_char irqnum;
542
543 autoirq_setup(0);
544
545
546
547
548 icr |=ICR_TNEM;
549 outb(1,EWRK3_TDQ);
550 outb(icr, EWRK3_ICR);
551
552 irqnum = irq[((icr & IRQ_SEL) >> 4)];
553
554 dev->irq = autoirq_report(1);
555 if ((dev->irq) && (irqnum == dev->irq)) {
556 printk(" and uses IRQ%d.\n", dev->irq);
557 } else {
558 if (!dev->irq) {
559 printk(" and failed to detect IRQ line.\n");
560 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
561 printk(" and an illegal IRQ line detected.\n");
562 } else {
563 printk(", but incorrect IRQ line detected.\n");
564 }
565 status = -ENXIO;
566 }
567
568 DISABLE_IRQs;
569
570 #endif
571 } else {
572 printk(" and requires IRQ%d.\n", dev->irq);
573 }
574 }
575 if (status) release_region(iobase, EWRK3_TOTAL_SIZE);
576 } else {
577 status = -ENXIO;
578 }
579 }
580 }
581 } else {
582 status = -ENXIO;
583 }
584 }
585
586 if (!status) {
587 if (ewrk3_debug > 0) {
588 printk(version);
589 }
590
591
592 dev->open = &ewrk3_open;
593 dev->hard_start_xmit = &ewrk3_queue_pkt;
594 dev->stop = &ewrk3_close;
595 dev->get_stats = &ewrk3_get_stats;
596 dev->set_multicast_list = &set_multicast_list;
597 dev->do_ioctl = &ewrk3_ioctl;
598
599 dev->mem_start = 0;
600
601
602 ether_setup(dev);
603 }
604 } else {
605 status = -ENXIO;
606 }
607
608 return status;
609 }
610
611
612 static int
613 ewrk3_open(struct device *dev)
614 {
615 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
616 u_long iobase = dev->base_addr;
617 int i, status = 0;
618 u_char icr, csr;
619
620
621
622
623 STOP_EWRK3;
624
625 if (!lp->hard_strapped) {
626 irq2dev_map[dev->irq] = dev;
627
628 if (request_irq(dev->irq, (void *)ewrk3_interrupt, 0, "ewrk3", NULL)) {
629 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
630 status = -EAGAIN;
631 } else {
632
633
634
635
636 ewrk3_init(dev);
637
638 if (ewrk3_debug > 1){
639 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
640 printk(" physical address: ");
641 for (i=0;i<5;i++){
642 printk("%2.2x:",(u_char)dev->dev_addr[i]);
643 }
644 printk("%2.2x\n",(u_char)dev->dev_addr[i]);
645 if (lp->shmem_length == 0) {
646 printk(" no shared memory, I/O only mode\n");
647 } else {
648 printk(" start of shared memory: 0x%08lx\n",lp->shmem_base);
649 printk(" window length: 0x%04lx\n",lp->shmem_length);
650 }
651 printk(" # of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
652 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
653 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
654 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
655 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
656 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
657 }
658
659 dev->tbusy = 0;
660 dev->start = 1;
661 dev->interrupt = UNMASK_INTERRUPTS;
662
663
664
665
666 icr = inb(EWRK3_ICR);
667 ENABLE_IRQs;
668
669 }
670 } else {
671 dev->start = 0;
672 dev->tbusy = 1;
673 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
674 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
675 }
676
677 MOD_INC_USE_COUNT;
678
679 return status;
680 }
681
682
683
684
685 static void
686 ewrk3_init(struct device *dev)
687 {
688 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
689 u_char csr, page;
690 u_long iobase = dev->base_addr;
691
692
693
694
695 set_multicast_list(dev);
696
697
698
699
700 while (inb(EWRK3_TQ));
701 while (inb(EWRK3_TDQ));
702 while (inb(EWRK3_RQ));
703 while (inb(EWRK3_FMQ));
704
705
706
707
708 for (page=1;page<lp->mPage;page++) {
709 outb(page, EWRK3_FMQ);
710 }
711
712 lp->lock = 0;
713
714 START_EWRK3;
715 }
716
717
718
719
720 static int
721 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
722 {
723 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
724 u_long iobase = dev->base_addr;
725 int status = 0;
726 u_char icr, csr;
727
728
729 if (dev->tbusy || lp->lock) {
730 int tickssofar = jiffies - dev->trans_start;
731 if (tickssofar < QUEUE_PKT_TIMEOUT) {
732 status = -1;
733 } else if (!lp->hard_strapped) {
734 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
735 dev->name, inb(EWRK3_CSR));
736
737
738
739
740 DISABLE_IRQs;
741
742
743
744
745 STOP_EWRK3;
746
747 ewrk3_init(dev);
748
749
750
751
752 ENABLE_IRQs;
753
754 dev->tbusy=0;
755 dev->trans_start = jiffies;
756 }
757 } else if (skb == NULL) {
758 dev_tint(dev);
759 } else if (skb->len > 0) {
760
761
762
763
764
765 if (set_bit(0, (void*)&dev->tbusy) != 0)
766 printk("%s: Transmitter access conflict.\n", dev->name);
767
768 DISABLE_IRQs;
769
770
771
772
773 if (inb(EWRK3_FMQC) > 0) {
774 u_long buf = 0;
775 u_char page;
776
777 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
778
779
780
781 while (set_bit(0, (void *)&lp->lock) != 0);
782 if (lp->shmem_length == IO_ONLY) {
783 outb(page, EWRK3_IOPR);
784 } else if (lp->shmem_length == SHMEM_2K) {
785 buf = lp->shmem_base;
786 outb(page, EWRK3_MPR);
787 } else if (lp->shmem_length == SHMEM_32K) {
788 buf = ((((short)page << 11) & 0x7800) + lp->shmem_base);
789 outb((page >> 4), EWRK3_MPR);
790 } else if (lp->shmem_length == SHMEM_64K) {
791 buf = ((((short)page << 11) & 0xf800) + lp->shmem_base);
792 outb((page >> 5), EWRK3_MPR);
793 } else {
794 status = -1;
795 printk("%s: Oops - your private data area is hosed!\n",dev->name);
796 }
797
798 if (!status) {
799
800
801
802
803
804
805 if (lp->shmem_length == IO_ONLY) {
806 int i;
807 u_char *p = skb->data;
808
809 outb((char)(TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
810 outb((char)(skb->len & 0xff), EWRK3_DATA);
811 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
812 outb((char)0x04, EWRK3_DATA);
813 for (i=0; i<skb->len; i++) {
814 outb(*p++, EWRK3_DATA);
815 }
816 outb(page, EWRK3_TQ);
817 } else {
818 writeb((char)(TCR_QMODE|TCR_PAD|TCR_IFC), (char *)buf);
819 buf+=1;
820 writeb((char)(skb->len & 0xff), (char *)buf);
821 buf+=1;
822 if (lp->txc) {
823 writeb((char)(((skb->len >> 8) & 0xff) | XCT), (char *)buf);
824 buf+=1;
825 writeb(0x04, (char *)buf);
826 buf+=1;
827 writeb(0x00, (char *)(buf + skb->len));
828 memcpy_toio(buf, skb->data, PRELOAD);
829 outb(page, EWRK3_TQ);
830 memcpy_toio(buf+PRELOAD, skb->data+PRELOAD, skb->len-PRELOAD);
831 writeb(0xff, (char *)(buf + skb->len));
832 } else {
833 writeb((char)((skb->len >> 8) & 0xff), (char *)buf);
834 buf+=1;
835 writeb(0x04, (char *)buf);
836 buf+=1;
837 memcpy_toio((char *)buf, skb->data, skb->len);
838 outb(page, EWRK3_TQ);
839 }
840 }
841
842 dev->trans_start = jiffies;
843 dev_kfree_skb (skb, FREE_WRITE);
844
845 } else {
846 outb(page, EWRK3_FMQ);
847 }
848 lp->lock = 0;
849 } else {
850 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
851 (u_char) page);
852 }
853 } else {
854 printk("ewrk3_queue_pkt(): No free resources...\n");
855 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
856 }
857
858
859 if (inb(EWRK3_FMQC) > 0) {
860 dev->tbusy = 0;
861 }
862
863 ENABLE_IRQs;
864 }
865
866 return status;
867 }
868
869
870
871
872 static void
873 ewrk3_interrupt(int irq, void *dev_id, struct pt_regs * regs)
874 {
875 struct device *dev = (struct device *)(irq2dev_map[irq]);
876 struct ewrk3_private *lp;
877 u_long iobase;
878 u_char icr, cr, csr;
879
880 if (dev == NULL) {
881 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
882 } else {
883 lp = (struct ewrk3_private *)dev->priv;
884 iobase = dev->base_addr;
885
886 if (dev->interrupt)
887 printk("%s: Re-entering the interrupt handler.\n", dev->name);
888
889 dev->interrupt = MASK_INTERRUPTS;
890
891
892 csr = inb(EWRK3_CSR);
893
894
895
896
897 DISABLE_IRQs;
898
899 cr = inb(EWRK3_CR);
900 cr |= CR_LED;
901 outb(cr, EWRK3_CR);
902
903 if (csr & CSR_RNE)
904 ewrk3_rx(dev);
905
906 if (csr & CSR_TNE)
907 ewrk3_tx(dev);
908
909
910
911
912
913
914
915 if (inb(EWRK3_FMQC)) {
916 lp->irq_mask |= ICR_TXDM|ICR_RXDM;
917 csr &= ~(CSR_TXD|CSR_RXD);
918 outb(csr, EWRK3_CSR);
919 dev->tbusy = 0;
920 mark_bh(NET_BH);
921 } else {
922 lp->irq_mask &= ~(ICR_TXDM|ICR_RXDM);
923 }
924
925
926 cr &= ~CR_LED;
927 outb(cr, EWRK3_CR);
928
929 dev->interrupt = UNMASK_INTERRUPTS;
930 ENABLE_IRQs;
931 }
932
933 return;
934 }
935
936 static int
937 ewrk3_rx(struct device *dev)
938 {
939 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
940 u_long iobase = dev->base_addr;
941 int i, status = 0;
942 u_char page, tmpPage = 0, tmpLock = 0;
943 u_long buf = 0;
944
945 while (inb(EWRK3_RQC) && !status) {
946 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
947
948
949
950
951 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
952 if (lp->shmem_length == IO_ONLY) {
953 tmpPage = inb(EWRK3_IOPR);
954 } else {
955 tmpPage = inb(EWRK3_MPR);
956 }
957 }
958
959
960
961
962 if (lp->shmem_length == IO_ONLY) {
963 outb(page, EWRK3_IOPR);
964 } else if (lp->shmem_length == SHMEM_2K) {
965 buf = lp->shmem_base;
966 outb(page, EWRK3_MPR);
967 } else if (lp->shmem_length == SHMEM_32K) {
968 buf = ((((short)page << 11) & 0x7800) + lp->shmem_base);
969 outb((page >> 4), EWRK3_MPR);
970 } else if (lp->shmem_length == SHMEM_64K) {
971 buf = ((((short)page << 11) & 0xf800) + lp->shmem_base);
972 outb((page >> 5), EWRK3_MPR);
973 } else {
974 status = -1;
975 printk("%s: Oops - your private data area is hosed!\n",dev->name);
976 }
977
978 if (!status) {
979 char rx_status;
980 int pkt_len;
981
982 if (lp->shmem_length == IO_ONLY) {
983 rx_status = inb(EWRK3_DATA);
984 pkt_len = inb(EWRK3_DATA);
985 pkt_len |= ((u_short)inb(EWRK3_DATA) << 8);
986 } else {
987 rx_status = readb(buf);
988 buf+=1;
989 pkt_len = readw(buf);
990 buf+=3;
991 }
992
993 if (!(rx_status & R_ROK)) {
994 lp->stats.rx_errors++;
995 if (rx_status & R_DBE) lp->stats.rx_frame_errors++;
996 if (rx_status & R_CRC) lp->stats.rx_crc_errors++;
997 if (rx_status & R_PLL) lp->stats.rx_fifo_errors++;
998 } else {
999 struct sk_buff *skb;
1000
1001 if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1002 unsigned char *p;
1003 skb->dev = dev;
1004 skb_reserve(skb,2);
1005 p = skb_put(skb,pkt_len);
1006
1007 if (lp->shmem_length == IO_ONLY) {
1008 *p = inb(EWRK3_DATA);
1009 for (i=0; i<pkt_len; i++) {
1010 *p++ = inb(EWRK3_DATA);
1011 }
1012 } else {
1013 memcpy_fromio(p, buf, pkt_len);
1014 }
1015
1016
1017
1018
1019
1020 skb->protocol=eth_type_trans(skb,dev);
1021 netif_rx(skb);
1022
1023
1024
1025
1026 lp->stats.rx_packets++;
1027 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1028 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1029 lp->pktStats.bins[i]++;
1030 i = EWRK3_PKT_STAT_SZ;
1031 }
1032 }
1033 p = skb->data;
1034 if (p[0] & 0x01) {
1035 if ((*(s32 *)&p[0] == -1) && (*(s16 *)&p[4] == -1)) {
1036 lp->pktStats.broadcast++;
1037 } else {
1038 lp->pktStats.multicast++;
1039 }
1040 } else if ((*(s32 *)&p[0] == *(s32 *)&dev->dev_addr[0]) &&
1041 (*(s16 *)&p[4] == *(s16 *)&dev->dev_addr[4])) {
1042 lp->pktStats.unicast++;
1043 }
1044
1045 lp->pktStats.bins[0]++;
1046 if (lp->pktStats.bins[0] == 0) {
1047 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1048 }
1049 } else {
1050 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1051 lp->stats.rx_dropped++;
1052 break;
1053 }
1054 }
1055 }
1056
1057
1058
1059 outb(page, EWRK3_FMQ);
1060
1061 if (tmpLock) {
1062 if (lp->shmem_length == IO_ONLY) {
1063 outb(tmpPage, EWRK3_IOPR);
1064 } else {
1065 outb(tmpPage, EWRK3_MPR);
1066 }
1067 }
1068 lp->lock = 0;
1069 } else {
1070 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1071 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1072 }
1073 }
1074 return status;
1075 }
1076
1077
1078
1079
1080 static int
1081 ewrk3_tx(struct device *dev)
1082 {
1083 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1084 u_long iobase = dev->base_addr;
1085 u_char tx_status;
1086
1087 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1088 if (tx_status & T_VSTS) {
1089 if (tx_status & T_TXE) {
1090 lp->stats.tx_errors++;
1091 if (tx_status & T_NCL) lp->stats.tx_carrier_errors++;
1092 if (tx_status & T_LCL) lp->stats.tx_window_errors++;
1093 if (tx_status & T_CTU) {
1094 if ((tx_status & T_COLL) ^ T_XUR) {
1095 lp->pktStats.tx_underruns++;
1096 } else {
1097 lp->pktStats.excessive_underruns++;
1098 }
1099 } else if (tx_status & T_COLL) {
1100 if ((tx_status & T_COLL) ^ T_XCOLL) {
1101 lp->stats.collisions++;
1102 } else {
1103 lp->pktStats.excessive_collisions++;
1104 }
1105 }
1106 } else {
1107 lp->stats.tx_packets++;
1108 }
1109 }
1110 }
1111
1112 return 0;
1113 }
1114
1115 static int
1116 ewrk3_close(struct device *dev)
1117 {
1118 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1119 u_long iobase = dev->base_addr;
1120 u_char icr, csr;
1121
1122 dev->start = 0;
1123 dev->tbusy = 1;
1124
1125 if (ewrk3_debug > 1) {
1126 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1127 dev->name, inb(EWRK3_CSR));
1128 }
1129
1130
1131
1132
1133 DISABLE_IRQs;
1134
1135 STOP_EWRK3;
1136
1137
1138
1139
1140
1141
1142
1143 while (inb(EWRK3_TQ));
1144 while (inb(EWRK3_TDQ));
1145 while (inb(EWRK3_RQ));
1146
1147 if (!lp->hard_strapped) {
1148 free_irq(dev->irq, NULL);
1149
1150 irq2dev_map[dev->irq] = 0;
1151 }
1152
1153 MOD_DEC_USE_COUNT;
1154
1155 return 0;
1156 }
1157
1158 static struct enet_statistics *
1159 ewrk3_get_stats(struct device *dev)
1160 {
1161 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1162
1163
1164
1165 return &lp->stats;
1166 }
1167
1168
1169
1170
1171 static void
1172 set_multicast_list(struct device *dev)
1173 {
1174 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1175 u_long iobase = dev->base_addr;
1176 u_char csr;
1177
1178 if (irq2dev_map[dev->irq] != NULL) {
1179 csr = inb(EWRK3_CSR);
1180
1181 if (lp->shmem_length == IO_ONLY) {
1182 lp->mctbl = (char *) PAGE0_HTE;
1183 } else {
1184 lp->mctbl = (char *)(lp->shmem_base + PAGE0_HTE);
1185 }
1186
1187 csr &= ~(CSR_PME | CSR_MCE);
1188 if (dev->flags & IFF_PROMISC) {
1189 csr |= CSR_PME;
1190 outb(csr, EWRK3_CSR);
1191 } else {
1192 SetMulticastFilter(dev);
1193 csr |= CSR_MCE;
1194 outb(csr, EWRK3_CSR);
1195 }
1196 }
1197 }
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207 static void SetMulticastFilter(struct device *dev)
1208 {
1209 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1210 struct dev_mc_list *dmi=dev->mc_list;
1211 u_long iobase = dev->base_addr;
1212 int i;
1213 char *addrs, j, bit, byte;
1214 short *p = (short *) lp->mctbl;
1215 u16 hashcode;
1216 s32 crc, poly = CRC_POLYNOMIAL_LE;
1217
1218 while (set_bit(0, (void *)&lp->lock) != 0);
1219
1220 if (lp->shmem_length == IO_ONLY) {
1221 outb(0, EWRK3_IOPR);
1222 outw(EEPROM_OFFSET(lp->mctbl), EWRK3_PIR1);
1223 } else {
1224 outb(0, EWRK3_MPR);
1225 }
1226
1227 if (dev->flags & IFF_ALLMULTI) {
1228 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1229 if (lp->shmem_length == IO_ONLY) {
1230 outb(0xff, EWRK3_DATA);
1231 } else {
1232 writew(0xffff, p);
1233 p++; i++;
1234 }
1235 }
1236 } else {
1237
1238 if (lp->shmem_length == IO_ONLY) {
1239 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++) {
1240 outb(0x00, EWRK3_DATA);
1241 }
1242 outb(0x80, EWRK3_DATA); i++;
1243 for (; i<(HASH_TABLE_LEN >> 3); i++) {
1244 outb(0x00, EWRK3_DATA);
1245 }
1246 } else {
1247 memset_io(lp->mctbl, 0, (HASH_TABLE_LEN >> 3));
1248 writeb(0x80, (char *)(lp->mctbl + (HASH_TABLE_LEN >> 4) - 1));
1249 }
1250
1251
1252 for (i=0;i<dev->mc_count;i++) {
1253 addrs=dmi->dmi_addr;
1254 dmi=dmi->next;
1255 if ((*addrs & 0x01) == 1) {
1256 crc = 0xffffffff;
1257 for (byte=0;byte<ETH_ALEN;byte++) {
1258
1259 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1260 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1261 }
1262 }
1263 hashcode = crc & ((1 << 9) - 1);
1264
1265 byte = hashcode >> 3;
1266 bit = 1 << (hashcode & 0x07);
1267
1268 if (lp->shmem_length == IO_ONLY) {
1269 u_char tmp;
1270
1271 outw((short)((long)lp->mctbl) + byte, EWRK3_PIR1);
1272 tmp = inb(EWRK3_DATA);
1273 tmp |= bit;
1274 outw((short)((long)lp->mctbl) + byte, EWRK3_PIR1);
1275 outb(tmp, EWRK3_DATA);
1276 } else {
1277 writeb(readb(lp->mctbl + byte) | bit, lp->mctbl + byte);
1278 }
1279 }
1280 }
1281 }
1282
1283 lp->lock = 0;
1284
1285 return;
1286 }
1287
1288
1289
1290
1291 static void isa_probe(struct device *dev, u_long ioaddr)
1292 {
1293 int i = num_ewrk3s, maxSlots;
1294 u_long iobase;
1295
1296 if (!ioaddr && autoprobed) return ;
1297 if (ioaddr >= 0x400) return;
1298
1299 if (ioaddr == 0) {
1300 iobase = EWRK3_IO_BASE;
1301 maxSlots = 24;
1302 } else {
1303 iobase = ioaddr;
1304 maxSlots = i + 1;
1305 }
1306
1307 for (; (i<maxSlots) && (dev!=NULL);iobase+=EWRK3_IOP_INC, i++) {
1308 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1309 if (DevicePresent(iobase) == 0) {
1310 if ((dev = alloc_device(dev, iobase)) != NULL) {
1311 if (ewrk3_hw_init(dev, iobase) == 0) {
1312 num_ewrk3s++;
1313 }
1314 num_eth++;
1315 }
1316 }
1317 } else if (autoprobed) {
1318 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1319 }
1320 }
1321
1322 return;
1323 }
1324
1325
1326
1327
1328
1329 static void eisa_probe(struct device *dev, u_long ioaddr)
1330 {
1331 int i, maxSlots;
1332 u_long iobase;
1333 char name[EWRK3_STRLEN];
1334
1335 if (!ioaddr && autoprobed) return ;
1336 if (ioaddr < 0x1000) return;
1337
1338 if (ioaddr == 0) {
1339 iobase = EISA_SLOT_INC;
1340 i = 1;
1341 maxSlots = MAX_EISA_SLOTS;
1342 } else {
1343 iobase = ioaddr;
1344 i = (ioaddr >> 12);
1345 maxSlots = i + 1;
1346 }
1347
1348 for (i=1; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
1349 if (EISA_signature(name, EISA_ID) == 0) {
1350 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1351 if (DevicePresent(iobase) == 0) {
1352 if ((dev = alloc_device(dev, iobase)) != NULL) {
1353 if (ewrk3_hw_init(dev, iobase) == 0) {
1354 num_ewrk3s++;
1355 }
1356 num_eth++;
1357 }
1358 }
1359 } else if (autoprobed) {
1360 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1361 }
1362 }
1363 }
1364
1365 return;
1366 }
1367
1368
1369
1370
1371
1372 static struct device *alloc_device(struct device *dev, u_long iobase)
1373 {
1374 int addAutoProbe = 0;
1375 struct device *tmp = NULL, *ret;
1376 int (*init)(struct device *) = NULL;
1377
1378
1379
1380
1381 if (!loading_module) {
1382 while (dev->next != NULL) {
1383 if ((dev->base_addr == EWRK3_NDA) || (dev->base_addr == 0)) break;
1384 dev = dev->next;
1385 num_eth++;
1386 }
1387
1388
1389
1390
1391
1392 if ((dev->base_addr == 0) && (num_ewrk3s > 0)) {
1393 addAutoProbe++;
1394 tmp = dev->next;
1395 init = dev->init;
1396 }
1397
1398
1399
1400
1401
1402 if ((dev->next == NULL) &&
1403 !((dev->base_addr == EWRK3_NDA) || (dev->base_addr == 0))){
1404 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1405 GFP_KERNEL);
1406
1407 dev = dev->next;
1408 if (dev == NULL) {
1409 printk("eth%d: Device not initialised, insufficient memory\n",
1410 num_eth);
1411 } else {
1412
1413
1414
1415
1416
1417 dev->name = (char *)(dev + sizeof(struct device));
1418 if (num_eth > 9999) {
1419 sprintf(dev->name,"eth????");
1420 } else {
1421 sprintf(dev->name,"eth%d", num_eth);
1422 }
1423 dev->base_addr = iobase;
1424 dev->next = NULL;
1425 dev->init = &ewrk3_probe;
1426 num_ewrk3s++;
1427 }
1428 }
1429 ret = dev;
1430
1431
1432
1433
1434
1435 if (ret != NULL) {
1436 if (addAutoProbe) {
1437 for (;(tmp->next!=NULL) && (tmp->base_addr!=EWRK3_NDA); tmp=tmp->next);
1438
1439
1440
1441
1442
1443 if ((tmp->next == NULL) && !(tmp->base_addr == EWRK3_NDA)) {
1444 tmp->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1445 GFP_KERNEL);
1446 tmp = tmp->next;
1447 if (tmp == NULL) {
1448 printk("%s: Insufficient memory to extend the device list.\n",
1449 dev->name);
1450 } else {
1451
1452
1453
1454
1455
1456 tmp->name = (char *)(tmp + sizeof(struct device));
1457 if (num_eth > 9999) {
1458 sprintf(tmp->name,"eth????");
1459 } else {
1460 sprintf(tmp->name,"eth%d", num_eth);
1461 }
1462 tmp->base_addr = 0;
1463 tmp->next = NULL;
1464 tmp->init = init;
1465 }
1466 } else {
1467 tmp->base_addr = 0;
1468 }
1469 }
1470 }
1471 } else {
1472 ret = dev;
1473 }
1474
1475 return ret;
1476 }
1477
1478
1479
1480
1481 static int Read_EEPROM(u_long iobase, u_char eaddr)
1482 {
1483 int i;
1484
1485 outb((eaddr & 0x3f), EWRK3_PIR1);
1486 outb(EEPROM_RD, EWRK3_IOPR);
1487 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1488
1489 return inw(EWRK3_EPROM1);
1490 }
1491
1492
1493
1494
1495 static int Write_EEPROM(short data, u_long iobase, u_char eaddr)
1496 {
1497 int i;
1498
1499 outb(EEPROM_WR_EN, EWRK3_IOPR);
1500 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1501 outw(data, EWRK3_EPROM1);
1502 outb((eaddr & 0x3f), EWRK3_PIR1);
1503 outb(EEPROM_WR, EWRK3_IOPR);
1504 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1505 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1506 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1507
1508 return 0;
1509 }
1510
1511
1512
1513
1514 static void EthwrkSignature(char *name, char *eeprom_image)
1515 {
1516 u_long i,j,k;
1517 char *signatures[] = EWRK3_SIGNATURE;
1518
1519 strcpy(name, "");
1520 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1521 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1522 if (signatures[i][k] == eeprom_image[j]) {
1523 k++;
1524 } else {
1525 k=0;
1526 }
1527 }
1528 if (k == strlen(signatures[i])) {
1529 for (k=0; k<EWRK3_STRLEN; k++) {
1530 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1531 name[EWRK3_STRLEN] = '\0';
1532 }
1533 }
1534 }
1535
1536 return;
1537 }
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551 static int DevicePresent(u_long iobase)
1552 {
1553 union {
1554 struct {
1555 u32 a;
1556 u32 b;
1557 } llsig;
1558 char Sig[sizeof(u32) << 1];
1559 } dev;
1560 short sigLength;
1561 char data;
1562 int i, j, status = 0;
1563
1564 dev.llsig.a = ETH_PROM_SIG;
1565 dev.llsig.b = ETH_PROM_SIG;
1566 sigLength = sizeof(u32) << 1;
1567
1568 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1569 data = inb(EWRK3_APROM);
1570 if (dev.Sig[j] == data) {
1571 j++;
1572 } else {
1573 if (data == dev.Sig[0]) {
1574 j=1;
1575 } else {
1576 j=0;
1577 }
1578 }
1579 }
1580
1581 if (j!=sigLength) {
1582 status = -ENODEV;
1583 }
1584
1585 return status;
1586 }
1587
1588 static u_char get_hw_addr(struct device *dev, u_char *eeprom_image, char chipType)
1589 {
1590 int i, j, k;
1591 u_short chksum;
1592 u_char crc, lfsr, sd, status = 0;
1593 u_long iobase = dev->base_addr;
1594 u16 tmp;
1595
1596 if (chipType == LeMAC2) {
1597 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1598 sd = dev->dev_addr[j] = eeprom_image[EEPROM_PADDR0 + j];
1599 outb(dev->dev_addr[j], EWRK3_PAR0 + j);
1600 for (k=0; k<8; k++, sd >>= 1) {
1601 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1602 crc = (crc >> 1) + lfsr;
1603 }
1604 }
1605 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1606 } else {
1607 for (i=0,k=0;i<ETH_ALEN;) {
1608 k <<= 1 ;
1609 if (k > 0xffff) k-=0xffff;
1610
1611 k += (u_char) (tmp = inb(EWRK3_APROM));
1612 dev->dev_addr[i] = (u_char) tmp;
1613 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1614 i++;
1615 k += (u_short) ((tmp = inb(EWRK3_APROM)) << 8);
1616 dev->dev_addr[i] = (u_char) tmp;
1617 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1618 i++;
1619
1620 if (k > 0xffff) k-=0xffff;
1621 }
1622 if (k == 0xffff) k=0;
1623 chksum = inb(EWRK3_APROM);
1624 chksum |= (inb(EWRK3_APROM)<<8);
1625 if (k != chksum) status = -1;
1626 }
1627
1628 return status;
1629 }
1630
1631
1632
1633
1634 static int EISA_signature(char *name, s32 eisa_id)
1635 {
1636 u_long i;
1637 char *signatures[] = EWRK3_SIGNATURE;
1638 char ManCode[EWRK3_STRLEN];
1639 union {
1640 s32 ID;
1641 char Id[4];
1642 } Eisa;
1643 int status = 0;
1644
1645 *name = '\0';
1646 for (i=0; i<4; i++) {
1647 Eisa.Id[i] = inb(eisa_id + i);
1648 }
1649
1650 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
1651 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
1652 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
1653 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
1654 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
1655 ManCode[5]='\0';
1656
1657 for (i=0;(*signatures[i] != '\0') && (*name == '\0');i++) {
1658 if (strstr(ManCode, signatures[i]) != NULL) {
1659 strcpy(name,ManCode);
1660 status = 1;
1661 }
1662 }
1663
1664 return status;
1665 }
1666
1667
1668
1669
1670
1671 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1672 {
1673 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1674 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1675 u_long iobase = dev->base_addr;
1676 int i, j, status = 0;
1677 u_char csr;
1678 union {
1679 u_char addr[HASH_TABLE_LEN * ETH_ALEN];
1680 u_short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1681 } tmp;
1682
1683 switch(ioc->cmd) {
1684 case EWRK3_GET_HWADDR:
1685 for (i=0; i<ETH_ALEN; i++) {
1686 tmp.addr[i] = dev->dev_addr[i];
1687 }
1688 ioc->len = ETH_ALEN;
1689 if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
1690 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1691 }
1692
1693 break;
1694 case EWRK3_SET_HWADDR:
1695 if (suser()) {
1696 if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN))) {
1697 csr = inb(EWRK3_CSR);
1698 csr |= (CSR_TXD|CSR_RXD);
1699 outb(csr, EWRK3_CSR);
1700
1701 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1702 for (i=0; i<ETH_ALEN; i++) {
1703 dev->dev_addr[i] = tmp.addr[i];
1704 outb(tmp.addr[i], EWRK3_PAR0 + i);
1705 }
1706
1707 csr &= ~(CSR_TXD|CSR_RXD);
1708 outb(csr, EWRK3_CSR);
1709 }
1710 } else {
1711 status = -EPERM;
1712 }
1713
1714 break;
1715 case EWRK3_SET_PROM:
1716 if (suser()) {
1717 csr = inb(EWRK3_CSR);
1718 csr |= CSR_PME;
1719 csr &= ~CSR_MCE;
1720 outb(csr, EWRK3_CSR);
1721 } else {
1722 status = -EPERM;
1723 }
1724
1725 break;
1726 case EWRK3_CLR_PROM:
1727 if (suser()) {
1728 csr = inb(EWRK3_CSR);
1729 csr &= ~CSR_PME;
1730 outb(csr, EWRK3_CSR);
1731 } else {
1732 status = -EPERM;
1733 }
1734
1735 break;
1736 case EWRK3_SAY_BOO:
1737 printk("%s: Boo!\n", dev->name);
1738
1739 break;
1740 case EWRK3_GET_MCA:
1741 if (!(status = verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1742 while (set_bit(0, (void *)&lp->lock) != 0);
1743 if (lp->shmem_length == IO_ONLY) {
1744 outb(0, EWRK3_IOPR);
1745 outw(PAGE0_HTE, EWRK3_PIR1);
1746 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1747 tmp.addr[i] = inb(EWRK3_DATA);
1748 }
1749 } else {
1750 outb(0, EWRK3_MPR);
1751 memcpy_fromio(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1752 }
1753 ioc->len = (HASH_TABLE_LEN >> 3);
1754 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1755 }
1756 lp->lock = 0;
1757
1758 break;
1759 case EWRK3_SET_MCA:
1760 if (suser()) {
1761 if (!(status=verify_area(VERIFY_READ, ioc->data, ETH_ALEN*ioc->len))) {
1762 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1763 set_multicast_list(dev);
1764 }
1765 } else {
1766 status = -EPERM;
1767 }
1768
1769 break;
1770 case EWRK3_CLR_MCA:
1771 if (suser()) {
1772 set_multicast_list(dev);
1773 } else {
1774 status = -EPERM;
1775 }
1776
1777 break;
1778 case EWRK3_MCA_EN:
1779 if (suser()) {
1780 csr = inb(EWRK3_CSR);
1781 csr |= CSR_MCE;
1782 csr &= ~CSR_PME;
1783 outb(csr, EWRK3_CSR);
1784 } else {
1785 status = -EPERM;
1786 }
1787
1788 break;
1789 case EWRK3_GET_STATS:
1790 cli();
1791 ioc->len = sizeof(lp->pktStats);
1792 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1793 memcpy_tofs(ioc->data, &lp->pktStats, ioc->len);
1794 }
1795 sti();
1796
1797 break;
1798 case EWRK3_CLR_STATS:
1799 if (suser()) {
1800 cli();
1801 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1802 sti();
1803 } else {
1804 status = -EPERM;
1805 }
1806
1807 break;
1808 case EWRK3_GET_CSR:
1809 tmp.addr[0] = inb(EWRK3_CSR);
1810 ioc->len = 1;
1811 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1812 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1813 }
1814
1815 break;
1816 case EWRK3_SET_CSR:
1817 if (suser()) {
1818 if (!(status=verify_area(VERIFY_READ, ioc->data, 1))) {
1819 memcpy_fromfs(tmp.addr, ioc->data, 1);
1820 outb(tmp.addr[0], EWRK3_CSR);
1821 }
1822 } else {
1823 status = -EPERM;
1824 }
1825
1826 break;
1827 case EWRK3_GET_EEPROM:
1828 if (suser()) {
1829 for (i=0; i<(EEPROM_MAX>>1); i++) {
1830 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1831 }
1832 i = EEPROM_MAX;
1833 tmp.addr[i++] = inb(EWRK3_CMR);
1834 for (j=0;j<ETH_ALEN;j++) {
1835 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1836 }
1837 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1838 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1839 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1840 }
1841 } else {
1842 status = -EPERM;
1843 }
1844
1845 break;
1846 case EWRK3_SET_EEPROM:
1847 if (suser()) {
1848 if (!(status=verify_area(VERIFY_READ, ioc->data, EEPROM_MAX))) {
1849 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1850 for (i=0; i<(EEPROM_MAX>>1); i++) {
1851 Write_EEPROM(tmp.val[i], iobase, i);
1852 }
1853 }
1854 } else {
1855 status = -EPERM;
1856 }
1857
1858 break;
1859 case EWRK3_GET_CMR:
1860 tmp.addr[0] = inb(EWRK3_CMR);
1861 ioc->len = 1;
1862 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1863 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1864 }
1865
1866 break;
1867 case EWRK3_SET_TX_CUT_THRU:
1868 if (suser()) {
1869 lp->txc = 1;
1870 } else {
1871 status = -EPERM;
1872 }
1873
1874 break;
1875 case EWRK3_CLR_TX_CUT_THRU:
1876 if (suser()) {
1877 lp->txc = 0;
1878 } else {
1879 status = -EPERM;
1880 }
1881
1882 break;
1883 default:
1884 status = -EOPNOTSUPP;
1885 }
1886
1887 return status;
1888 }
1889
1890 #ifdef MODULE
1891 static char devicename[9] = { 0, };
1892 static struct device thisEthwrk = {
1893 devicename,
1894 0, 0, 0, 0,
1895 0x300, 5,
1896 0, 0, 0, NULL, ewrk3_probe };
1897
1898 static int io=0x300;
1899 static int irq=5;
1900
1901 int
1902 init_module(void)
1903 {
1904 thisEthwrk.base_addr=io;
1905 thisEthwrk.irq=irq;
1906 if (register_netdev(&thisEthwrk) != 0)
1907 return -EIO;
1908 return 0;
1909 }
1910
1911 void
1912 cleanup_module(void)
1913 {
1914 if (thisEthwrk.priv) {
1915 kfree(thisEthwrk.priv);
1916 thisEthwrk.priv = NULL;
1917 }
1918 thisEthwrk.irq = 0;
1919
1920 unregister_netdev(&thisEthwrk);
1921 release_region(thisEthwrk.base_addr, EWRK3_TOTAL_SIZE);
1922 }
1923 #endif
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933