This source file includes following definitions.
- pci_lookup_dev
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/ptrace.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/bios32.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16
17 #include <asm/page.h>
18
19 struct pci_bus pci_root;
20 struct pci_dev *pci_devices = 0;
21
22
23
24
25
26
27
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29
30
31
32 #define DEVICE(vid,did,name) \
33 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
34
35 #define BRIDGE(vid,did,name,bridge) \
36 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
37
38
39
40
41
42
43 struct pci_dev_info dev_info[] = {
44 DEVICE( COMPAQ, COMPAQ_1280, "QVision 1280/p"),
45 DEVICE( COMPAQ, COMPAQ_THUNDER, "ThunderLAN"),
46 DEVICE( NCR, NCR_53C810, "53c810"),
47 DEVICE( NCR, NCR_53C820, "53c820"),
48 DEVICE( NCR, NCR_53C825, "53c825"),
49 DEVICE( NCR, NCR_53C815, "53c815"),
50 DEVICE( ATI, ATI_68800, "68800AX"),
51 DEVICE( ATI, ATI_215CT222, "215CT222"),
52 DEVICE( ATI, ATI_210888CX, "210888CX"),
53 DEVICE( ATI, ATI_210888GX, "210888GX"),
54 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
55 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
56 DEVICE( VLSI, VLSI_82C594, "82C594-AFC2"),
57 DEVICE( VLSI, VLSI_82C597, "82C597-AFC2"),
58 DEVICE( ADL, ADL_2301, "2301"),
59 DEVICE( NS, NS_87410, "87410"),
60 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
61 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
62 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
63 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
64 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
65 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
66 BRIDGE( DEC, DEC_BRD, "DC21050", 0x00),
67 DEVICE( DEC, DEC_TULIP, "DC21040"),
68 DEVICE( DEC, DEC_TGA, "DC21030"),
69 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
70 DEVICE( DEC, DEC_FDDI, "DEFPA"),
71 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
72 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
73 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
74 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
75 DEVICE( CIRRUS, CIRRUS_5436, "GD 5436"),
76 DEVICE( CIRRUS, CIRRUS_6205, "GD 6205"),
77 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
78 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
79 DEVICE( CIRRUS, CIRRUS_7543, "CL 7543"),
80 DEVICE( IBM, IBM_82G2675, "82G2675"),
81 DEVICE( WD, WD_7197, "WD 7197"),
82 DEVICE( AMD, AMD_LANCE, "79C970"),
83 DEVICE( AMD, AMD_SCSI, "53C974"),
84 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
85 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
86 DEVICE( TRIDENT, TRIDENT_9660, "TG 9660"),
87 DEVICE( AI, AI_M1435, "M1435"),
88 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
89 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
90 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
91 DEVICE( CT, CT_65545, "65545"),
92 DEVICE( CT, CT_65548, "65548"),
93 DEVICE( FD, FD_36C70, "TMC-18C30"),
94 DEVICE( SI, SI_6201, "6201"),
95 DEVICE( SI, SI_6202, "6202"),
96 DEVICE( SI, SI_503, "85C503"),
97 DEVICE( SI, SI_501, "85C501"),
98 DEVICE( SI, SI_496, "85C496"),
99 DEVICE( SI, SI_601, "85C601"),
100 DEVICE( SI, SI_5511, "85C5511"),
101 DEVICE( SI, SI_5513, "85C5513"),
102 DEVICE( HP, HP_J2585A, "J2585A"),
103 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
104 DEVICE( PCTECH, PCTECH_RZ1001, "RZ1000"),
105 DEVICE( DPT, DPT, "SmartCache/Raid"),
106 DEVICE( OPTI, OPTI_92C178, "92C178"),
107 DEVICE( OPTI, OPTI_82C557, "82C557"),
108 DEVICE( OPTI, OPTI_82C558, "82C558"),
109 DEVICE( OPTI, OPTI_82C621, "82C621"),
110 DEVICE( OPTI, OPTI_82C822, "82C822"),
111 DEVICE( SGS, SGS_2000, "STG 2000X"),
112 DEVICE( SGS, SGS_1764, "STG 1764X"),
113 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"BT-946C"),
114 DEVICE( BUSLOGIC, BUSLOGIC_946C, "BT-946C"),
115 DEVICE( BUSLOGIC, BUSLOGIC_930, "BT-930"),
116 DEVICE( OAK, OAK_OTI107, "OTI107"),
117 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
118 DEVICE( N9, N9_I128, "Imagine 128"),
119 DEVICE( N9, N9_I128_2, "Imagine 128v2"),
120 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
121 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
122 DEVICE( UMC, UMC_UM8886BF, "UM8886BF"),
123 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
124 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
125 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
126 DEVICE( UMC, UMC_UM9017F, "UM9017F"),
127 DEVICE( UMC, UMC_UM8886N, "UM8886N"),
128 DEVICE( UMC, UMC_UM8891N, "UM8891N"),
129 DEVICE( X, X_AGX016, "ITT AGX016"),
130 DEVICE( NEXGEN, NEXGEN_82C501, "82C501"),
131 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
132 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
133 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
134 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
135 DEVICE( CMD, CMD_640, "640 (buggy)"),
136 DEVICE( CMD, CMD_646, "646"),
137 DEVICE( VISION, VISION_QD8500, "QD-8500"),
138 DEVICE( VISION, VISION_QD8580, "QD-8580"),
139 DEVICE( SIERRA, SIERRA_STB, "STB Horizon 64"),
140 DEVICE( ACC, ACC_2056, "2056"),
141 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
142 DEVICE( WINBOND, WINBOND_82C105, "SL82C105"),
143 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
144 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
145 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
146 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
147 DEVICE( AL, AL_M1445, "M1445"),
148 DEVICE( AL, AL_M1449, "M1449"),
149 DEVICE( AL, AL_M1451, "M1451"),
150 DEVICE( AL, AL_M1461, "M1461"),
151 DEVICE( AL, AL_M1489, "M1489"),
152 DEVICE( AL, AL_M1511, "M1511"),
153 DEVICE( AL, AL_M1513, "M1513"),
154 DEVICE( AL, AL_M4803, "M4803"),
155 DEVICE( ASP, ASP_ABP940, "ABP940"),
156 DEVICE( IMS, IMS_8849, "8849"),
157 DEVICE( TEKRAM2, TEKRAM2_690c, "DC690c"),
158 DEVICE( AMCC, AMCC_MYRINET, "Myrinet PCI (M2-PCI-32)"),
159 DEVICE( INTERG, INTERG_1680, "IGA-1680"),
160 DEVICE( REALTEK, REALTEK_8029, "8029"),
161 DEVICE( INIT, INIT_320P, "320 P"),
162 DEVICE( VIA, VIA_82C505, "VT 82C505"),
163 DEVICE( VIA, VIA_82C561, "VT 82C561"),
164 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
165 DEVICE( VIA, VIA_82C416, "VT 82C416MV"),
166 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
167 DEVICE( EF, EF_ATM_FPGA, "155P-MF1 (FPGA)"),
168 DEVICE( EF, EF_ATM_ASIC, "155P-MF1 (ASIC)"),
169 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
170 DEVICE( FORE, FORE_PCA200PC, "PCA-200PC"),
171 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge"),
172 DEVICE( ALLIANCE, ALLIANCE_PROMOTIO, "Promotion-6410"),
173 DEVICE( ALLIANCE, ALLIANCE_PROVIDEO, "Provideo"),
174 DEVICE( VMIC, VMIC_VME, "VMIVME-7587"),
175 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
176 DEVICE( ZEITNET, ZEITNET_1221, "1221"),
177 DEVICE( ZEITNET, ZEITNET_1225, "1225"),
178 DEVICE( SPECIALIX, SPECIALIX_XIO, "XIO/SIO host"),
179 DEVICE( SPECIALIX, SPECIALIX_RIO, "RIO host"),
180 DEVICE( RP, RP8OCTA, "RocketPort 8 Oct"),
181 DEVICE( RP, RP8INTF, "RocketPort 8 Intf"),
182 DEVICE( RP, RP16INTF, "RocketPort 16 Intf"),
183 DEVICE( RP, RP32INTF, "RocketPort 32 Intf"),
184 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
185 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
186 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
187 DEVICE( AVANCE, AVANCE_2302, "ALG-2302"),
188 DEVICE( S3, S3_811, "Trio32/Trio64"),
189 DEVICE( S3, S3_868, "Vision 868"),
190 DEVICE( S3, S3_928, "Vision 928-P"),
191 DEVICE( S3, S3_864_1, "Vision 864-P"),
192 DEVICE( S3, S3_864_2, "Vision 864-P"),
193 DEVICE( S3, S3_964_1, "Vision 964-P"),
194 DEVICE( S3, S3_964_2, "Vision 964-P"),
195 DEVICE( S3, S3_968, "Vision 968"),
196 DEVICE( INTEL, INTEL_82375, "82375EB"),
197 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
198 DEVICE( INTEL, INTEL_82378, "82378IB"),
199 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
200 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
201 DEVICE( INTEL, INTEL_7116, "SAA7116"),
202 DEVICE( INTEL, INTEL_82596, "82596"),
203 DEVICE( INTEL, INTEL_82865, "82865"),
204 DEVICE( INTEL, INTEL_82557, "82557"),
205 DEVICE( INTEL, INTEL_82437, "82437"),
206 DEVICE( INTEL, INTEL_82371_0, "82371 Triton PIIX"),
207 DEVICE( INTEL, INTEL_82371_1, "82371 Triton PIIX"),
208 DEVICE( INTEL, INTEL_P6, "Orion P6"),
209 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
210 DEVICE( ADAPTEC, ADAPTEC_7855, "AIC-7855"),
211 DEVICE( ADAPTEC, ADAPTEC_7870, "AIC-7870"),
212 DEVICE( ADAPTEC, ADAPTEC_7871, "AIC-7871"),
213 DEVICE( ADAPTEC, ADAPTEC_7872, "AIC-7872"),
214 DEVICE( ADAPTEC, ADAPTEC_7873, "AIC-7873"),
215 DEVICE( ADAPTEC, ADAPTEC_7874, "AIC-7874"),
216 DEVICE( ADAPTEC, ADAPTEC_7880, "AIC-7880U"),
217 DEVICE( ADAPTEC, ADAPTEC_7881, "AIC-7881U"),
218 DEVICE( ADAPTEC, ADAPTEC_7882, "AIC-7882U"),
219 DEVICE( ADAPTEC, ADAPTEC_7883, "AIC-7883U"),
220 DEVICE( ADAPTEC, ADAPTEC_7884, "AIC-7884U"),
221 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
222 DEVICE( HER, HER_STING, "Stingray"),
223 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV")
224 };
225
226
227 #ifdef CONFIG_PCI_OPTIMIZE
228
229
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243
244 struct optimization_type {
245 const char *type;
246 const char *off;
247 const char *on;
248 } bridge_optimization[] = {
249 {"Cache L2", "write through", "write back"},
250 {"CPU-PCI posted write", "off", "on"},
251 {"CPU-Memory posted write", "off", "on"},
252 {"PCI-Memory posted write", "off", "on"},
253 {"PCI burst", "off", "on"}
254 };
255
256 #define NUM_OPTIMIZATIONS \
257 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
258
259 struct bridge_mapping_type {
260 unsigned char addr;
261 unsigned char mask;
262 unsigned char value;
263 } bridge_mapping[] = {
264
265
266
267
268
269
270
271 {0x0 ,0x02 ,0x02 },
272 {0x53 ,0x02 ,0x02 },
273 {0x53 ,0x01 ,0x01 },
274 {0x54 ,0x01 ,0x01 },
275 {0x54 ,0x02 ,0x02 },
276
277
278
279
280
281 {0x50 ,0x10 ,0x00 },
282 {0x51 ,0x40 ,0x40 },
283 {0x0 ,0x0 ,0x0 },
284 {0x0 ,0x0 ,0x0 },
285 {0x0 ,0x0 ,0x0 },
286
287
288
289
290
291
292 {0x0 ,0x1 ,0x1 },
293 {0x0 ,0x2 ,0x0 },
294 {0x0 ,0x0 ,0x0 },
295 {0x0 ,0x0 ,0x0 },
296 {0x0 ,0x0 ,0x0 }
297 };
298
299 #endif
300
301
302
303
304
305 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
306 {
307 int min = 0,
308 max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
309
310 for ( ; ; )
311 {
312 int i = (min + max) >> 1;
313 long order;
314
315 order = dev_info[i].vendor - (long) vendor;
316 if (!order)
317 order = dev_info[i].device - (long) dev;
318
319 if (order < 0)
320 {
321 min = i + 1;
322 if ( min > max )
323 return 0;
324 continue;
325 }
326
327 if (order > 0)
328 {
329 max = i - 1;
330 if ( min > max )
331 return 0;
332 continue;
333 }
334
335 return & dev_info[ i ];
336 }
337 }
338
339 const char *pci_strclass (unsigned int class)
340 {
341 switch (class >> 8) {
342 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
343 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
344
345 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
346 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
347 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
348 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
349 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
350 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
351
352 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
353 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
354 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
355 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
356 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
357
358 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
359 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
360 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
361
362 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
363 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
364 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
365
366 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
367 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
368 case PCI_CLASS_MEMORY_OTHER: return "Memory";
369
370 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
371 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
372 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
373 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
374 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
375 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
376 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
377 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
378 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
379
380 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
381 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
382 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
383
384 case PCI_CLASS_SYSTEM_PIC: return "PIC";
385 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
386 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
387 case PCI_CLASS_SYSTEM_RTC: return "RTC";
388 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
389
390 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
391 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
392 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
393 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
394
395 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
396 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
397
398 case PCI_CLASS_PROCESSOR_386: return "386";
399 case PCI_CLASS_PROCESSOR_486: return "486";
400 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
401 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
402 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
403 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
404
405 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
406 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
407 case PCI_CLASS_SERIAL_SSA: return "SSA";
408 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
409
410 default: return "Unknown class";
411 }
412 }
413
414
415 const char *pci_strvendor(unsigned int vendor)
416 {
417 switch (vendor) {
418 case PCI_VENDOR_ID_COMPAQ: return "Compaq";
419 case PCI_VENDOR_ID_NCR: return "NCR";
420 case PCI_VENDOR_ID_ATI: return "ATI";
421 case PCI_VENDOR_ID_VLSI: return "VLSI";
422 case PCI_VENDOR_ID_ADL: return "Advance Logic";
423 case PCI_VENDOR_ID_NS: return "NS";
424 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
425 case PCI_VENDOR_ID_WEITEK: return "Weitek";
426 case PCI_VENDOR_ID_DEC: return "DEC";
427 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
428 case PCI_VENDOR_ID_IBM: return "IBM";
429 case PCI_VENDOR_ID_WD: return "Western Digital";
430 case PCI_VENDOR_ID_AMD: return "AMD";
431 case PCI_VENDOR_ID_TRIDENT: return "Trident";
432 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
433 case PCI_VENDOR_ID_MATROX: return "Matrox";
434 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
435 case PCI_VENDOR_ID_MIRO: return "Miro";
436 case PCI_VENDOR_ID_FD: return "Future Domain";
437 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
438 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
439 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
440 case PCI_VENDOR_ID_DPT: return "DPT";
441 case PCI_VENDOR_ID_OPTI: return "OPTI";
442 case PCI_VENDOR_ID_SGS: return "SGS Thomson";
443 case PCI_VENDOR_ID_BUSLOGIC: return "BusLogic";
444 case PCI_VENDOR_ID_OAK: return "OAK";
445 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
446 case PCI_VENDOR_ID_N9: return "Number Nine";
447 case PCI_VENDOR_ID_UMC: return "UMC";
448 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
449 case PCI_VENDOR_ID_NEXGEN: return "Nexgen";
450 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
451 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
452 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
453 case PCI_VENDOR_ID_FOREX: return "Forex";
454 case PCI_VENDOR_ID_OLICOM: return "Olicom";
455 case PCI_VENDOR_ID_CMD: return "CMD";
456 case PCI_VENDOR_ID_VISION: return "Vision";
457 case PCI_VENDOR_ID_SIERRA: return "Sierra";
458 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
459 case PCI_VENDOR_ID_WINBOND: return "Winbond";
460 case PCI_VENDOR_ID_3COM: return "3Com";
461 case PCI_VENDOR_ID_AL: return "Acer Labs";
462 case PCI_VENDOR_ID_ASP: return "Advanced System Products";
463 case PCI_VENDOR_ID_IMS: return "IMS";
464 case PCI_VENDOR_ID_TEKRAM2: return "Tekram";
465 case PCI_VENDOR_ID_AMCC: return "AMCC";
466 case PCI_VENDOR_ID_INTERG: return "Intergraphics";
467 case PCI_VENDOR_ID_REALTEK: return "Realtek";
468 case PCI_VENDOR_ID_INIT: return "Initio Corp";
469 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
470 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
471 case PCI_VENDOR_ID_EF: return "Efficient Networks";
472 case PCI_VENDOR_ID_FORE: return "Fore Systems";
473 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
474 case PCI_VENDOR_ID_PLX: return "PLX";
475 case PCI_VENDOR_ID_ALLIANCE: return "Alliance";
476 case PCI_VENDOR_ID_VMIC: return "VMIC";
477 case PCI_VENDOR_ID_MUTECH: return "Mutech";
478 case PCI_VENDOR_ID_TOSHIBA: return "Toshiba";
479 case PCI_VENDOR_ID_ZEITNET: return "ZeitNet";
480 case PCI_VENDOR_ID_SPECIALIX: return "Specialix";
481 case PCI_VENDOR_ID_RP: return "Comtrol";
482 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
483 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
484 case PCI_VENDOR_ID_TEKRAM: return "Tekram";
485 case PCI_VENDOR_ID_AVANCE: return "Avance";
486 case PCI_VENDOR_ID_S3: return "S3 Inc.";
487 case PCI_VENDOR_ID_INTEL: return "Intel";
488 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
489 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
490 case PCI_VENDOR_ID_HER: return "Hercules";
491 default: return "Unknown vendor";
492 }
493 }
494
495
496 const char *pci_strdev(unsigned int vendor, unsigned int device)
497 {
498 struct pci_dev_info *info;
499
500 info = pci_lookup_dev(vendor, device);
501 return info ? info->name : "Unknown device";
502 }
503
504
505
506
507
508
509 static void burst_bridge(unsigned char bus, unsigned char devfn,
510 unsigned char pos, int turn_on)
511 {
512 #ifdef CONFIG_PCI_OPTIMIZE
513 struct bridge_mapping_type *bmap;
514 unsigned char val;
515 int i;
516
517 pos *= NUM_OPTIMIZATIONS;
518 printk("PCI bridge optimization.\n");
519 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
520 printk(" %s: ", bridge_optimization[i].type);
521 bmap = &bridge_mapping[pos + i];
522 if (!bmap->addr) {
523 printk("Not supported.");
524 } else {
525 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
526 if ((val & bmap->mask) == bmap->value) {
527 printk("%s.", bridge_optimization[i].on);
528 if (!turn_on) {
529 pcibios_write_config_byte(bus, devfn,
530 bmap->addr,
531 (val | bmap->mask)
532 - bmap->value);
533 printk("Changed! Now %s.", bridge_optimization[i].off);
534 }
535 } else {
536 printk("%s.", bridge_optimization[i].off);
537 if (turn_on) {
538 pcibios_write_config_byte(bus, devfn,
539 bmap->addr,
540 (val & (0xff - bmap->mask))
541 + bmap->value);
542 printk("Changed! Now %s.", bridge_optimization[i].on);
543 }
544 }
545 }
546 printk("\n");
547 }
548 #endif
549 }
550
551
552
553
554
555
556
557
558 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
559 {
560 unsigned long base;
561 unsigned int l, class_rev, bus, devfn;
562 unsigned short vendor, device, status;
563 unsigned char bist, latency, min_gnt, max_lat;
564 int reg, len = 0;
565 const char *str;
566
567 bus = dev->bus->number;
568 devfn = dev->devfn;
569
570 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
571 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
572 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
573 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
574 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
575 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
576 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
577 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
578 if (len + 80 > size) {
579 return -1;
580 }
581 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
582 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
583
584 if (len + 80 > size) {
585 return -1;
586 }
587 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
588 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
589 pci_strdev(vendor, device), class_rev & 0xff);
590
591 if (!pci_lookup_dev(vendor, device)) {
592 len += sprintf(buf + len,
593 "Vendor id=%x. Device id=%x.\n ",
594 vendor, device);
595 }
596
597 str = 0;
598 switch (status & PCI_STATUS_DEVSEL_MASK) {
599 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
600 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
601 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
602 }
603 if (len + strlen(str) > size) {
604 return -1;
605 }
606 len += sprintf(buf + len, str);
607
608 if (status & PCI_STATUS_FAST_BACK) {
609 # define fast_b2b_capable "Fast back-to-back capable. "
610 if (len + strlen(fast_b2b_capable) > size) {
611 return -1;
612 }
613 len += sprintf(buf + len, fast_b2b_capable);
614 # undef fast_b2b_capable
615 }
616
617 if (bist & PCI_BIST_CAPABLE) {
618 # define BIST_capable "BIST capable. "
619 if (len + strlen(BIST_capable) > size) {
620 return -1;
621 }
622 len += sprintf(buf + len, BIST_capable);
623 # undef BIST_capable
624 }
625
626 if (dev->irq) {
627 if (len + 40 > size) {
628 return -1;
629 }
630 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
631 }
632
633 if (dev->master) {
634 if (len + 80 > size) {
635 return -1;
636 }
637 len += sprintf(buf + len, "Master Capable. ");
638 if (latency)
639 len += sprintf(buf + len, "Latency=%d. ", latency);
640 else
641 len += sprintf(buf + len, "No bursts. ");
642 if (min_gnt)
643 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
644 if (max_lat)
645 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
646 }
647
648 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
649 if (len + 40 > size) {
650 return -1;
651 }
652 pcibios_read_config_dword(bus, devfn, reg, &l);
653 base = l;
654 if (!base) {
655 continue;
656 }
657
658 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
659 len += sprintf(buf + len,
660 "\n I/O at 0x%lx.",
661 base & PCI_BASE_ADDRESS_IO_MASK);
662 } else {
663 const char *pref, *type = "unknown";
664
665 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
666 pref = "P";
667 } else {
668 pref = "Non-p";
669 }
670 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
671 case PCI_BASE_ADDRESS_MEM_TYPE_32:
672 type = "32 bit"; break;
673 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
674 type = "20 bit"; break;
675 case PCI_BASE_ADDRESS_MEM_TYPE_64:
676 type = "64 bit";
677
678 reg += 4;
679 pcibios_read_config_dword(bus, devfn, reg, &l);
680 base |= ((u64) l) << 32;
681 break;
682 }
683 len += sprintf(buf + len,
684 "\n %srefetchable %s memory at "
685 "0x%lx.", pref, type,
686 base & PCI_BASE_ADDRESS_MEM_MASK);
687 }
688 }
689
690 len += sprintf(buf + len, "\n");
691 return len;
692 }
693
694
695
696
697
698
699 int get_pci_list(char *buf)
700 {
701 int nprinted, len, size;
702 struct pci_dev *dev;
703 # define MSG "\nwarning: page-size limit reached!\n"
704
705
706 size = PAGE_SIZE - (strlen(MSG) + 1);
707 len = sprintf(buf, "PCI devices found:\n");
708
709 for (dev = pci_devices; dev; dev = dev->next) {
710 nprinted = sprint_dev_config(dev, buf + len, size - len);
711 if (nprinted < 0) {
712 return len + sprintf(buf + len, MSG);
713 }
714 len += nprinted;
715 }
716 return len;
717 }
718
719
720
721
722
723
724 static void *pci_malloc(long size, unsigned long *mem_startp)
725 {
726 void *mem;
727
728 #ifdef DEBUG
729 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
730 #endif
731 mem = (void*) *mem_startp;
732 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
733 memset(mem, 0, size);
734 return mem;
735 }
736
737
738 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
739 {
740 unsigned int devfn, l, max;
741 unsigned char cmd, tmp, hdr_type = 0;
742 struct pci_dev_info *info;
743 struct pci_dev *dev;
744 struct pci_bus *child;
745
746 #ifdef DEBUG
747 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
748 #endif
749
750 max = bus->secondary;
751 for (devfn = 0; devfn < 0xff; ++devfn) {
752 if (PCI_FUNC(devfn) == 0) {
753 pcibios_read_config_byte(bus->number, devfn,
754 PCI_HEADER_TYPE, &hdr_type);
755 } else if (!(hdr_type & 0x80)) {
756
757 continue;
758 }
759
760 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
761 &l);
762
763 if (l == 0xffffffff || l == 0x00000000) {
764 hdr_type = 0;
765 continue;
766 }
767
768 dev = pci_malloc(sizeof(*dev), mem_startp);
769 dev->bus = bus;
770
771
772
773
774
775 dev->next = pci_devices;
776 pci_devices = dev;
777
778 dev->devfn = devfn;
779 dev->vendor = l & 0xffff;
780 dev->device = (l >> 16) & 0xffff;
781
782
783
784
785
786
787 info = pci_lookup_dev(dev->vendor, dev->device);
788 if (!info) {
789 printk("Warning : Unknown PCI device (%x:%x). Please read include/linux/pci.h \n",
790 dev->vendor, dev->device);
791 } else {
792
793 if (info->bridge_type != 0xff) {
794 burst_bridge(bus->number, devfn,
795 info->bridge_type, 1);
796 }
797 }
798
799
800 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
801 &cmd);
802 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
803 cmd | PCI_COMMAND_MASTER);
804 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
805 &tmp);
806 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
807 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
808 cmd);
809
810
811 pcibios_read_config_byte(bus->number, devfn,
812 PCI_INTERRUPT_LINE, &dev->irq);
813
814
815 pcibios_read_config_dword(bus->number, devfn,
816 PCI_CLASS_REVISION, &l);
817 l = l >> 8;
818 dev->class = l;
819
820
821
822
823 dev->sibling = bus->devices;
824 bus->devices = dev;
825
826 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
827 unsigned int buses;
828 unsigned short cr;
829
830
831
832
833 child = pci_malloc(sizeof(*child), mem_startp);
834 child->next = bus->children;
835 bus->children = child;
836 child->self = dev;
837 child->parent = bus;
838
839
840
841
842
843 child->number = child->secondary = ++max;
844 child->primary = bus->secondary;
845 child->subordinate = 0xff;
846
847
848
849
850 pcibios_read_config_word(bus->number, devfn,
851 PCI_COMMAND, &cr);
852 pcibios_write_config_word(bus->number, devfn,
853 PCI_COMMAND, 0x0000);
854 pcibios_write_config_word(bus->number, devfn,
855 PCI_STATUS, 0xffff);
856
857
858
859 pcibios_read_config_dword(bus->number, devfn, 0x18,
860 &buses);
861 buses &= 0xff000000;
862 buses |= (((unsigned int)(child->primary) << 0) |
863 ((unsigned int)(child->secondary) << 8) |
864 ((unsigned int)(child->subordinate) << 16));
865 pcibios_write_config_dword(bus->number, devfn, 0x18,
866 buses);
867
868
869
870 max = scan_bus(child, mem_startp);
871
872
873
874
875 child->subordinate = max;
876 buses = (buses & 0xff00ffff)
877 | ((unsigned int)(child->subordinate) << 16);
878 pcibios_write_config_dword(bus->number, devfn, 0x18,
879 buses);
880 pcibios_write_config_word(bus->number, devfn,
881 PCI_COMMAND, cr);
882 }
883 }
884
885
886
887
888
889
890
891 return max;
892 }
893
894
895 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
896 {
897 mem_start = pcibios_init(mem_start, mem_end);
898
899 if (!pcibios_present()) {
900 printk("pci_init: no BIOS32 detected\n");
901 return mem_start;
902 }
903
904 printk("Probing PCI hardware.\n");
905
906 memset(&pci_root, 0, sizeof(pci_root));
907 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
908
909
910 mem_start = pcibios_fixup(mem_start, mem_end);
911
912 #ifdef DEBUG
913 {
914 int len = get_pci_list((char*)mem_start);
915 if (len) {
916 ((char *) mem_start)[len] = '\0';
917 printk("%s\n", (char *) mem_start);
918 }
919 }
920 #endif
921 return mem_start;
922 }
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