include/asm-sparc/mxcc.h

/* */
   1 /* $Id: mxcc.h,v 1.2 1995/11/25 02:32:11 davem Exp $
   2  * mxcc.h:  Definitions of the Viking MXCC registers
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _SPARC_MXCC_H
   8 #define _SPARC_MXCC_H
   9 
  10 /* These registers are accessed through ASI 0x2. */
  11 #define MXCC_DATSTREAM       0x1C00000  /* Data stream register */
  12 #define MXCC_SRCSTREAM       0x1C00100  /* Source stream register */
  13 #define MXCC_DESSTREAM       0x1C00200  /* Destination stream register */
  14 #define MXCC_RMCOUNT         0x1C00300  /* Count of references and misses */
  15 #define MXCC_STEST           0x1C00804  /* Internal self-test */
  16 #define MXCC_CREG            0x1C00A04  /* Control register */
  17 #define MXCC_SREG            0x1C00B00  /* Status register */
  18 #define MXCC_RREG            0x1C00C04  /* Reset register */
  19 #define MXCC_EREG            0x1C00E00  /* Error code register */
  20 #define MXCC_PREG            0x1C00F04  /* Address port register */
  21 
  22 /* The MXCC Control Register:
  23  *
  24  * ----------------------------------------------------------------------
  25  * |                                   | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
  26  * ----------------------------------------------------------------------
  27  *  31                              10    9    8-6   5   4    3   2  1-0
  28  *
  29  * RRC: Controls what you read from MXCC_RMCOUNT reg.
  30  *      0=Misses 1=References
  31  * PRE: Prefetch enable
  32  * MCE: Multiple Command Enable
  33  * PARE: Parity enable
  34  * ECE: External cache enable
  35  */
  36 
  37 #define MXCC_CTL_RRC   0x00000200
  38 #define MXCC_CTL_PRE   0x00000020
  39 #define MXCC_CTL_MCE   0x00000010
  40 #define MXCC_CTL_PARE  0x00000008
  41 #define MXCC_CTL_ECE   0x00000004
  42 
  43 /* The MXCC Error Register:
  44  *
  45  * --------------------------------------------------------
  46  * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
  47  * --------------------------------------------------------
  48  *  31   30 29  28  27  26  25 24-15  14-7   6  5-3   2-0
  49  *
  50  * ME: Multiple Errors have occurred
  51  * CE: Cache consistancy Error
  52  * PEW: Parity Error during a Write operation
  53  * PEE: Parity Error involving the External cache
  54  * ASE: ASynchronous Error
  55  * EIV: This register is toast
  56  * MOPC: MXCC Operation Code for instance causing error
  57  * ECODE: The Error CODE
  58  * PRIV: A privileged mode error? 0=no 1=yes
  59  * HPADDR: High PhysicalADDRess bits (35-32)
  60  */
  61 
  62 #define MXCC_ERR_ME     0x80000000
  63 #define MXCC_ERR_CE     0x20000000
  64 #define MXCC_ERR_PEW    0x10000000
  65 #define MXCC_ERR_PEE    0x08000000
  66 #define MXCC_ERR_ASE    0x04000000
  67 #define MXCC_ERR_EIV    0x02000000
  68 #define MXCC_ERR_MOPC   0x01FF8000
  69 #define MXCC_ERR_ECODE  0x00007F80
  70 #define MXCC_ERR_PRIV   0x00000040
  71 #define MXCC_ERR_HPADDR 0x0000000f
  72 
  73 /* The MXCC Port register:
  74  *
  75  * -----------------------------------------------------
  76  * |                | MID |                            |
  77  * -----------------------------------------------------
  78  *  31            21 20-18 17                         0
  79  *
  80  * MID: The moduleID of the cpu your read this from.
  81  */
  82 
  83 #endif /* !(_SPARC_MXCC_H) */
/* */
root/include/asm-sparc/mxcc.h

INCLUDED FROM
