drivers/sound/ad1848.c

/* */
This source file includes following definitions.
ad_read
ad_write
wait_for_calibration
ad_mute
ad_unmute
ad_enter_MCE
ad_leave_MCE
ad1848_set_recmask
change_bits
ad1848_mixer_get
ad1848_mixer_set
ad1848_mixer_reset
ad1848_mixer_ioctl
ad1848_open
ad1848_close
set_speed
set_channels
set_format
ad1848_ioctl
ad1848_output_block
ad1848_start_input
ad1848_prepare_for_IO
ad1848_reset
ad1848_halt
ad1848_halt_input
ad1848_halt_output
ad1848_trigger
ad1848_detect
ad1848_init
ad1848_unload
ad1848_interrupt
check_opl3
probe_ms_sound
attach_ms_sound
unload_ms_sound
probe_pnp_ad1848
attach_pnp_ad1848
unload_pnp_ad1848
ad1848_tmr_start
ad1848_tmr_reprogram
ad1848_tmr_disable
ad1848_tmr_restart
ad1848_tmr_install
   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  */
  16 
  17 /*
  18  * Copyright by Hannu Savolainen 1993-1996
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are
  22  * met: 1. Redistributions of source code must retain the above copyright
  23  * notice, this list of conditions and the following disclaimer. 2.
  24  * Redistributions in binary form must reproduce the above copyright notice,
  25  * this list of conditions and the following disclaimer in the documentation
  26  * and/or other materials provided with the distribution.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  29  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  30  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  32  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  */
  40 #include <linux/config.h>
  41 
  42 
  43 #define DEB(x)
  44 #define DEB1(x)
  45 #include "sound_config.h"
  46 
  47 #if defined(CONFIG_AD1848)
  48 
  49 #include "ad1848_mixer.h"
  50 
  51 typedef struct
  52   {
  53     int             base;
  54     int             irq;
  55     int             dual_dma;   /* 1, when two DMA channels allocated */
  56     unsigned char   MCE_bit;
  57     unsigned char   saved_regs[16];
  58     int             debug_flag;
  59 
  60     int             speed;
  61     unsigned char   speed_bits;
  62     int             channels;
  63     int             audio_format;
  64     unsigned char   format_bits;
  65 
  66     int             xfer_count;
  67     int             irq_mode;
  68     int             intr_active;
  69     int             opened;
  70     char           *chip_name;
  71     int             mode;
  72 #define MD_1848         1
  73 #define MD_4231         2
  74 #define MD_4231A        3
  75 #define MD_1845         4
  76 #define MD_4232         5
  77 
  78     /* Mixer parameters */
  79     int             recmask;
  80     int             supported_devices;
  81     int             supported_rec_devices;
  82     unsigned short  levels[32];
  83     int             dev_no;
  84     volatile unsigned long timer_ticks;
  85     int             timer_running;
  86     int             irq_ok;
  87     int            *osp;
  88   }
  89 
  90 ad1848_info;
  91 
  92 static int      nr_ad1848_devs = 0;
  93 static volatile char irq2dev[17] =
  94 {-1, -1, -1, -1, -1, -1, -1, -1,
  95  -1, -1, -1, -1, -1, -1, -1, -1, -1};
  96 
  97 static int      timer_installed = -1;
  98 
  99 static char     mixer2codec[MAX_MIXER_DEV] =
 100 {0};
 101 
 102 static int      ad_format_mask[6 /*devc->mode */ ] =
 103 {
 104   0,
 105   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 106   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 107   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM,
 108   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,     /* AD1845 */
 109   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM
 110 };
 111 
 112 static ad1848_info dev_info[MAX_AUDIO_DEV];
 113 
 114 #define io_Index_Addr(d)        ((d)->base)
 115 #define io_Indexed_Data(d)      ((d)->base+1)
 116 #define io_Status(d)            ((d)->base+2)
 117 #define io_Polled_IO(d)         ((d)->base+3)
 118 
 119 static int      ad1848_open (int dev, int mode);
 120 static void     ad1848_close (int dev);
 121 static int      ad1848_ioctl (int dev, unsigned int cmd, caddr_t arg, int local);
 122 static void     ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 123 static void     ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 124 static int      ad1848_prepare_for_IO (int dev, int bsize, int bcount);
 125 static void     ad1848_reset (int dev);
 126 static void     ad1848_halt (int dev);
 127 static void     ad1848_halt_input (int dev);
 128 static void     ad1848_halt_output (int dev);
 129 static void     ad1848_trigger (int dev, int bits);
 130 static int      ad1848_tmr_install (int dev);
 131 static void     ad1848_tmr_reprogram (int dev);
 132 
 133 static int
 134 ad_read (ad1848_info * devc, int reg)
     /*  */
 135 {
 136   unsigned long   flags;
 137   int             x;
 138   int             timeout = 900000;
 139 
 140   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 141     timeout--;
 142 
 143   save_flags (flags);
 144   cli ();
 145   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 146   x = inb (io_Indexed_Data (devc));
 147   /*  printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
 148   restore_flags (flags);
 149 
 150   return x;
 151 }
 152 
 153 static void
 154 ad_write (ad1848_info * devc, int reg, int data)
     /*  */
 155 {
 156   unsigned long   flags;
 157   int             timeout = 900000;
 158 
 159   while (timeout > 0 &&
 160          inb (devc->base) == 0x80)      /*Are we initializing */
 161     timeout--;
 162 
 163   save_flags (flags);
 164   cli ();
 165   outb ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 166   outb ((unsigned char) (data & 0xff), io_Indexed_Data (devc));
 167   /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
 168   restore_flags (flags);
 169 }
 170 
 171 static void
 172 wait_for_calibration (ad1848_info * devc)
     /*  */
 173 {
 174   int             timeout = 0;
 175 
 176   /*
 177      * Wait until the auto calibration process has finished.
 178      *
 179      * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 180      * 2)       Wait until the ACI bit of I11 gets on and then off.
 181    */
 182 
 183   timeout = 100000;
 184   while (timeout > 0 && inb (devc->base) == 0x80)
 185     timeout--;
 186   if (inb (devc->base) & 0x80)
 187     printk ("ad1848: Auto calibration timed out(1).\n");
 188 
 189   timeout = 100;
 190   while (timeout > 0 && !(ad_read (devc, 11) & 0x20))
 191     timeout--;
 192   if (!(ad_read (devc, 11) & 0x20))
 193     return;
 194 
 195   timeout = 80000;
 196   while (timeout > 0 && ad_read (devc, 11) & 0x20)
 197     timeout--;
 198   if (ad_read (devc, 11) & 0x20)
 199     printk ("ad1848: Auto calibration timed out(3).\n");
 200 }
 201 
 202 static void
 203 ad_mute (ad1848_info * devc)
     /*  */
 204 {
 205   int             i;
 206   unsigned char   prev;
 207 
 208   if (devc->mode != MD_1848)
 209     return;
 210   /*
 211      * Save old register settings and mute output channels
 212    */
 213   for (i = 6; i < 8; i++)
 214     {
 215       prev = devc->saved_regs[i] = ad_read (devc, i);
 216       ad_write (devc, i, prev | 0x80);
 217     }
 218 }
 219 
 220 static void
 221 ad_unmute (ad1848_info * devc)
     /*  */
 222 {
 223   int             i;
 224 
 225   /*
 226      * Restore back old volume registers (unmute)
 227    */
 228   for (i = 6; i < 8; i++)
 229     {
 230       ad_write (devc, i, devc->saved_regs[i] & ~0x80);
 231     }
 232 }
 233 
 234 static void
 235 ad_enter_MCE (ad1848_info * devc)
     /*  */
 236 {
 237   unsigned long   flags;
 238   int             timeout = 1000;
 239   unsigned short  prev;
 240 
 241   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 242     timeout--;
 243 
 244   save_flags (flags);
 245   cli ();
 246 
 247   devc->MCE_bit = 0x40;
 248   prev = inb (io_Index_Addr (devc));
 249   if (prev & 0x40)
 250     {
 251       restore_flags (flags);
 252       return;
 253     }
 254 
 255   outb (devc->MCE_bit, io_Index_Addr (devc));
 256   restore_flags (flags);
 257 }
 258 
 259 static void
 260 ad_leave_MCE (ad1848_info * devc)
     /*  */
 261 {
 262   unsigned long   flags;
 263   unsigned char   prev;
 264   int             timeout = 1000;
 265 
 266   while (timeout > 0 && inb (devc->base) == 0x80)       /*Are we initializing */
 267     timeout--;
 268 
 269   save_flags (flags);
 270   cli ();
 271 
 272   devc->MCE_bit = 0x00;
 273   prev = inb (io_Index_Addr (devc));
 274   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 275 
 276   if ((prev & 0x40) == 0)       /* Not in MCE mode */
 277     {
 278       restore_flags (flags);
 279       return;
 280     }
 281 
 282   outb (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 283   wait_for_calibration (devc);
 284   restore_flags (flags);
 285 }
 286 
 287 
 288 static int
 289 ad1848_set_recmask (ad1848_info * devc, int mask)
     /*  */
 290 {
 291   unsigned char   recdev;
 292   int             i, n;
 293 
 294   mask &= devc->supported_rec_devices;
 295 
 296   n = 0;
 297   for (i = 0; i < 32; i++)      /* Count selected device bits */
 298     if (mask & (1 << i))
 299       n++;
 300 
 301   if (n == 0)
 302     mask = SOUND_MASK_MIC;
 303   else if (n != 1)              /* Too many devices selected */
 304     {
 305       mask &= ~devc->recmask;   /* Filter out active settings */
 306 
 307       n = 0;
 308       for (i = 0; i < 32; i++)  /* Count selected device bits */
 309         if (mask & (1 << i))
 310           n++;
 311 
 312       if (n != 1)
 313         mask = SOUND_MASK_MIC;
 314     }
 315 
 316   switch (mask)
 317     {
 318     case SOUND_MASK_MIC:
 319       recdev = 2;
 320       break;
 321 
 322     case SOUND_MASK_LINE:
 323     case SOUND_MASK_LINE3:
 324       recdev = 0;
 325       break;
 326 
 327     case SOUND_MASK_CD:
 328     case SOUND_MASK_LINE1:
 329       recdev = 1;
 330       break;
 331 
 332     case SOUND_MASK_IMIX:
 333       recdev = 3;
 334       break;
 335 
 336     default:
 337       mask = SOUND_MASK_MIC;
 338       recdev = 2;
 339     }
 340 
 341   recdev <<= 6;
 342   ad_write (devc, 0, (ad_read (devc, 0) & 0x3f) | recdev);
 343   ad_write (devc, 1, (ad_read (devc, 1) & 0x3f) | recdev);
 344 
 345   devc->recmask = mask;
 346   return mask;
 347 }
 348 
 349 static void
 350 change_bits (unsigned char *regval, int dev, int chn, int newval)
     /*  */
 351 {
 352   unsigned char   mask;
 353   int             shift;
 354 
 355   if (mix_devices[dev][chn].polarity == 1)      /* Reverse */
 356     newval = 100 - newval;
 357 
 358   mask = (1 << mix_devices[dev][chn].nbits) - 1;
 359   shift = mix_devices[dev][chn].bitpos;
 360   newval = (int) ((newval * mask) + 50) / 100;  /* Scale it */
 361 
 362   *regval &= ~(mask << shift);  /* Clear bits */
 363   *regval |= (newval & mask) << shift;  /* Set new value */
 364 }
 365 
 366 static int
 367 ad1848_mixer_get (ad1848_info * devc, int dev)
     /*  */
 368 {
 369   if (!((1 << dev) & devc->supported_devices))
 370     return -EINVAL;
 371 
 372   return devc->levels[dev];
 373 }
 374 
 375 static int
 376 ad1848_mixer_set (ad1848_info * devc, int dev, int value)
     /*  */
 377 {
 378   int             left = value & 0x000000ff;
 379   int             right = (value & 0x0000ff00) >> 8;
 380   int             retvol;
 381 
 382   int             regoffs;
 383   unsigned char   val;
 384 
 385   if (left > 100)
 386     left = 100;
 387   if (right > 100)
 388     right = 100;
 389 
 390   if (mix_devices[dev][RIGHT_CHN].nbits == 0)   /* Mono control */
 391     right = left;
 392 
 393   retvol = left | (left << 8);
 394 
 395   /* Scale volumes */
 396   left = mix_cvt[left];
 397   right = mix_cvt[right];
 398 
 399   /* Scale it again */
 400   left = mix_cvt[left];
 401   right = mix_cvt[right];
 402 
 403   if (dev > 31)
 404     return -EINVAL;
 405 
 406   if (!(devc->supported_devices & (1 << dev)))
 407     return -EINVAL;
 408 
 409   if (mix_devices[dev][LEFT_CHN].nbits == 0)
 410     return -EINVAL;
 411 
 412   devc->levels[dev] = retvol;
 413 
 414   /*
 415      * Set the left channel
 416    */
 417 
 418   regoffs = mix_devices[dev][LEFT_CHN].regno;
 419   val = ad_read (devc, regoffs);
 420   change_bits (&val, dev, LEFT_CHN, left);
 421   ad_write (devc, regoffs, val);
 422   devc->saved_regs[regoffs] = val;
 423 
 424   /*
 425      * Set the right channel
 426    */
 427 
 428   if (mix_devices[dev][RIGHT_CHN].nbits == 0)
 429     return retvol;              /* Was just a mono channel */
 430 
 431   regoffs = mix_devices[dev][RIGHT_CHN].regno;
 432   val = ad_read (devc, regoffs);
 433   change_bits (&val, dev, RIGHT_CHN, right);
 434   ad_write (devc, regoffs, val);
 435   devc->saved_regs[regoffs] = val;
 436 
 437   return retvol;
 438 }
 439 
 440 static void
 441 ad1848_mixer_reset (ad1848_info * devc)
     /*  */
 442 {
 443   int             i;
 444 
 445   switch (devc->mode)
 446     {
 447     case MD_4231:
 448     case MD_4231A:
 449     case MD_1845:
 450       devc->supported_devices = MODE2_MIXER_DEVICES;
 451       break;
 452 
 453     case MD_4232:
 454       devc->supported_devices = MODE3_MIXER_DEVICES;
 455       break;
 456 
 457     default:
 458       devc->supported_devices = MODE1_MIXER_DEVICES;
 459     }
 460 
 461   devc->supported_rec_devices = MODE1_REC_DEVICES;
 462 
 463   for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 464     if (devc->supported_devices & (1 << i))
 465       ad1848_mixer_set (devc, i, default_mixer_levels[i]);
 466   ad1848_set_recmask (devc, SOUND_MASK_MIC);
 467 }
 468 
 469 static int
 470 ad1848_mixer_ioctl (int dev, unsigned int cmd, caddr_t arg)
     /*  */
 471 {
 472   ad1848_info    *devc;
 473 
 474   int             codec_dev = mixer2codec[dev];
 475 
 476   if (!codec_dev)
 477     return -ENXIO;
 478 
 479   codec_dev--;
 480 
 481   devc = (ad1848_info *) audio_devs[codec_dev]->devc;
 482 
 483   if (((cmd >> 8) & 0xff) == 'M')
 484     {
 485 
 486       if (_IOC_DIR (cmd) & _IOC_WRITE)
 487         switch (cmd & 0xff)
 488           {
 489           case SOUND_MIXER_RECSRC:
 490             return snd_ioctl_return ((int *) arg, ad1848_set_recmask (devc, get_fs_long ((long *) arg)));
 491             break;
 492 
 493           default:
 494             return snd_ioctl_return ((int *) arg, ad1848_mixer_set (devc, cmd & 0xff, get_fs_long ((long *) arg)));
 495           }
 496       else
 497         switch (cmd & 0xff)     /*
 498                                  * Return parameters
 499                                  */
 500           {
 501 
 502           case SOUND_MIXER_RECSRC:
 503             return snd_ioctl_return ((int *) arg, devc->recmask);
 504             break;
 505 
 506           case SOUND_MIXER_DEVMASK:
 507             return snd_ioctl_return ((int *) arg, devc->supported_devices);
 508             break;
 509 
 510           case SOUND_MIXER_STEREODEVS:
 511             return snd_ioctl_return ((int *) arg, devc->supported_devices & ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX));
 512             break;
 513 
 514           case SOUND_MIXER_RECMASK:
 515             return snd_ioctl_return ((int *) arg, devc->supported_rec_devices);
 516             break;
 517 
 518           case SOUND_MIXER_CAPS:
 519             return snd_ioctl_return ((int *) arg, SOUND_CAP_EXCL_INPUT);
 520             break;
 521 
 522           default:
 523             return snd_ioctl_return ((int *) arg, ad1848_mixer_get (devc, cmd & 0xff));
 524           }
 525     }
 526   else
 527     return -EINVAL;
 528 }
 529 
 530 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
 531 {
 532   {
 533     "Generic AD1848 codec",
 534     DMA_AUTOMODE,
 535     AFMT_U8,                    /* Will be set later */
 536     NULL,
 537     ad1848_open,
 538     ad1848_close,
 539     ad1848_output_block,
 540     ad1848_start_input,
 541     ad1848_ioctl,
 542     ad1848_prepare_for_IO,
 543     ad1848_prepare_for_IO,
 544     ad1848_reset,
 545     ad1848_halt,
 546     NULL,
 547     NULL,
 548     ad1848_halt_input,
 549     ad1848_halt_output,
 550     ad1848_trigger
 551   }};
 552 
 553 static struct mixer_operations ad1848_mixer_operations =
 554 {
 555   "AD1848/CS4248/CS4231",
 556   ad1848_mixer_ioctl
 557 };
 558 
 559 static int
 560 ad1848_open (int dev, int mode)
     /*  */
 561 {
 562   ad1848_info    *devc = NULL;
 563   unsigned long   flags;
 564 
 565   if (dev < 0 || dev >= num_audiodevs)
 566     return -ENXIO;
 567 
 568   devc = (ad1848_info *) audio_devs[dev]->devc;
 569 
 570 
 571   save_flags (flags);
 572   cli ();
 573   if (devc->opened)
 574     {
 575       restore_flags (flags);
 576       printk ("ad1848: Already opened\n");
 577       return -EBUSY;
 578     }
 579 
 580 
 581   devc->dual_dma = 0;
 582 
 583   if (audio_devs[dev]->flags & DMA_DUPLEX)
 584     {
 585       devc->dual_dma = 1;
 586     }
 587 
 588   devc->intr_active = 0;
 589   devc->opened = 1;
 590   devc->irq_mode = 0;
 591   ad1848_trigger (dev, 0);
 592   restore_flags (flags);
 593 /*
 594  * Mute output until the playback really starts. This decreases clicking (hope so).
 595  */
 596   ad_mute (devc);
 597 
 598   return 0;
 599 }
 600 
 601 static void
 602 ad1848_close (int dev)
     /*  */
 603 {
 604   unsigned long   flags;
 605   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 606 
 607   DEB (printk ("ad1848_close(void)\n"));
 608 
 609   save_flags (flags);
 610   cli ();
 611 
 612   devc->intr_active = 0;
 613   ad1848_reset (dev);
 614 
 615 
 616   devc->opened = 0;
 617   devc->irq_mode = 0;
 618 
 619   ad_unmute (devc);
 620   restore_flags (flags);
 621 }
 622 
 623 static int
 624 set_speed (ad1848_info * devc, int arg)
     /*  */
 625 {
 626   /*
 627      * The sampling speed is encoded in the least significant nible of I8. The
 628      * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
 629      * three bits select the divisor (indirectly):
 630      *
 631      * The available speeds are in the following table. Keep the speeds in
 632      * the increasing order.
 633    */
 634   typedef struct
 635   {
 636     int             speed;
 637     unsigned char   bits;
 638   }
 639   speed_struct;
 640 
 641   static speed_struct speed_table[] =
 642   {
 643     {5510, (0 << 1) | 1},
 644     {5510, (0 << 1) | 1},
 645     {6620, (7 << 1) | 1},
 646     {8000, (0 << 1) | 0},
 647     {9600, (7 << 1) | 0},
 648     {11025, (1 << 1) | 1},
 649     {16000, (1 << 1) | 0},
 650     {18900, (2 << 1) | 1},
 651     {22050, (3 << 1) | 1},
 652     {27420, (2 << 1) | 0},
 653     {32000, (3 << 1) | 0},
 654     {33075, (6 << 1) | 1},
 655     {37800, (4 << 1) | 1},
 656     {44100, (5 << 1) | 1},
 657     {48000, (6 << 1) | 0}
 658   };
 659 
 660   int             i, n, selected = -1;
 661 
 662   n = sizeof (speed_table) / sizeof (speed_struct);
 663 
 664   if (devc->mode == MD_1845)    /* AD1845 has different timer than others */
 665     {
 666       if (arg < 4000)
 667         arg = 4000;
 668       if (arg > 50000)
 669         arg = 50000;
 670 
 671       devc->speed = arg;
 672       devc->speed_bits = speed_table[3].bits;
 673       return devc->speed;
 674     }
 675 
 676   if (arg < speed_table[0].speed)
 677     selected = 0;
 678   if (arg > speed_table[n - 1].speed)
 679     selected = n - 1;
 680 
 681   for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 682     if (speed_table[i].speed == arg)
 683       selected = i;
 684     else if (speed_table[i].speed > arg)
 685       {
 686         int             diff1, diff2;
 687 
 688         diff1 = arg - speed_table[i - 1].speed;
 689         diff2 = speed_table[i].speed - arg;
 690 
 691         if (diff1 < diff2)
 692           selected = i - 1;
 693         else
 694           selected = i;
 695       }
 696 
 697   if (selected == -1)
 698     {
 699       printk ("ad1848: Can't find speed???\n");
 700       selected = 3;
 701     }
 702 
 703   devc->speed = speed_table[selected].speed;
 704   devc->speed_bits = speed_table[selected].bits;
 705   return devc->speed;
 706 }
 707 
 708 static int
 709 set_channels (ad1848_info * devc, int arg)
     /*  */
 710 {
 711   if (arg != 1 && arg != 2)
 712     return devc->channels;
 713 
 714   devc->channels = arg;
 715   return arg;
 716 }
 717 
 718 static int
 719 set_format (ad1848_info * devc, int arg)
     /*  */
 720 {
 721 
 722   static struct format_tbl
 723   {
 724     int             format;
 725     unsigned char   bits;
 726   }
 727   format2bits[] =
 728   {
 729     {
 730       0, 0
 731     }
 732     ,
 733     {
 734       AFMT_MU_LAW, 1
 735     }
 736     ,
 737     {
 738       AFMT_A_LAW, 3
 739     }
 740     ,
 741     {
 742       AFMT_IMA_ADPCM, 5
 743     }
 744     ,
 745     {
 746       AFMT_U8, 0
 747     }
 748     ,
 749     {
 750       AFMT_S16_LE, 2
 751     }
 752     ,
 753     {
 754       AFMT_S16_BE, 6
 755     }
 756     ,
 757     {
 758       AFMT_S8, 0
 759     }
 760     ,
 761     {
 762       AFMT_U16_LE, 0
 763     }
 764     ,
 765     {
 766       AFMT_U16_BE, 0
 767     }
 768   };
 769   int             i, n = sizeof (format2bits) / sizeof (struct format_tbl);
 770 
 771   if (!(arg & ad_format_mask[devc->mode]))
 772     arg = AFMT_U8;
 773 
 774   devc->audio_format = arg;
 775 
 776   for (i = 0; i < n; i++)
 777     if (format2bits[i].format == arg)
 778       {
 779         if ((devc->format_bits = format2bits[i].bits) == 0)
 780           return devc->audio_format = AFMT_U8;  /* Was not supported */
 781 
 782         return arg;
 783       }
 784 
 785   /* Still hanging here. Something must be terribly wrong */
 786   devc->format_bits = 0;
 787   return devc->audio_format = AFMT_U8;
 788 }
 789 
 790 static int
 791 ad1848_ioctl (int dev, unsigned int cmd, caddr_t arg, int local)
     /*  */
 792 {
 793   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 794 
 795   switch (cmd)
 796     {
 797     case SOUND_PCM_WRITE_RATE:
 798       if (local)
 799         return set_speed (devc, (int) arg);
 800       return snd_ioctl_return ((int *) arg, set_speed (devc, get_fs_long ((long *) arg)));
 801 
 802     case SOUND_PCM_READ_RATE:
 803       if (local)
 804         return devc->speed;
 805       return snd_ioctl_return ((int *) arg, devc->speed);
 806 
 807     case SNDCTL_DSP_STEREO:
 808       if (local)
 809         return set_channels (devc, (int) arg + 1) - 1;
 810       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg) + 1) - 1);
 811 
 812     case SOUND_PCM_WRITE_CHANNELS:
 813       if (local)
 814         return set_channels (devc, (int) arg);
 815       return snd_ioctl_return ((int *) arg, set_channels (devc, get_fs_long ((long *) arg)));
 816 
 817     case SOUND_PCM_READ_CHANNELS:
 818       if (local)
 819         return devc->channels;
 820       return snd_ioctl_return ((int *) arg, devc->channels);
 821 
 822     case SNDCTL_DSP_SAMPLESIZE:
 823       if (local)
 824         return set_format (devc, (int) arg);
 825       return snd_ioctl_return ((int *) arg, set_format (devc, get_fs_long ((long *) arg)));
 826 
 827     case SOUND_PCM_READ_BITS:
 828       if (local)
 829         return devc->audio_format;
 830       return snd_ioctl_return ((int *) arg, devc->audio_format);
 831 
 832     default:;
 833     }
 834   return -EINVAL;
 835 }
 836 
 837 static void
 838 ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 839 {
 840   unsigned long   flags, cnt;
 841   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 842 
 843   cnt = count;
 844 
 845   if (devc->audio_format == AFMT_IMA_ADPCM)
 846     {
 847       cnt /= 4;
 848     }
 849   else
 850     {
 851       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 852         cnt >>= 1;
 853     }
 854   if (devc->channels > 1)
 855     cnt >>= 1;
 856   cnt--;
 857 
 858   if (devc->irq_mode & PCM_ENABLE_OUTPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 859       intrflag &&
 860       cnt == devc->xfer_count)
 861     {
 862       devc->irq_mode |= PCM_ENABLE_OUTPUT;
 863       devc->intr_active = 1;
 864       return;                   /*
 865                                  * Auto DMA mode on. No need to react
 866                                  */
 867     }
 868   save_flags (flags);
 869   cli ();
 870 
 871   if (dma_restart)
 872     {
 873       ad_write (devc, 9, ad_read (devc, 9) & ~0x01);    /* Playback disable */
 874       /* ad1848_halt (dev); */
 875       DMAbuf_start_dma (dev, buf, count, DMA_MODE_WRITE);
 876     }
 877 
 878   ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 879   ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 880 
 881   ad_unmute (devc);
 882 
 883   devc->xfer_count = cnt;
 884   devc->irq_mode |= PCM_ENABLE_OUTPUT;
 885   devc->intr_active = 1;
 886   restore_flags (flags);
 887 }
 888 
 889 static void
 890 ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 891 {
 892   unsigned long   flags, cnt;
 893   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 894 
 895   cnt = count;
 896   if (devc->audio_format == AFMT_IMA_ADPCM)
 897     {
 898       cnt /= 4;
 899     }
 900   else
 901     {
 902       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 903         cnt >>= 1;
 904     }
 905   if (devc->channels > 1)
 906     cnt >>= 1;
 907   cnt--;
 908 
 909   if (devc->irq_mode & PCM_ENABLE_INPUT && audio_devs[dev]->flags & DMA_AUTOMODE &&
 910       intrflag &&
 911       cnt == devc->xfer_count)
 912     {
 913       devc->irq_mode |= PCM_ENABLE_INPUT;
 914       devc->intr_active = 1;
 915       return;                   /*
 916                                  * Auto DMA mode on. No need to react
 917                                  */
 918     }
 919   save_flags (flags);
 920   cli ();
 921 
 922   if (dma_restart)
 923     {
 924       /* ad1848_halt (dev); */
 925       ad_write (devc, 9, ad_read (devc, 9) & ~0x02);    /* Capture disable */
 926       DMAbuf_start_dma (dev, buf, count, DMA_MODE_READ);
 927     }
 928 
 929   if (devc->mode == MD_1848 || !devc->dual_dma)         /* Single DMA channel mode */
 930     {
 931       ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 932       ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 933     }
 934   else
 935     /* Dual DMA channel mode */
 936     {
 937       ad_write (devc, 31, (unsigned char) (cnt & 0xff));
 938       ad_write (devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
 939     }
 940 
 941   ad_unmute (devc);
 942 
 943   devc->xfer_count = cnt;
 944   devc->irq_mode |= PCM_ENABLE_INPUT;
 945   devc->intr_active = 1;
 946   restore_flags (flags);
 947 }
 948 
 949 static int
 950 ad1848_prepare_for_IO (int dev, int bsize, int bcount)
     /*  */
 951 {
 952   int             timeout;
 953   unsigned char   fs, old_fs, tmp = 0;
 954   unsigned long   flags;
 955   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 956 
 957   if (devc->irq_mode)
 958     return 0;
 959 
 960   save_flags (flags);
 961   cli ();
 962   fs = devc->speed_bits | (devc->format_bits << 5);
 963 
 964   if (devc->channels > 1)
 965     fs |= 0x10;
 966 
 967   if (devc->mode == MD_1845)    /* Use alternate speed select registers */
 968     {
 969       fs &= 0xf0;               /* Mask off the rate select bits */
 970 
 971       ad_write (devc, 22, (devc->speed >> 8) & 0xff);   /* Speed MSB */
 972       ad_write (devc, 23, devc->speed & 0xff);  /* Speed LSB */
 973     }
 974 
 975   old_fs = ad_read (devc, 8);
 976 
 977   if (devc->mode != MD_4232)
 978     if (fs == old_fs)           /* No change */
 979       {
 980         restore_flags (flags);
 981         devc->xfer_count = 0;
 982         return 0;
 983       }
 984 
 985   ad_enter_MCE (devc);          /* Enables changes to the format select reg */
 986 
 987   if (devc->mode == MD_4232)
 988     {
 989       tmp = ad_read (devc, 16);
 990       ad_write (devc, 16, tmp | 0x30);
 991     }
 992 
 993   ad_write (devc, 8, fs);
 994   /*
 995    * Write to I8 starts resyncronization. Wait until it completes.
 996    */
 997   timeout = 10000;
 998   while (timeout > 0 && inb (devc->base) == 0x80)
 999     timeout--;
1000 
1001   /*
1002      * If mode == 2 (CS4231), set I28 also. It's the capture format register.
1003    */
1004   if (devc->mode != MD_1848)
1005     {
1006       ad_write (devc, 28, fs);
1007 
1008       /*
1009          * Write to I28 starts resyncronization. Wait until it completes.
1010        */
1011       timeout = 10000;
1012       while (timeout > 0 && inb (devc->base) == 0x80)
1013         timeout--;
1014 
1015     }
1016 
1017   if (devc->mode == MD_4232)
1018     ad_write (devc, 16, tmp & ~0x30);
1019 
1020   ad_leave_MCE (devc);          /*
1021                                  * Starts the calibration process.
1022                                  */
1023   restore_flags (flags);
1024   devc->xfer_count = 0;
1025 
1026 #ifdef CONFIG_SEQUENCER
1027   if (dev == timer_installed && devc->timer_running)
1028     if ((fs & 0x01) != (old_fs & 0x01))
1029       {
1030         ad1848_tmr_reprogram (dev);
1031       }
1032 #endif
1033   return 0;
1034 }
1035 
1036 static void
1037 ad1848_reset (int dev)
     /*  */
1038 {
1039   ad1848_halt (dev);
1040 }
1041 
1042 static void
1043 ad1848_halt (int dev)
     /*  */
1044 {
1045   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1046 
1047   unsigned char   bits = ad_read (devc, 9);
1048 
1049   if (bits & 0x01)
1050     ad1848_halt_output (dev);
1051 
1052   if (bits & 0x02)
1053     ad1848_halt_input (dev);
1054 }
1055 
1056 static void
1057 ad1848_halt_input (int dev)
     /*  */
1058 {
1059   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1060   unsigned long   flags;
1061 
1062   save_flags (flags);
1063   cli ();
1064 
1065   ad_mute (devc);
1066 
1067   if (devc->mode == MD_4232)    /* Use applied black magic */
1068     {
1069       int             tmout;
1070 
1071       disable_dma (audio_devs[dev]->dmachan1);
1072 
1073       for (tmout = 0; tmout < 100000; tmout++)
1074         if (ad_read (devc, 11) & 0x10)
1075           break;
1076       ad_write (devc, 9, ad_read (devc, 9) & ~0x01);    /* Stop playback */
1077 
1078       enable_dma (audio_devs[dev]->dmachan1);
1079       restore_flags (flags);
1080       return;
1081     }
1082   ad_write (devc, 9, ad_read (devc, 9) & ~0x02);        /* Stop capture */
1083 
1084 
1085   outb (0, io_Status (devc));   /* Clear interrupt status */
1086   outb (0, io_Status (devc));   /* Clear interrupt status */
1087 
1088   devc->irq_mode &= ~PCM_ENABLE_INPUT;
1089 
1090   restore_flags (flags);
1091 }
1092 
1093 static void
1094 ad1848_halt_output (int dev)
     /*  */
1095 {
1096   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1097   unsigned long   flags;
1098 
1099   save_flags (flags);
1100   cli ();
1101 
1102   ad_mute (devc);
1103   if (devc->mode == MD_4232)    /* Use applied black magic */
1104     {
1105       int             tmout;
1106 
1107       disable_dma (audio_devs[dev]->dmachan1);
1108 
1109       for (tmout = 0; tmout < 100000; tmout++)
1110         if (ad_read (devc, 11) & 0x10)
1111           break;
1112       ad_write (devc, 9, ad_read (devc, 9) & ~0x01);    /* Stop playback */
1113 
1114       enable_dma (audio_devs[dev]->dmachan1);
1115       restore_flags (flags);
1116       return;
1117     }
1118   ad_write (devc, 9, ad_read (devc, 9) & ~0x01);        /* Stop playback */
1119 
1120 
1121   outb (0, io_Status (devc));   /* Clear interrupt status */
1122   outb (0, io_Status (devc));   /* Clear interrupt status */
1123 
1124   devc->irq_mode &= ~PCM_ENABLE_OUTPUT;
1125 
1126   restore_flags (flags);
1127 }
1128 
1129 static void
1130 ad1848_trigger (int dev, int state)
     /*  */
1131 {
1132   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1133   unsigned long   flags;
1134   unsigned char   tmp;
1135 
1136   save_flags (flags);
1137   cli ();
1138   state &= devc->irq_mode;
1139 
1140   tmp = ad_read (devc, 9) & ~0x03;
1141   if (state & PCM_ENABLE_INPUT)
1142     tmp |= 0x02;
1143   if (state & PCM_ENABLE_OUTPUT)
1144     tmp |= 0x01;
1145   ad_write (devc, 9, tmp);
1146 
1147   restore_flags (flags);
1148 }
1149 
1150 int
1151 ad1848_detect (int io_base, int *ad_flags, int *osp)
     /*  */
1152 {
1153 
1154   unsigned char   tmp;
1155   int             i;
1156   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1157   unsigned char   tmp1 = 0xff, tmp2 = 0xff;
1158 
1159   DDB (printk ("ad1848_detect(%x)\n", io_base));
1160 
1161   if (ad_flags)
1162     *ad_flags = 0;
1163 
1164   if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1165     {
1166       DDB (printk ("ad1848 detect error - step 0\n"));
1167       return 0;
1168     }
1169   if (check_region (io_base, 4))
1170     {
1171       printk ("\n\nad1848.c: Port %x not free.\n\n", io_base);
1172       return 0;
1173     }
1174 
1175   devc->base = io_base;
1176   devc->irq_ok = 0;
1177   devc->timer_running = 0;
1178   devc->MCE_bit = 0x40;
1179   devc->irq = 0;
1180   devc->opened = 0;
1181   devc->chip_name = "AD1848";
1182   devc->mode = MD_1848;         /* AD1848 or CS4248 */
1183   devc->osp = osp;
1184   devc->debug_flag = 0;
1185 
1186   /*
1187      * Check that the I/O address is in use.
1188      *
1189      * The bit 0x80 of the base I/O port is known to be 0 after the
1190      * chip has performed it's power on initialization. Just assume
1191      * this has happened before the OS is starting.
1192      *
1193      * If the I/O address is unused, it typically returns 0xff.
1194    */
1195 
1196   DDB (printk ("ad1848_detect() - step A\n"));
1197   if ((inb (devc->base) & 0x80) != 0x00)        /* Not a AD1848 */
1198     {
1199       DDB (printk ("ad1848 detect error - step A (%02x)\n",
1200                    inb (devc->base)));
1201       return 0;
1202     }
1203 
1204   /*
1205      * Test if it's possible to change contents of the indirect registers.
1206      * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1207      * so try to avoid using it.
1208    */
1209 
1210   DDB (printk ("ad1848_detect() - step B\n"));
1211   ad_write (devc, 0, 0xaa);
1212   ad_write (devc, 1, 0x45);     /* 0x55 with bit 0x10 clear */
1213 
1214   if ((tmp1 = ad_read (devc, 0)) != 0xaa || (tmp2 = ad_read (devc, 1)) != 0x45)
1215     {
1216       DDB (printk ("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1217       return 0;
1218     }
1219 
1220   DDB (printk ("ad1848_detect() - step C\n"));
1221   ad_write (devc, 0, 0x45);
1222   ad_write (devc, 1, 0xaa);
1223 
1224   if ((tmp1 = ad_read (devc, 0)) != 0x45 || (tmp2 = ad_read (devc, 1)) != 0xaa)
1225     {
1226       DDB (printk ("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1227       return 0;
1228     }
1229 
1230   /*
1231      * The indirect register I12 has some read only bits. Lets
1232      * try to change them.
1233    */
1234 
1235   DDB (printk ("ad1848_detect() - step D\n"));
1236   tmp = ad_read (devc, 12);
1237   ad_write (devc, 12, (~tmp) & 0x0f);
1238 
1239   if ((tmp & 0x0f) != ((tmp1 = ad_read (devc, 12)) & 0x0f))
1240     {
1241       DDB (printk ("ad1848 detect error - step D (%x)\n", tmp1));
1242       return 0;
1243     }
1244 
1245   /*
1246      * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1247      *   0x01=RevB and 0x0A=RevC.
1248    */
1249 
1250   /*
1251      * The original AD1848/CS4248 has just 15 indirect registers. This means
1252      * that I0 and I16 should return the same value (etc.).
1253      * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1254      * with CS4231.
1255    */
1256 
1257   DDB (printk ("ad1848_detect() - step F\n"));
1258   ad_write (devc, 12, 0);       /* Mode2=disabled */
1259 
1260   for (i = 0; i < 16; i++)
1261     if ((tmp1 = ad_read (devc, i)) != (tmp2 = ad_read (devc, i + 16)))
1262       {
1263         DDB (printk ("ad1848 detect error - step F(%d/%x/%x)\n", i, tmp1, tmp2));
1264         return 0;
1265       }
1266 
1267   /*
1268      * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1269      * The bit 0x80 is always 1 in CS4248 and CS4231.
1270    */
1271 
1272   DDB (printk ("ad1848_detect() - step G\n"));
1273   ad_write (devc, 12, 0x40);    /* Set mode2, clear 0x80 */
1274 
1275   tmp1 = ad_read (devc, 12);
1276   if (tmp1 & 0x80)
1277     {
1278       if (ad_flags)
1279         *ad_flags |= AD_F_CS4248;
1280 
1281       devc->chip_name = "CS4248";       /* Our best knowledge just now */
1282     }
1283 
1284   if ((tmp1 & 0xc0) == (0x80 | 0x40))
1285     {
1286       /*
1287          *      CS4231 detected - is it?
1288          *
1289          *      Verify that setting I0 doesn't change I16.
1290        */
1291       DDB (printk ("ad1848_detect() - step H\n"));
1292       ad_write (devc, 16, 0);   /* Set I16 to known value */
1293 
1294       ad_write (devc, 0, 0x45);
1295       if ((tmp1 = ad_read (devc, 16)) != 0x45)  /* No change -> CS4231? */
1296         {
1297 
1298           ad_write (devc, 0, 0xaa);
1299           if ((tmp1 = ad_read (devc, 16)) == 0xaa)      /* Rotten bits? */
1300             {
1301               DDB (printk ("ad1848 detect error - step H(%x)\n", tmp1));
1302               return 0;
1303             }
1304 
1305           /*
1306              * Verify that some bits of I25 are read only.
1307            */
1308 
1309           DDB (printk ("ad1848_detect() - step I\n"));
1310           tmp1 = ad_read (devc, 25);    /* Original bits */
1311           ad_write (devc, 25, ~tmp1);   /* Invert all bits */
1312           if ((ad_read (devc, 25) & 0xe7) == (tmp1 & 0xe7))
1313             {
1314               int             id;
1315 
1316               /*
1317                *      It's at least CS4231
1318                */
1319               devc->chip_name = "CS4231";
1320 
1321               devc->mode = MD_4231;
1322 
1323               /*
1324                * It could be an AD1845 or CS4231A as well.
1325                * CS4231 and AD1845 report the same revision info in I25
1326                * while the CS4231A reports different.
1327                */
1328 
1329               DDB (printk ("ad1848_detect() - step I\n"));
1330               id = ad_read (devc, 25) & 0xe7;
1331 
1332               switch (id)
1333                 {
1334 
1335                 case 0xa0:
1336                   devc->chip_name = "CS4231A";
1337                   devc->mode = MD_4231A;
1338                   break;
1339 
1340                 case 0xa2:
1341                   devc->chip_name = "CS4232";
1342                   devc->mode = MD_4232;
1343                   break;
1344 
1345                 case 0xb2:
1346                   devc->chip_name = "CS4232A";
1347                   devc->mode = MD_4232;
1348                   break;
1349 
1350                 case 0x80:
1351                   {
1352                     /* 
1353                      * It must be a CS4231 or AD1845. The register I23 of
1354                      * CS4231 is undefined and it appears to be read only.
1355                      * AD1845 uses I23 for setting sample rate. Assume
1356                      * the chip is AD1845 if I23 is changeable.
1357                      */
1358 
1359                     unsigned char   tmp = ad_read (devc, 23);
1360 
1361                     ad_write (devc, 23, ~tmp);
1362                     if (ad_read (devc, 23) != tmp)      /* AD1845 ? */
1363                       {
1364                         devc->chip_name = "AD1845";
1365                         devc->mode = MD_1845;
1366                       }
1367 
1368                     ad_write (devc, 23, tmp);   /* Restore */
1369                   }
1370                   break;
1371 
1372                 default:        /* Assume CS4231 */
1373                   devc->mode = MD_4231;
1374 
1375                 }
1376             }
1377           ad_write (devc, 25, tmp1);    /* Restore bits */
1378 
1379           DDB (printk ("ad1848_detect() - step K\n"));
1380         }
1381     }
1382 
1383   DDB (printk ("ad1848_detect() - step L\n"));
1384   if (ad_flags)
1385     {
1386       if (devc->mode != MD_1848)
1387         *ad_flags |= AD_F_CS4231;
1388     }
1389 
1390   DDB (printk ("ad1848_detect() - Detected OK\n"));
1391   return 1;
1392 }
1393 
1394 void
1395 ad1848_init (char *name, int io_base, int irq, int dma_playback, int dma_capture, int share_dma, int *osp)
     /*  */
1396 {
1397   /*
1398      * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1399      *   so that this driver doesn't need to allocate/deallocate it.
1400      *   The actually used IRQ is ABS(irq).
1401    */
1402 
1403   /*
1404      * Initial values for the indirect registers of CS4248/AD1848.
1405    */
1406   static int      init_values[] =
1407   {
1408     0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1409     0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1410 
1411   /* Positions 16 to 31 just for CS4231 */
1412     0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1413     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1414   };
1415   int             i, my_dev;
1416 
1417   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1418 
1419   if (!ad1848_detect (io_base, NULL, osp))
1420     return;
1421 
1422   request_region (devc->base, 4, devc->chip_name);
1423 
1424   devc->irq = (irq > 0) ? irq : 0;
1425   devc->opened = 0;
1426   devc->timer_ticks = 0;
1427   devc->osp = osp;
1428 
1429   if (nr_ad1848_devs != 0)
1430     {
1431       memcpy ((char *) &ad1848_pcm_operations[nr_ad1848_devs],
1432               (char *) &ad1848_pcm_operations[0],
1433               sizeof (struct audio_operations));
1434     }
1435 
1436   for (i = 0; i < 16; i++)
1437     ad_write (devc, i, init_values[i]);
1438 
1439   ad_mute (devc);               /* Initialize some variables */
1440   ad_unmute (devc);             /* Leave it unmuted now */
1441 
1442   if (devc->mode > MD_1848)
1443     {
1444       if (dma_capture == dma_playback || dma_capture == -1 || dma_playback == -1)
1445         {
1446           ad_write (devc, 9, ad_read (devc, 9) | 0x04);         /* Single DMA mode */
1447           ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1448         }
1449       else
1450         {
1451           ad_write (devc, 9, ad_read (devc, 9) & ~0x04);        /* Dual DMA mode */
1452           ad1848_pcm_operations[nr_ad1848_devs].flags |= DMA_DUPLEX;
1453         }
1454 
1455       ad_write (devc, 12, ad_read (devc, 12) | 0x40);   /* Mode2 = enabled */
1456       for (i = 16; i < 32; i++)
1457         ad_write (devc, i, init_values[i]);
1458 
1459 
1460       if (devc->mode == MD_1845)
1461         ad_write (devc, 27, ad_read (devc, 27) | 0x08);         /* Alternate freq select enabled */
1462     }
1463   else
1464     {
1465       ad1848_pcm_operations[nr_ad1848_devs].flags &= ~DMA_DUPLEX;
1466       ad_write (devc, 9, ad_read (devc, 9) | 0x04);     /* Single DMA mode */
1467     }
1468 
1469   outb (0, io_Status (devc));   /* Clear pending interrupts */
1470 
1471   if (name != NULL && name[0] != 0)
1472     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1473              "%s (%s)", name, devc->chip_name);
1474   else
1475     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1476              "Generic audio codec (%s)", devc->chip_name);
1477 
1478   conf_printf2 (ad1848_pcm_operations[nr_ad1848_devs].name,
1479                 devc->base, devc->irq, dma_playback, dma_capture);
1480 
1481   if (num_audiodevs < MAX_AUDIO_DEV)
1482     {
1483       audio_devs[my_dev = num_audiodevs++] = &ad1848_pcm_operations[nr_ad1848_devs];
1484       if (irq > 0)
1485         {
1486           audio_devs[my_dev]->devc = devc;
1487           irq2dev[irq] = devc->dev_no = my_dev;
1488           if (snd_set_irq_handler (devc->irq, ad1848_interrupt,
1489                                    audio_devs[my_dev]->name,
1490                                    devc->osp) < 0)
1491             {
1492               printk ("ad1848: IRQ in use\n");
1493             }
1494 
1495 #ifdef NO_IRQ_TEST
1496           if (devc->mode != MD_1848)
1497             {
1498               int             x;
1499               unsigned char   tmp = ad_read (devc, 16);
1500 
1501               devc->timer_ticks = 0;
1502 
1503               ad_write (devc, 21, 0x00);        /* Timer msb */
1504               ad_write (devc, 20, 0x10);        /* Timer lsb */
1505 
1506               ad_write (devc, 16, tmp | 0x40);  /* Enable timer */
1507               for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1508               ad_write (devc, 16, tmp & ~0x40);         /* Disable timer */
1509 
1510               if (devc->timer_ticks == 0)
1511                 printk ("[IRQ conflict???]");
1512               else
1513                 devc->irq_ok = 1;
1514 
1515             }
1516           else
1517             devc->irq_ok = 1;   /* Couldn't test. assume it's OK */
1518 #else
1519           devc->irq_ok = 1;
1520 #endif
1521         }
1522       else if (irq < 0)
1523         irq2dev[-irq] = devc->dev_no = my_dev;
1524 
1525       audio_devs[my_dev]->dmachan1 = dma_playback;
1526       audio_devs[my_dev]->dmachan2 = dma_capture;
1527       audio_devs[my_dev]->buffsize = DSP_BUFFSIZE;
1528       audio_devs[my_dev]->devc = devc;
1529       audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1530       nr_ad1848_devs++;
1531 
1532 #ifdef CONFIG_SEQUENCER
1533       if (devc->mode != MD_1848 && devc->mode != MD_1845 && devc->irq_ok)
1534         ad1848_tmr_install (my_dev);
1535 #endif
1536 
1537       if (!share_dma)
1538         {
1539           if (sound_alloc_dma (dma_playback, "Sound System"))
1540             printk ("ad1848.c: Can't allocate DMA%d\n", dma_playback);
1541 
1542           if (dma_capture != dma_playback)
1543             if (sound_alloc_dma (dma_capture, "Sound System (capture)"))
1544               printk ("ad1848.c: Can't allocate DMA%d\n", dma_capture);
1545         }
1546 
1547       /*
1548          * Toggle the MCE bit. It completes the initialization phase.
1549        */
1550 
1551       ad_enter_MCE (devc);      /* In case the bit was off */
1552       ad_leave_MCE (devc);
1553 
1554       if (num_mixers < MAX_MIXER_DEV)
1555         {
1556           mixer2codec[num_mixers] = my_dev + 1;
1557           audio_devs[my_dev]->mixer_dev = num_mixers;
1558           mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1559           ad1848_mixer_reset (devc);
1560         }
1561     }
1562   else
1563     printk ("AD1848: Too many PCM devices available\n");
1564 }
1565 
1566 void
1567 ad1848_unload (int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
     /*  */
1568 {
1569   int             i, dev = 0;
1570   ad1848_info    *devc = NULL;
1571 
1572   for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
1573     if (dev_info[i].base == io_base)
1574       {
1575         devc = &dev_info[i];
1576         dev = devc->dev_no;
1577       }
1578 
1579   if (devc != NULL)
1580     {
1581       release_region (devc->base, 4);
1582 
1583       if (!share_dma)
1584         {
1585           if (irq > 0)
1586             snd_release_irq (devc->irq);
1587 
1588           sound_free_dma (audio_devs[dev]->dmachan1);
1589 
1590           if (audio_devs[dev]->dmachan2 != audio_devs[dev]->dmachan1)
1591             sound_free_dma (audio_devs[dev]->dmachan2);
1592         }
1593     }
1594   else
1595     printk ("ad1848: Can't find device to be undoaded. Base=%x\n",
1596             io_base);
1597 }
1598 
1599 void
1600 ad1848_interrupt (int irq, void *dev_id, struct pt_regs *dummy)
     /*  */
1601 {
1602   unsigned char   status;
1603   ad1848_info    *devc;
1604   int             dev;
1605   int             alt_stat = 0xff;
1606 
1607   if (irq < 0 || irq > 15)
1608     {
1609       dev = -1;
1610     }
1611   else
1612     dev = irq2dev[irq];
1613 
1614   if (dev < 0 || dev >= num_audiodevs)
1615     {
1616       for (irq = 0; irq < 17; irq++)
1617         if (irq2dev[irq] != -1)
1618           break;
1619 
1620       if (irq > 15)
1621         {
1622           /* printk ("ad1848.c: Bogus interrupt %d\n", irq); */
1623           return;
1624         }
1625 
1626       dev = irq2dev[irq];
1627       devc = (ad1848_info *) audio_devs[dev]->devc;
1628     }
1629   else
1630     devc = (ad1848_info *) audio_devs[dev]->devc;
1631 
1632   status = inb (io_Status (devc));
1633 
1634   if (status == 0x80)
1635     printk ("ad1848_interrupt: Why?\n");
1636 
1637   if (status & 0x01)
1638     {
1639 
1640       if (devc->mode != MD_1848)
1641         alt_stat = ad_read (devc, 24);
1642 
1643       if (devc->opened && devc->irq_mode & PCM_ENABLE_INPUT && alt_stat & 0x20)
1644         {
1645           DMAbuf_inputintr (dev);
1646         }
1647 
1648       if (devc->opened && devc->irq_mode & PCM_ENABLE_OUTPUT &&
1649           alt_stat & 0x10)
1650         {
1651           DMAbuf_outputintr (dev, 1);
1652         }
1653 
1654       if (devc->mode != MD_1848 && alt_stat & 0x40)     /* Timer interrupt */
1655         {
1656           devc->timer_ticks++;
1657 #ifdef CONFIG_SEQUENCER
1658           if (timer_installed == dev && devc->timer_running)
1659             sound_timer_interrupt ();
1660 #endif
1661         }
1662     }
1663 
1664   if (devc->mode != MD_1848)
1665     ad_write (devc, 24, ad_read (devc, 24) & ~alt_stat);        /* Selective ack */
1666   else
1667     outb (0, io_Status (devc)); /* Clear interrupt status */
1668 }
1669 
1670 /*
1671  * Some extra code for the MS Sound System
1672  */
1673 
1674 void
1675 check_opl3 (int base, struct address_info *hw_config)
     /*  */
1676 {
1677 
1678 #ifdef CONFIG_YM3812
1679   if (check_region (base, 4))
1680     {
1681       printk ("\n\nopl3.c: I/O port %x already in use\n\n", base);
1682       return;
1683     }
1684 
1685   if (!opl3_detect (base, hw_config->osp))
1686     return;
1687 
1688   opl3_init (0, base, hw_config->osp);
1689   request_region (base, 4, "OPL3/OPL2");
1690 #endif
1691 }
1692 
1693 int
1694 probe_ms_sound (struct address_info *hw_config)
     /*  */
1695 {
1696   unsigned char   tmp;
1697 
1698   DDB (printk ("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
1699 
1700   if (check_region (hw_config->io_base, 8))
1701     {
1702       printk ("MSS: I/O port conflict\n");
1703       return 0;
1704     }
1705 
1706   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1707     {
1708       /* check_opl3(0x388, hw_config); */
1709       return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1710     }
1711 
1712   /*
1713      * Check if the IO port returns valid signature. The original MS Sound
1714      * system returns 0x04 while some cards (AudioTriX Pro for example)
1715      * return 0x00 or 0x0f.
1716    */
1717 
1718   if ((tmp = inb (hw_config->io_base + 3)) == 0xff)     /* Bus float */
1719     {
1720       int             ret;
1721 
1722       DDB (printk ("I/O address is inactive (%x)\n", tmp));
1723       if (!(ret = ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp)))
1724         return 0;
1725       return 1;
1726     }
1727   if ((tmp & 0x3f) != 0x04 &&
1728       (tmp & 0x3f) != 0x0f &&
1729       (tmp & 0x3f) != 0x00)
1730     {
1731       int             ret;
1732 
1733       DDB (printk ("No MSS signature detected on port 0x%x (0x%x)\n",
1734                    hw_config->io_base, inb (hw_config->io_base + 3)));
1735       DDB (printk ("Trying to detect codec anyway but IRQ/DMA may not work\n"));
1736       if (!(ret = ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp)))
1737         return 0;
1738 
1739       return 1;
1740     }
1741 
1742   if (hw_config->irq > 11)
1743     {
1744       printk ("MSS: Bad IRQ %d\n", hw_config->irq);
1745       return 0;
1746     }
1747 
1748   if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
1749     {
1750       printk ("MSS: Bad DMA %d\n", hw_config->dma);
1751       return 0;
1752     }
1753 
1754   /*
1755      * Check that DMA0 is not in use with a 8 bit board.
1756    */
1757 
1758   if (hw_config->dma == 0 && inb (hw_config->io_base + 3) & 0x80)
1759     {
1760       printk ("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1761       return 0;
1762     }
1763 
1764   if (hw_config->irq > 7 && hw_config->irq != 9 && inb (hw_config->io_base + 3) & 0x80)
1765     {
1766       printk ("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1767       return 0;
1768     }
1769 
1770   return ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp);
1771 }
1772 
1773 long
1774 attach_ms_sound (long mem_start, struct address_info *hw_config)
     /*  */
1775 {
1776   static char     interrupt_bits[12] =
1777   {
1778     -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1779   };
1780   char            bits;
1781 
1782   static char     dma_bits[4] =
1783   {
1784     1, 2, 0, 3
1785   };
1786 
1787   int             config_port = hw_config->io_base + 0;
1788   int             version_port = hw_config->io_base + 3;
1789 
1790   if (!ad1848_detect (hw_config->io_base + 4, NULL, hw_config->osp))
1791     return mem_start;
1792 
1793   if (hw_config->card_subtype == 1)     /* Has no IRQ/DMA registers */
1794     {
1795       ad1848_init ("MS Sound System", hw_config->io_base + 4,
1796                    hw_config->irq,
1797                    hw_config->dma,
1798                    hw_config->dma2, 0, hw_config->osp);
1799       request_region (hw_config->io_base, 4, "WSS config");
1800       return mem_start;
1801     }
1802 
1803   /*
1804      * Set the IRQ and DMA addresses.
1805    */
1806 
1807   bits = interrupt_bits[hw_config->irq];
1808   if (bits == -1)
1809     return mem_start;
1810 
1811   outb (bits | 0x40, config_port);
1812   if ((inb (version_port) & 0x40) == 0)
1813     printk ("[IRQ Conflict?]");
1814 
1815   outb (bits | dma_bits[hw_config->dma], config_port);  /* Write IRQ+DMA setup */
1816 
1817   ad1848_init ("MS Sound System", hw_config->io_base + 4,
1818                hw_config->irq,
1819                hw_config->dma,
1820                hw_config->dma, 0, hw_config->osp);
1821   request_region (hw_config->io_base, 4, "WSS config");
1822   return mem_start;
1823 }
1824 
1825 void
1826 unload_ms_sound (struct address_info *hw_config)
     /*  */
1827 {
1828   ad1848_unload (hw_config->io_base + 4,
1829                  hw_config->irq,
1830                  hw_config->dma,
1831                  hw_config->dma, 0);
1832   release_region (hw_config->io_base, 4);
1833 }
1834 
1835 /*
1836  * WSS compatible PnP codec support
1837  */
1838 
1839 int
1840 probe_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1841 {
1842   return ad1848_detect (hw_config->io_base, NULL, hw_config->osp);
1843 }
1844 
1845 long
1846 attach_pnp_ad1848 (long mem_start, struct address_info *hw_config)
     /*  */
1847 {
1848 
1849   ad1848_init (hw_config->name, hw_config->io_base,
1850                hw_config->irq,
1851                hw_config->dma,
1852                hw_config->dma2, 0, hw_config->osp);
1853   return mem_start;
1854 }
1855 
1856 void
1857 unload_pnp_ad1848 (struct address_info *hw_config)
     /*  */
1858 {
1859   ad1848_unload (hw_config->io_base,
1860                  hw_config->irq,
1861                  hw_config->dma,
1862                  hw_config->dma2, 0);
1863   release_region (hw_config->io_base, 4);
1864 }
1865 
1866 #ifdef CONFIG_SEQUENCER
1867 /*
1868  * Timer stuff (for /dev/music).
1869  */
1870 
1871 static unsigned int current_interval = 0;
1872 
1873 static unsigned int
1874 ad1848_tmr_start (int dev, unsigned int usecs)
     /*  */
1875 {
1876   unsigned long   flags;
1877   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1878   unsigned long   xtal_nsecs;   /* nanoseconds per xtal oscillaror tick */
1879   unsigned long   divider;
1880 
1881   save_flags (flags);
1882   cli ();
1883 
1884 /*
1885  * Length of the timer interval (in nanoseconds) depends on the
1886  * selected crystal oscillator. Check this from bit 0x01 of I8.
1887  *
1888  * AD1845 has just one oscillator which has cycle time of 10.050 us
1889  * (when a 24.576 MHz xtal oscillator is used).
1890  *
1891  * Convert requested interval to nanoseconds before computing
1892  * the timer divider.
1893  */
1894 
1895   if (devc->mode == MD_1845)
1896     xtal_nsecs = 10050;
1897   else if (ad_read (devc, 8) & 0x01)
1898     xtal_nsecs = 9920;
1899   else
1900     xtal_nsecs = 9969;
1901 
1902   divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
1903 
1904   if (divider < 100)            /* Don't allow shorter intervals than about 1ms */
1905     divider = 100;
1906 
1907   if (divider > 65535)          /* Overflow check */
1908     divider = 65535;
1909 
1910   ad_write (devc, 21, (divider >> 8) & 0xff);   /* Set upper bits */
1911   ad_write (devc, 20, divider & 0xff);  /* Set lower bits */
1912   ad_write (devc, 16, ad_read (devc, 16) | 0x40);       /* Start the timer */
1913   devc->timer_running = 1;
1914   restore_flags (flags);
1915 
1916   return current_interval = (divider * xtal_nsecs + 500) / 1000;
1917 }
1918 
1919 static void
1920 ad1848_tmr_reprogram (int dev)
     /*  */
1921 {
1922 /*
1923  *    Audio driver has changed sampling rate so that a different xtal
1924  *      oscillator was selected. We have to reprogram the timer rate.
1925  */
1926 
1927   ad1848_tmr_start (dev, current_interval);
1928   sound_timer_syncinterval (current_interval);
1929 }
1930 
1931 static void
1932 ad1848_tmr_disable (int dev)
     /*  */
1933 {
1934   unsigned long   flags;
1935   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1936 
1937   save_flags (flags);
1938   cli ();
1939   ad_write (devc, 16, ad_read (devc, 16) & ~0x40);
1940   devc->timer_running = 0;
1941   restore_flags (flags);
1942 }
1943 
1944 static void
1945 ad1848_tmr_restart (int dev)
     /*  */
1946 {
1947   unsigned long   flags;
1948   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1949 
1950   if (current_interval == 0)
1951     return;
1952 
1953   save_flags (flags);
1954   cli ();
1955   ad_write (devc, 16, ad_read (devc, 16) | 0x40);
1956   devc->timer_running = 1;
1957   restore_flags (flags);
1958 }
1959 
1960 static struct sound_lowlev_timer ad1848_tmr =
1961 {
1962   0,
1963   ad1848_tmr_start,
1964   ad1848_tmr_disable,
1965   ad1848_tmr_restart
1966 };
1967 
1968 static int
1969 ad1848_tmr_install (int dev)
     /*  */
1970 {
1971 
1972   if (timer_installed != -1)
1973     return 0;                   /* Don't install another timer */
1974 
1975   timer_installed = ad1848_tmr.dev = dev;
1976   sound_timer_init (&ad1848_tmr, audio_devs[dev]->name);
1977 
1978   return 1;
1979 }
1980 #endif
1981 #endif
/* */
root/drivers/sound/ad1848.c

DEFINITIONS
