include/asm-alpha/alcor.h

/* */
This source file includes following definitions.
virt_to_bus
bus_to_virt
__inb
__outb
__inw
__outw
__inl
__outl
__readb
__readw
__readl
__writeb
__writew
__writel
   1 #ifndef __ALPHA_ALCOR__H__
   2 #define __ALPHA_ALCOR__H__
   3 
   4 #include <linux/types.h>
   5 
   6 /*
   7  * ALCOR is the internal name for the 2117x chipset which provides
   8  * memory controller and PCI access for the 21164 chip based systems.
   9  *
  10  * This file is based on:
  11  *
  12  * DECchip 21171 Core Logic Chipset 
  13  * Technical Reference Manual
  14  *
  15  * EC-QE18B-TE
  16  *
  17  * david.rusling@reo.mts.dec.com Initial Version.
  18  *
  19  */
  20 
  21 /*------------------------------------------------------------------------**
  22 **                                                                        **
  23 **  EB164 I/O procedures                                                   **
  24 **                                                                        **
  25 **      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
  26 **      inportbxt: 8 bits only                                            **
  27 **      inport:    alias of inportw                                       **
  28 **      outport:   alias of outportw                                      **
  29 **                                                                        **
  30 **      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
  31 **      inmembxt: 8 bits only                                             **
  32 **      inmem:    alias of inmemw                                         **
  33 **      outmem:   alias of outmemw                                        **
  34 **                                                                        **
  35 **------------------------------------------------------------------------*/
  36 
  37 
  38 /* ALCOR ADDRESS BIT DEFINITIONS
  39  *
  40  *  3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
  41  *  9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  42  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  43  * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0|
  44  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 
  45  *  |                                                                        \_/ \_/
  46  *  |                                                                         |   |
  47  *  +-- IO space, not cached.                                   Byte Enable --+   |
  48  *                                                              Transfer Length --+
  49  *
  50  *
  51  *
  52  *   Byte      Transfer
  53  *   Enable    Length    Transfer  Byte    Address
  54  *   adr<6:5>  adr<4:3>  Length    Enable  Adder
  55  *   ---------------------------------------------
  56  *      00        00      Byte      1110   0x000
  57  *      01        00      Byte      1101   0x020
  58  *      10        00      Byte      1011   0x040
  59  *      11        00      Byte      0111   0x060
  60  *
  61  *      00        01      Word      1100   0x008
  62  *      01        01      Word      1001   0x028 <= Not supported in this code.
  63  *      10        01      Word      0011   0x048
  64  *
  65  *      00        10      Tribyte   1000   0x010
  66  *      01        10      Tribyte   0001   0x030
  67  *
  68  *      10        11      Longword  0000   0x058
  69  *
  70  *      Note that byte enables are asserted low.
  71  *
  72  */
  73 
  74 #define BYTE_ENABLE_SHIFT 5
  75 #define TRANSFER_LENGTH_SHIFT 3
  76 #define MEM_SP1_MASK 0x1fffffff  /* Mem sparse space 1 mask is 29 bits */
  77 
  78 
  79 #define ALCOR_DMA_WIN_BASE      (1024UL*1024UL*1024UL)
  80 #define ALCOR_DMA_WIN_SIZE      (1024*1024*1024)
  81 
  82 /*
  83  * 21171-CA Control and Status Registers (p4-1)
  84  */
  85 #define ALCOR_IOC_CIA_REV               (IDENT_ADDR + 0x8740000080UL)
  86 #define ALCOR_IOC_PCI_LAT               (IDENT_ADDR + 0x87400000C0UL)
  87 #define ALCOR_IOC_CIA_CTRL              (IDENT_ADDR + 0x8740000100UL)
  88 #define ALCOR_IOC_HAE_MEM               (IDENT_ADDR + 0x8740000400UL)
  89 #define ALCOR_IOC_HAE_IO                (IDENT_ADDR + 0x8740000440UL)
  90 #define ALCOR_IOC_CFG                   (IDENT_ADDR + 0x8740000480UL)
  91 #define ALCOR_IOC_CACK_EN               (IDENT_ADDR + 0x8740000600UL)
  92 
  93 /*
  94  * 21171-CA Diagnostic Registers (p4-2)
  95  */
  96 #define ALCOR_IOC_CIA_DIAG              (IDENT_ADDR + 0x8740002000UL)
  97 #define ALCOR_IOC_DIAG_CHECK            (IDENT_ADDR + 0x8740003000UL)
  98 
  99 /*
 100  * 21171-CA Performance Monitor registers (p4-3)
 101  */
 102 #define ALCOR_IOC_PERF_MONITOR          (IDENT_ADDR + 0x8740004000UL)
 103 #define ALCOR_IOC_PERF_CONTROL          (IDENT_ADDR + 0x8740004040UL)
 104 
 105 /*
 106  * 21171-CA Error registers (p4-3)
 107  */
 108 #define ALCOR_IOC_CPU_ERR0              (IDENT_ADDR + 0x8740008000UL)
 109 #define ALCOR_IOC_CPU_ERR1              (IDENT_ADDR + 0x8740008040UL)
 110 #define ALCOR_IOC_CIA_ERR               (IDENT_ADDR + 0x8740008200UL)
 111 #define ALCOR_IOC_CIA_STAT              (IDENT_ADDR + 0x8740008240UL)
 112 #define ALCOR_IOC_ERR_MASK              (IDENT_ADDR + 0x8740008280UL)
 113 #define ALCOR_IOC_CIA_SYN               (IDENT_ADDR + 0x8740008300UL)
 114 #define ALCOR_IOC_MEM_ERR0              (IDENT_ADDR + 0x8740008400UL)
 115 #define ALCOR_IOC_MEM_ERR1              (IDENT_ADDR + 0x8740008440UL)
 116 #define ALCOR_IOC_PCI_ERR0              (IDENT_ADDR + 0x8740008800UL)
 117 #define ALCOR_IOC_PCI_ERR1              (IDENT_ADDR + 0x8740008840UL)
 118 #define ALCOR_IOC_PCI_ERR3              (IDENT_ADDR + 0x8740008880UL)
 119 
 120 /*
 121  * 2117A-CA PCI Address Translation Registers.   I've only defined
 122  * the first window fully as that's the only one that we're currently using.
 123  * The other window bases are needed to disable the windows.
 124  */
 125 #define ALCOR_IOC_PCI_TBIA              (IDENT_ADDR + 0x8760000100UL)
 126 #define ALCOR_IOC_PCI_W0_BASE           (IDENT_ADDR + 0x8760000400UL)
 127 #define ALCOR_IOC_PCI_W0_MASK           (IDENT_ADDR + 0x8760000440UL)
 128 #define ALCOR_IOC_PCI_T0_BASE           (IDENT_ADDR + 0x8760000480UL)
 129 
 130 #define ALCOR_IOC_PCI_W1_BASE           (IDENT_ADDR + 0x8760000500UL)
 131 #define ALCOR_IOC_PCI_W2_BASE           (IDENT_ADDR + 0x8760000600UL)
 132 #define ALCOR_IOC_PCI_W3_BASE           (IDENT_ADDR + 0x8760000700UL)
 133 
 134 /*
 135  * 21171-CA System configuration registers (p4-3)
 136  */
 137 #define ALCOR_IOC_MCR                   (IDENT_ADDR + 0x8750000000UL)
 138 #define ALCOR_IOC_MBA0                  (IDENT_ADDR + 0x8750000600UL)
 139 #define ALCOR_IOC_MBA2                  (IDENT_ADDR + 0x8750000680UL)
 140 #define ALCOR_IOC_MBA4                  (IDENT_ADDR + 0x8750000700UL)
 141 #define ALCOR_IOC_MBA6                  (IDENT_ADDR + 0x8750000780UL)
 142 #define ALCOR_IOC_MBA8                  (IDENT_ADDR + 0x8750000800UL)
 143 #define ALCOR_IOC_MBAA                  (IDENT_ADDR + 0x8750000880UL)
 144 #define ALCOR_IOC_MBAC                  (IDENT_ADDR + 0x8750000900UL)
 145 #define ALCOR_IOC_MBAE                  (IDENT_ADDR + 0x8750000980UL)
 146 #define ALCOR_IOC_TMG0                  (IDENT_ADDR + 0x8750000B00UL)
 147 #define ALCOR_IOC_TMG1                  (IDENT_ADDR + 0x8750000B40UL)
 148 #define ALCOR_IOC_TMG2                  (IDENT_ADDR + 0x8750000B80UL)
 149 
 150 /*
 151  * Memory spaces:
 152  */
 153 #define ALCOR_IACK_SC                   (IDENT_ADDR + 0x8720000000UL)
 154 #define ALCOR_CONF                      (IDENT_ADDR + 0x8700000000UL)
 155 #define ALCOR_IO                        (IDENT_ADDR + 0x8580000000UL)
 156 #define ALCOR_SPARSE_MEM                (IDENT_ADDR + 0x8000000000UL)
 157 #define ALCOR_DENSE_MEM                 (IDENT_ADDR + 0x8600000000UL)
 158 
 159 /*
 160  * Bit definitions for I/O Controller status register 0:
 161  */
 162 #define ALCOR_IOC_STAT0_CMD             0xf
 163 #define ALCOR_IOC_STAT0_ERR             (1<<4)
 164 #define ALCOR_IOC_STAT0_LOST            (1<<5)
 165 #define ALCOR_IOC_STAT0_THIT            (1<<6)
 166 #define ALCOR_IOC_STAT0_TREF            (1<<7)
 167 #define ALCOR_IOC_STAT0_CODE_SHIFT      8
 168 #define ALCOR_IOC_STAT0_CODE_MASK       0x7
 169 #define ALCOR_IOC_STAT0_P_NBR_SHIFT     13
 170 #define ALCOR_IOC_STAT0_P_NBR_MASK      0x7ffff
 171 
 172 #define HAE_ADDRESS                     ALCOR_IOC_HAE_MEM
 173 
 174 #ifdef __KERNEL__
 175 
 176 /*
 177  * Translate physical memory address as seen on (PCI) bus into
 178  * a kernel virtual address and vv.
 179  */
 180 extern inline unsigned long virt_to_bus(void * address)
     /*  */
 181 {
 182         return virt_to_phys(address) + ALCOR_DMA_WIN_BASE;
 183 }
 184 
 185 extern inline void * bus_to_virt(unsigned long address)
     /*  */
 186 {
 187         return phys_to_virt(address - ALCOR_DMA_WIN_BASE);
 188 }
 189 
 190 /*
 191  * I/O functions:
 192  *
 193  * Alcor (the 2117x PCI/memory support chipset for the EV5 (21164)
 194  * series of processors uses a sparse address mapping scheme to
 195  * get at PCI memory and I/O.
 196  */
 197 
 198 #define vuip    volatile unsigned int *
 199 
 200 extern inline unsigned int __inb(unsigned long addr)
     /*  */
 201 {
 202         long result = *(vuip) ((addr << 5) + ALCOR_IO + 0x00);
 203         result >>= (addr & 3) * 8;
 204         return 0xffUL & result;
 205 }
 206 
 207 extern inline void __outb(unsigned char b, unsigned long addr)
     /*  */
 208 {
 209         unsigned int w;
 210 
 211         asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 212         *(vuip) ((addr << 5) + ALCOR_IO + 0x00) = w;
 213         mb();
 214 }
 215 
 216 extern inline unsigned int __inw(unsigned long addr)
     /*  */
 217 {
 218         long result = *(vuip) ((addr << 5) + ALCOR_IO + 0x08);
 219         result >>= (addr & 3) * 8;
 220         return 0xffffUL & result;
 221 }
 222 
 223 extern inline void __outw(unsigned short b, unsigned long addr)
     /*  */
 224 {
 225         unsigned int w;
 226 
 227         asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 228         *(vuip) ((addr << 5) + ALCOR_IO + 0x08) = w;
 229         mb();
 230 }
 231 
 232 extern inline unsigned int __inl(unsigned long addr)
     /*  */
 233 {
 234         return *(vuip) ((addr << 5) + ALCOR_IO + 0x18);
 235 }
 236 
 237 extern inline void __outl(unsigned int b, unsigned long addr)
     /*  */
 238 {
 239         *(vuip) ((addr << 5) + ALCOR_IO + 0x18) = b;
 240         mb();
 241 }
 242 
 243 
 244 /*
 245  * Memory functions.  64-bit and 32-bit accesses are done through
 246  * dense memory space, everything else through sparse space.
 247  * 
 248  * For reading and writing 8 and 16 bit quantities we need to 
 249  * go through one of the three sparse address mapping regions
 250  * and use the HAE_MEM CSR to provide some bits of the address.
 251  * The following few routines use only sparse address region 1
 252  * which gives 1Gbyte of accessible space which relates exactly
 253  * to the amount of PCI memory mapping *into* system address space.
 254  * See p 6-17 of the specification but it looks something like this:
 255  *
 256  * 21164 Address:
 257  * 
 258  *          3         2         1                                                               
 259  * 9876543210987654321098765432109876543210
 260  * 1ZZZZ0.PCI.QW.Address............BBLL                 
 261  *
 262  * ZZ = SBZ
 263  * BB = Byte offset
 264  * LL = Transfer length
 265  *
 266  * PCI Address:
 267  *
 268  * 3         2         1                                                               
 269  * 10987654321098765432109876543210
 270  * HHH....PCI.QW.Address........ 00
 271  *
 272  * HHH = 31:29 HAE_MEM CSR
 273  * 
 274  */
 275 
 276 extern inline unsigned long __readb(unsigned long addr)
     /*  */
 277 {
 278         unsigned long result, shift, msb;
 279 
 280         shift = (addr & 0x3) * 8 ;
 281         msb = addr & 0xE0000000 ;
 282         addr &= MEM_SP1_MASK ;
 283         if (msb != hae.cache) {
 284           set_hae(msb);
 285         }
 286         result = *(vuip) ((addr << 5) + ALCOR_SPARSE_MEM + 0x00) ;
 287         result >>= shift;
 288         return 0xffUL & result;
 289 }
 290 
 291 extern inline unsigned long __readw(unsigned long addr)
     /*  */
 292 {
 293         unsigned long result, shift, msb;
 294 
 295         shift = (addr & 0x3) * 8;
 296         msb = addr & 0xE0000000 ;
 297         addr &= MEM_SP1_MASK ;
 298         if (msb != hae.cache) {
 299           set_hae(msb);
 300         }
 301         result = *(vuip) ((addr << 5) + ALCOR_SPARSE_MEM + 0x08);
 302         result >>= shift;
 303         return 0xffffUL & result;
 304 }
 305 
 306 extern inline unsigned long __readl(unsigned long addr)
     /*  */
 307 {
 308         return *(vuip) (addr + ALCOR_DENSE_MEM);
 309 }
 310 
 311 extern inline void __writeb(unsigned char b, unsigned long addr)
     /*  */
 312 {
 313         unsigned long msb ; 
 314 
 315         msb = addr & 0xE0000000 ;
 316         addr &= MEM_SP1_MASK ;
 317         if (msb != hae.cache) {
 318           set_hae(msb);
 319         }
 320         *(vuip) ((addr << 5) + ALCOR_SPARSE_MEM + 0x00) = b * 0x01010101;
 321 }
 322 
 323 extern inline void __writew(unsigned short b, unsigned long addr)
     /*  */
 324 {
 325         unsigned long msb ; 
 326 
 327         msb = addr & 0xE0000000 ;
 328         addr &= MEM_SP1_MASK ;
 329         if (msb != hae.cache) {
 330           set_hae(msb);
 331         }
 332         *(vuip) ((addr << 5) + ALCOR_SPARSE_MEM + 0x08) = b * 0x00010001;
 333 }
 334 
 335 extern inline void __writel(unsigned int b, unsigned long addr)
     /*  */
 336 {
 337         *(vuip) (addr + ALCOR_DENSE_MEM) = b;
 338 }
 339 
 340 #define inb(port) \
 341 (__builtin_constant_p((port))?__inb(port):_inb(port))
 342 
 343 #define outb(x, port) \
 344 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 345 
 346 #define readl(a)        __readl((unsigned long)(a))
 347 #define writel(v,a)     __writel((v),(unsigned long)(a))
 348 
 349 #undef vuip
 350 
 351 extern unsigned long alcor_init (unsigned long mem_start,
 352                                  unsigned long mem_end);
 353 
 354 #endif /* __KERNEL__ */
 355 
 356 /*
 357  * Data structure for handling ALCOR machine checks:
 358  */
 359 struct el_ALCOR_sysdata_mcheck {
 360     u_long      coma_gcr;                       
 361     u_long      coma_edsr;                      
 362     u_long      coma_ter;                       
 363     u_long      coma_elar;                      
 364     u_long      coma_ehar;                      
 365     u_long      coma_ldlr;                      
 366     u_long      coma_ldhr;                      
 367     u_long      coma_base0;                     
 368     u_long      coma_base1;                     
 369     u_long      coma_base2;                     
 370     u_long      coma_cnfg0;                     
 371     u_long      coma_cnfg1;                     
 372     u_long      coma_cnfg2;                     
 373     u_long      epic_dcsr;                      
 374     u_long      epic_pear;                      
 375     u_long      epic_sear;                      
 376     u_long      epic_tbr1;                      
 377     u_long      epic_tbr2;                      
 378     u_long      epic_pbr1;                      
 379     u_long      epic_pbr2;                      
 380     u_long      epic_pmr1;                      
 381     u_long      epic_pmr2;                      
 382     u_long      epic_harx1;                     
 383     u_long      epic_harx2;                     
 384     u_long      epic_pmlt;                      
 385     u_long      epic_tag0;                      
 386     u_long      epic_tag1;                      
 387     u_long      epic_tag2;                      
 388     u_long      epic_tag3;                      
 389     u_long      epic_tag4;                      
 390     u_long      epic_tag5;                      
 391     u_long      epic_tag6;                      
 392     u_long      epic_tag7;                      
 393     u_long      epic_data0;                     
 394     u_long      epic_data1;                     
 395     u_long      epic_data2;                     
 396     u_long      epic_data3;                     
 397     u_long      epic_data4;                     
 398     u_long      epic_data5;                     
 399     u_long      epic_data6;                     
 400     u_long      epic_data7;                     
 401 };
 402 
 403 #define RTC_PORT(x)     (0x70 + (x))
 404 #define RTC_ADDR(x)     (0x80 | (x))
 405 #define RTC_ALWAYS_BCD  0
 406 
 407 #endif /* __ALPHA_ALCOR__H__ */
/* */
root/include/asm-alpha/alcor.h

INCLUDED FROM

DEFINITIONS
