drivers/net/pt.c

/* */
This source file includes following definitions.
pt0_preprobe
random
wrtscc
rdscc
switchbuffers
hardware_send_packet
setup_rx_dma
setup_tx_dma
free_p
pt_loopback
pt_header
pt_rebuild_header
scc_init
chipset_init
pt_init
hw_probe
pt_rts
valid_dma_page
pt_set_mac_address
get_dma_buffer
pt_probe
pt_open
pt_send_packet
pt_close
pt_ioctl
pt_get_stats
tdelay
pt_txisr
pt_rxisr
empty_scc
pt_tmrisr
pt_interrupt
pt_exisr
send_kiss
   1 #undef PT_DEBUG 1
   2 /*
   3  * pt.c: Linux device driver for the Gracilis PackeTwin.
   4  * Copyright (c) 1995 Craig Small VK2XLZ (vk2xlz@vk2xlz.ampr.org.)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge MA 02139, USA.
  18  *
  19  * This driver is largely based upon the PI driver by David Perry.
  20  *
  21  * Revision History
  22  * 23/02/95 cs  Started again on driver, last one scrapped
  23  * 27/02/95 cs  Program works, we have chan A only.  Tx stays on
  24  * 28/02/95 cs  Fix Tx problem (& TxUIE instead of | )
  25  *              Fix Chan B Tx timer problem, used TMR2 instead of TMR1
  26  * 03/03/95 cs  Painfully found out (after 3 days) SERIAL_CFG is write only
  27  *              created image of it and DMA_CFG
  28  * 21/06/95 cs  Upgraded to suit PI driver 0.8 ALPHA
  29  * 22/08/95     cs      Changed it all around to make it like pi driver
  30  * 23/08/95 cs  It now works, got caught again by TMR2 and we must have
  31  *                              auto-enables for daughter boards.
  32  * 07/10/95 cs  Fixed for 1.3.30 (hopefully)
  33  * 26/11/95 cs  Fixed for 1.3.43, ala 29/10 for pi2.c by ac
  34  * 21/12/95 cs  Got rid of those nasty warnings when compiling, for 1.3.48
  35  */
  36  
  37 /* 
  38  * default configuration of the PackeTwin,
  39  * ie What Craig uses his PT for.
  40  */
  41 #define PT_DMA 3
  42 
  43 #define DEF_A_SPEED     4800            /* 4800 baud */
  44 #define DEF_A_TXDELAY   350             /* 350 mS */
  45 #define DEF_A_PERSIST   64              /* 25% persistance */
  46 #define DEF_A_SLOTIME   10              /* 10 mS */
  47 #define DEF_A_SQUELDELAY 30             /* 30 mS */
  48 #define DEF_A_CLOCKMODE 0               /* Normal clock mode */
  49 #define DEF_A_NRZI              1               /* NRZI mode */
  50 
  51 #define DEF_B_SPEED     0               /* 0 means external clock */
  52 #define DEF_B_TXDELAY   250             /* 250 mS */
  53 #define DEF_B_PERSIST   64              /* 25% */
  54 #define DEF_B_SLOTIME   10              /* 10 mS */
  55 #define DEF_B_SQUELDELAY 30             /* 30 mS */
  56 #define DEF_B_CLOCKMODE 0               /* Normal clock mode ?!? */
  57 #define DEF_B_NRZI              1               /* NRZI mode */
  58 
  59 
  60 #define PARAM_TXDELAY   1
  61 #define PARAM_PERSIST   2
  62 #define PARAM_SLOTTIME  3
  63 #define PARAM_FULLDUP   5
  64 #define PARAM_HARDWARE  6
  65 #define PARAM_RETURN    255
  66 
  67 #include <linux/kernel.h>
  68 #include <linux/sched.h>
  69 #include <linux/types.h>
  70 #include <linux/fcntl.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/ptrace.h>
  73 #include <linux/ioport.h>
  74 #include <linux/in.h>
  75 #include <linux/malloc.h>
  76 #include <linux/string.h>
  77 #include <linux/errno.h>
  78 #include <asm/system.h>
  79 #include <asm/bitops.h>
  80 #include <asm/io.h>
  81 #include <asm/dma.h>
  82 #include <asm/segment.h>
  83 #include <linux/inet.h>
  84 #include <linux/netdevice.h>
  85 #include <linux/etherdevice.h>
  86 #include <linux/skbuff.h>
  87 #include <linux/timer.h>
  88 #include <linux/if_arp.h>
  89 #include "pt.h"
  90 #include "z8530.h"
  91 #include <net/ax25.h>
  92 
  93 static char *version =
  94 "PT: 0.41 ALPHA 07 October 1995 Craig Small (vk2xlz@vk2xlz.ampr.org)\n";
  95 
  96 
  97 struct mbuf {
  98     struct mbuf *next;
  99     int cnt;
 100     char data[0];
 101 };
 102 
 103 /*
 104  * The actual PT devices we will use
 105  */
 106 static int pt0_preprobe(struct device *dev) {return 0;} /* Dummy probe function */
     /*  */
 107 static struct device pt0a = { "pt0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pt0_preprobe };
 108 static struct device pt0b = { "pt0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pt0_preprobe };
 109 
 110 /* Ok, they shouldn't be here, but both channels share them */
 111 /* The Images of the Serial and DMA config registers */
 112 static unsigned char pt_sercfg = 0;
 113 static unsigned char pt_dmacfg = 0;
 114 
 115 /* The number of IO ports used by the card */
 116 #define PT_TOTAL_SIZE   16
 117 
 118 /* Index to functions, as function prototypes. */
 119 
 120 static int pt_probe(struct device *dev);
 121 static int pt_open(struct device *dev);
 122 static int pt_send_packet(struct sk_buff *skb, struct device *dev);
 123 static void pt_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 124 static int pt_close(struct device *dev);
 125 static int pt_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
 126 static struct enet_statistics *pt_get_stats(struct device *dev);
 127 static void pt_rts(struct pt_local *lp, int x);
 128 static void pt_rxisr(struct device *dev);
 129 static void pt_txisr(struct pt_local *lp);
 130 static void pt_exisr(struct pt_local *lp);
 131 static void pt_tmrisr(struct pt_local *lp);
 132 static char *get_dma_buffer(unsigned long *mem_ptr);
 133 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize);
 134 static int hw_probe(int ioaddr);
 135 static void tdelay(struct pt_local *lp, int time);
 136 static void empty_scc(struct pt_local *lp);
 137 static void chipset_init(struct device *dev);
 138 static void send_kiss(struct device *dev, unsigned char arg, unsigned char val);
 139 
 140 static char ax25_bcast[7] =
 141 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
 142 static char ax25_test[7] =
 143 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
 144 
 145 
 146 
 147 static int ext2_secrm_seed = 152;
 148 
 149 static inline unsigned char random(void)
     /*  */
 150 {
 151     return (unsigned char) (ext2_secrm_seed = ext2_secrm_seed * 60691 + 1);
 152 }
 153 
 154 static inline void wrtscc(int cbase, int ctl, int sccreg, unsigned char val)
     /*  */
 155 {
 156     outb_p(sccreg, ctl);        /* Select register */
 157     outb_p(val, ctl);           /* Output value */
 158 }
 159 
 160 static inline unsigned char rdscc(int cbase, int ctl, int sccreg)
     /*  */
 161 {
 162     unsigned char retval;
 163 
 164     outb_p(sccreg, ctl);        /* Select register */
 165     retval = inb_p(ctl);
 166     return retval;
 167 }
 168 
 169 static void switchbuffers(struct pt_local *lp)
     /*  */
 170 {
 171     if (lp->rcvbuf == lp->rxdmabuf1)
 172         lp->rcvbuf = lp->rxdmabuf2;
 173     else
 174         lp->rcvbuf = lp->rxdmabuf1;
 175 }
 176                 
 177 static void hardware_send_packet(struct pt_local *lp, struct sk_buff *skb)
     /*  */
 178 {
 179     char kickflag;
 180     unsigned long flags;
 181     char *ptr;
 182     struct device *dev;
 183 
 184         /* First, let's see if this packet is actually a KISS packet */
 185         ptr = skb->data;
 186         if (ptr[0] != 0 && skb->len >= 2)
 187         {
 188                 printk("Rx KISS... Control = %d, value = %d.\n", ptr[0], (skb->len > 1? ptr[1] : -1));
 189                 /* Kludge to get device */
 190                 if ((struct pt_local*)(&pt0b.priv) == lp)
 191                         dev = &pt0b;
 192                 else
 193                         dev = &pt0a;
 194                 switch(ptr[0])
 195                 {
 196 
 197                         case PARAM_TXDELAY:
 198                                 /*TxDelay is in 10mS increments */
 199                                 lp->txdelay = ptr[1] * 10;
 200                                 send_kiss(dev, PARAM_TXDELAY, (u_char)(lp->txdelay/10));
 201                                 break;
 202                         case PARAM_PERSIST:
 203                                 lp->persist = ptr[1];
 204                                 send_kiss(dev, PARAM_PERSIST, (u_char)(lp->persist));
 205                                 break;
 206                         case PARAM_SLOTTIME:
 207                                 lp->slotime = ptr[1];
 208                                 send_kiss(dev, PARAM_SLOTTIME, (u_char)(lp->slotime/10));
 209                                 break;
 210                         case PARAM_FULLDUP:
 211                                 /* Yeah right, you wish!  Fullduplex is a little while to
 212                                  * go folks, but this is how you fire it up
 213                                  */
 214                                 send_kiss(dev, PARAM_FULLDUP, 0);
 215                                 break;
 216                         /* Perhaps we should have txtail here?? */
 217                 } /*switch */
 218                 return;
 219         }
 220         
 221     lp->stats.tx_packets++;
 222 
 223     save_flags(flags);
 224     cli();
 225     kickflag = (skb_peek(&lp->sndq) == NULL) && (lp->sndbuf == NULL);
 226     restore_flags(flags);
 227 
 228 #ifdef PT_DEBUG
 229         printk("PTd hardware_send_packet(): kickflag = %d (%d).\n", kickflag, lp->base & CHANA);
 230 #endif  
 231     skb_queue_tail(&lp->sndq, skb);
 232     if (kickflag) {
 233         /* Simulate interrupt to transmit */
 234             if (lp->dmachan)
 235             {   
 236                 pt_txisr(lp);
 237             } else {
 238                 save_flags(flags);
 239                         cli();
 240                 if (lp->tstate == IDLE)
 241                         pt_txisr(lp); 
 242                 restore_flags(flags);
 243             }
 244     }
 245 } /* hardware_send_packet() */
 246 
 247 static void setup_rx_dma(struct pt_local *lp)
     /*  */
 248 {
 249     unsigned long flags;
 250     int cmd;
 251     unsigned long dma_abs;
 252     unsigned char dmachan;
 253 
 254     save_flags(flags);
 255     cli();
 256 
 257     dma_abs = (unsigned long) (lp->rcvbuf->data);
 258     dmachan = lp->dmachan;
 259     cmd = lp->base + CTL;
 260 
 261     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 262         panic("PI: RX buffer violates DMA boundary!");
 263 
 264     /* Get ready for RX DMA */
 265     wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 266 
 267     disable_dma(dmachan);
 268     clear_dma_ff(dmachan);
 269 
 270     /* Set DMA mode register to single transfers, incrementing address,
 271      *  auto init, writes
 272      */
 273     set_dma_mode(dmachan, DMA_MODE_READ | 0x10);
 274     set_dma_addr(dmachan, dma_abs);
 275     set_dma_count(dmachan, lp->bufsiz);
 276     enable_dma(dmachan);
 277 
 278     /* If a packet is already coming in, this line is supposed to
 279            avoid receiving a partial packet.
 280      */
 281     wrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
 282 
 283     /* Enable RX dma */
 284     wrtscc(lp->cardbase, cmd, R1,
 285       WT_RDY_ENAB | WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 286 
 287     restore_flags(flags);
 288 }
 289 
 290 static void setup_tx_dma(struct pt_local *lp, int length)
     /*  */
 291 {
 292     unsigned long dma_abs;
 293     unsigned long flags;
 294     unsigned long dmachan;
 295 
 296     save_flags(flags);
 297     cli();
 298 
 299     dmachan = lp->dmachan;
 300     dma_abs = (unsigned long) (lp->txdmabuf);
 301 
 302     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 303         panic("PT: TX buffer violates DMA boundary!");
 304 
 305     disable_dma(dmachan);
 306     /* Set DMA mode register to single transfers, incrementing address,
 307      *  no auto init, reads
 308      */
 309     set_dma_mode(dmachan, DMA_MODE_WRITE);
 310     clear_dma_ff(dmachan);
 311     set_dma_addr(dmachan, dma_abs);
 312     /* output byte count */
 313     set_dma_count(dmachan, length);
 314 
 315     restore_flags(flags);
 316 }
 317 
 318 static void free_p(struct sk_buff *skb)
     /*  */
 319 {
 320     dev_kfree_skb(skb, FREE_WRITE);
 321 }
 322 
 323 static void pt_loopback(struct pt_local *lp, int onoff)
     /*  */
 324 {
 325     if (lp->base & CHANA) {
 326         if (onoff == ON)
 327             outb_p(pt_sercfg |= PT_LOOPA_ON, lp->cardbase + SERIAL_CFG);
 328         else
 329             outb_p(pt_sercfg &= ~PT_LOOPA_ON, lp->cardbase + SERIAL_CFG);
 330     } else {    /* it's channel B */
 331         if (onoff == ON)
 332             outb_p(pt_sercfg |= PT_LOOPB_ON, lp->cardbase + SERIAL_CFG);
 333         else
 334             outb_p(pt_sercfg &= ~PT_LOOPB_ON, lp->cardbase + SERIAL_CFG);
 335     }
 336 } /*pt_loopback */
 337 
 338 /* Fill in the MAC-level header */
 339 static int pt_header (struct sk_buff *skb, struct device *dev, unsigned short type,
     /*  */
 340                 void *daddr, void *saddr, unsigned len)
 341 {
 342         return ax25_encapsulate(skb, dev, type, daddr, saddr, len);
 343 }
 344 
 345 
 346 /* Rebuild the MAC-level header */
 347 static int pt_rebuild_header(void *buff, struct device *dev, unsigned long raddr,
     /*  */
 348                                 struct sk_buff *skb)
 349 {
 350         return ax25_rebuild_header(buff, dev, raddr, skb);
 351 }
 352 
 353                                         
 354                                         
 355 
 356 
 357 /*
 358  * This sets up all the registers in the SCC for the given channel
 359  * based upon tsync_hwint()
 360  */
 361 static void scc_init(struct device *dev)
     /*  */
 362 {
 363     unsigned long flags;
 364     struct pt_local *lp = (struct pt_local*) dev->priv;
 365     register int cmd = lp->base + CTL;
 366     int tc, br;
 367 
 368 #ifdef PT_DEBUG
 369         printk("PTd scc_init(): (%d).\n", lp->base & CHANA);
 370 #endif  
 371     save_flags(flags);
 372     cli();
 373 
 374     /* We may put something here to enable_escc */
 375 
 376     if (cmd & CHANA)
 377     {
 378         wrtscc(lp->cardbase, cmd, R9, CHRA);            /* Reset channel A */
 379         wrtscc(lp->cardbase, cmd, R2, 0xff);            /* Initialise interrupt vector */
 380     } else {
 381         wrtscc(lp->cardbase, cmd, R9, CHRB);            /* Reset channel B */
 382     }
 383     
 384     /* Deselect all Rx and Tx interrupts */
 385     wrtscc(lp->cardbase, cmd, R1, 0);
 386     
 387     /* Turn off external interrupts (like CTS/CD) */
 388     wrtscc(lp->cardbase, cmd, R15, 0);
 389            
 390     /* X1 clock, SDLC mode */
 391     wrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
 392         
 393         /* Preset CRC and set mode */
 394         if (lp->nrzi)
 395         {
 396         /* Preset Tx CRC, put into NRZI mode */
 397        wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);            
 398     } else {
 399         /* Preset Tx CRC, put into NRZ mode */
 400        wrtscc(lp->cardbase, cmd, R10, CRCPS);    
 401     }
 402     
 403     /* Tx/Rx parameters */
 404     if (lp->speed)              /* Use internal clocking */
 405     {
 406        /* Tx Clk from BRG. Rx Clk form DPLL, TRxC pin outputs DPLL */
 407        wrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
 408 
 409     } else {                    /* Use external clocking */
 410            /* Tx Clk from TRxCL. Rx Clk from RTxCL, TRxC pin if input */
 411            wrtscc(lp->cardbase, cmd, R11, TCTRxCP | RCRTxCP | TRxCBR);
 412            wrtscc(lp->cardbase,cmd, R14, 0);    /* wiz1 */
 413     }
 414        
 415     /* Null out SDLC start address */
 416     wrtscc(lp->cardbase, cmd, R6, 0);
 417 
 418     /* SDLC flag */
 419     wrtscc(lp->cardbase, cmd, R7, FLAG);
 420 
 421     /* Setup Tx but don't enable it */
 422     wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
 423 
 424     /* Setup Rx */
 425     wrtscc(lp->cardbase, cmd, R3, AUTO_ENAB | Rx8);
 426 
 427     /* Setup the BRG, turn it off first */
 428     wrtscc(lp->cardbase, cmd, R14, BRSRC);
 429 
 430     /* set the 32x time constant for the BRG in Rx mode */
 431         if (lp->speed)
 432         {
 433                 br = lp->speed;
 434                 tc = ((lp->xtal / 32) / (br * 2)) - 2;
 435             wrtscc(lp->cardbase, cmd, R12, tc & 0xff);          /* lower byte */
 436                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xff);       /* upper byte */                        
 437         }
 438 
 439         /* Turn transmitter off, to setup stuff */
 440         pt_rts(lp, OFF);
 441         
 442         /* External clocking */
 443         if (lp->speed)
 444         {
 445                 /* DPLL frm BRG, BRG src PCLK */
 446                 wrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
 447                 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH); /* SEARCH mode, keep BRG src */
 448             wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);    /* Enable the BRG */
 449 
 450             /* Turn off external clock port */
 451         if (lp->base & CHANA)
 452             outb_p( (pt_sercfg &= ~PT_EXTCLKA), (lp->cardbase + SERIAL_CFG) );
 453         else
 454             outb_p( (pt_sercfg &= ~PT_EXTCLKB), (lp->cardbase + SERIAL_CFG) );              
 455     } else {
 456                 /* DPLL frm rtxc,BRG src PCLK */
 457 /*              wrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);*/
 458         /* Turn on external clock port */
 459         if (lp->base & CHANA)
 460             outb_p( (pt_sercfg |= PT_EXTCLKA), (lp->cardbase + SERIAL_CFG) );
 461         else
 462             outb_p( (pt_sercfg |= PT_EXTCLKB), (lp->cardbase + SERIAL_CFG) );     
 463     }
 464 
 465     if (!lp->dmachan)   
 466                 wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
 467 
 468     wrtscc(lp->cardbase, cmd, R15, BRKIE);      /* ABORT int */
 469         
 470         /* Turn on the DTR to tell modem we're alive */
 471         if (lp->base & CHANA)
 472             outb_p( (pt_sercfg |= PT_DTRA_ON), (lp->cardbase + SERIAL_CFG) );
 473         else
 474         outb_p( (pt_sercfg |= PT_DTRB_ON), (lp->cardbase + SERIAL_CFG) );
 475 
 476     /* Now, turn on the receiver and hunt for a flag */
 477     wrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | AUTO_ENAB | Rx8 );
 478         
 479         restore_flags(flags);
 480 
 481 } /* scc_init() */
 482 
 483 /* Resets the given channel and whole SCC if both channels off */
 484 static void chipset_init(struct device *dev)
     /*  */
 485 {
 486 
 487         struct pt_local *lp = (struct pt_local*) dev->priv;
 488 #ifdef PT_DEBUG
 489         printk("PTd chipset_init(): pt0a tstate = %d.\n", ((struct pt_local*)pt0a.priv)->tstate);
 490         printk("PTd chipset_init(): pt0b tstate = %d.\n", ((struct pt_local*)pt0b.priv)->tstate);       
 491 #endif
 492         /* Reset SCC if both channels are to be canned */
 493         if ( ((lp->base & CHANA) && !(pt_sercfg & PT_DTRB_ON)) ||
 494                         (!(lp->base & CHANA) && !(pt_sercfg & PT_DTRA_ON)) ) 
 495         {
 496                 wrtscc(lp->cardbase, lp->base + CTL, R9, FHWRES);
 497                 /* Reset int and dma registers */
 498                 outb_p((pt_sercfg = 0), lp->cardbase + SERIAL_CFG);
 499                 outb_p((pt_dmacfg = 0), lp->cardbase + DMA_CFG);
 500 #ifdef PT_DEBUG
 501                 printk("PTd chipset_init() Resetting SCC, called by ch (%d).\n", lp->base & CHANA);
 502 #endif                          
 503         }
 504         /* Reset individual channel */
 505         if (lp->base & CHANA) {
 506                 wrtscc(lp->cardbase, lp->base + CTL, R9, MIE | DLC | NV | CHRA);
 507                 outb_p( (pt_sercfg &= ~PT_DTRA_ON), lp->cardbase + SERIAL_CFG);
 508         } else {
 509                 wrtscc(lp->cardbase, lp->base + CTL, R9, MIE | DLC | NV | CHRB);
 510                         outb_p( (pt_sercfg &= ~PT_DTRB_ON), lp->cardbase + SERIAL_CFG);                  
 511         }       
 512 } /* chipset_init() */  
 513         
 514         
 515 
 516 int pt_init(void)
     /*  */
 517 {
 518     int *port;
 519     int ioaddr = 0;
 520     int card_type = 0;
 521     int ports[] =
 522     { 0x230, 0x240, 0x250, 0x260, 0x270, 0x280, 0x290, 0x2a0,
 523       0x2b0, 0x300, 0x330, 0x3f0,  0};
 524 
 525     printk(version);
 526 
 527     for (port = &ports[0]; *port && !card_type; port++) {
 528         ioaddr = *port;
 529 
 530         if (check_region(ioaddr, PT_TOTAL_SIZE) == 0) {
 531             printk("PT: Probing for card at address %#3x\n", ioaddr);
 532             card_type = hw_probe(ioaddr);
 533         }
 534     }
 535     if (card_type) {
 536         printk("PT: Found a PT at address %#3x\n",ioaddr);
 537     } else {
 538         printk("PT: ERROR: No card found.\n");
 539         return -EIO;
 540     }
 541 
 542     /*
 543      * Link a couple of device structres into the chain
 544      *
 545      * For the A port
 546      * Allocate space for 4 buffers even though we only need 3,
 547      * because one of them may cross a DMA page boundary and
 548      * be rejected by get_dma_buffer().
 549      */
 550     register_netdev(&pt0a);
 551 
 552     pt0a.priv= kmalloc(sizeof(struct pt_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4, GFP_KERNEL | GFP_DMA);
 553 
 554     pt0a.dma = 0;       /* wizzer - no dma yet */
 555     pt0a.base_addr = ioaddr + CHANA;
 556     pt0a.irq = 0;
 557 
 558     /* And B port */
 559     register_netdev(&pt0b);
 560 
 561     pt0b.priv= kmalloc(sizeof(struct pt_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4, GFP_KERNEL | GFP_DMA);
 562 
 563     pt0b.base_addr = ioaddr + CHANB;
 564     pt0b.irq = 0;
 565 
 566     /* Now initialise them */
 567     pt_probe(&pt0a);
 568     pt_probe(&pt0b);
 569 
 570     pt0b.irq = pt0a.irq;        /* IRQ is shared */
 571     
 572     return 0;
 573 } /* pt_init() */
 574 
 575 /*
 576  * Probe for PT card.  Also initialises the timers
 577  */
 578 static int hw_probe(int ioaddr)
     /*  */
 579 {
 580     int time = 1000;            /* Number of milliseconds to test */
 581     int a = 1;
 582     int b = 1;
 583     unsigned long start_time, end_time;
 584     
 585     inb_p(ioaddr + TMR1CLR);
 586     inb_p(ioaddr + TMR2CLR);
 587 
 588     /* Timer counter channel 0, 1mS period */
 589     outb_p(SC0 | LSB_MSB | MODE3, ioaddr + TMRCMD);
 590     outb_p(0x00, ioaddr + TMR0);
 591     outb_p(0x18, ioaddr + TMR0);
 592 
 593     /* Setup timer control word for timer 1 */
 594     outb_p(SC1 | LSB_MSB | MODE0, ioaddr + TMRCMD);
 595     outb_p((time << 1) & 0xff, ioaddr + TMR1);
 596     outb_p((time >> 7) & 0xff, ioaddr + TMR1);
 597     
 598     /* wait until counter reg is loaded */
 599     do {
 600         /* Latch count for reading */
 601         outb_p(SC1, ioaddr + TMRCMD);
 602         a = inb_p(ioaddr + TMR1);
 603         b = inb_p(ioaddr + TMR1);
 604     } while (b == 0);
 605     start_time = jiffies;
 606     while(b != 0)
 607     {
 608         /* Latch count for reading */
 609         outb_p(SC1, ioaddr + TMRCMD);
 610         a = inb_p(ioaddr + TMR1);
 611         b = inb_p(ioaddr + TMR1);
 612         end_time = jiffies;
 613         /* Don't wait forever - there may be no card here */
 614         if ((end_time - start_time) > 200)
 615         {
 616                 inb_p(ioaddr + TMR1CLR);
 617             return 0;
 618         }
 619     }
 620     
 621     /* Now fix the timers up for general operation */
 622     
 623     /* Clear the timers */
 624     inb_p(ioaddr + TMR1CLR);
 625     inb_p(ioaddr + TMR2CLR);
 626     
 627     outb_p(SC1 | LSB_MSB | MODE0, ioaddr + TMRCMD);
 628     inb_p(ioaddr + TMR1CLR);
 629     
 630     outb_p(SC2 | LSB_MSB | MODE0, ioaddr + TMRCMD);
 631     /* Should this be tmr1 or tmr2? wiz3*/
 632     inb_p(ioaddr + TMR1CLR);
 633     
 634     return 1;
 635 } /* hw_probe() */
 636 
 637 
 638 static void pt_rts(struct pt_local *lp, int x)
     /*  */
 639 {
 640         int tc;
 641         long br;
 642         int cmd = lp->base + CTL;
 643 #ifdef PT_DEBUG
 644         printk("PTd pt_rts(): Transmitter status will be %d (%d).\n", x, lp->base & CHANA);
 645 #endif                  
 646         if (x == ON) {
 647             /* Ex ints off to avoid int */
 648             wrtscc(lp->cardbase, cmd, R15, 0);
 649             wrtscc(lp->cardbase, cmd, R3, AUTO_ENAB | Rx8);     /* Rx off */
 650             lp->rstate = IDLE;
 651             
 652             if(lp->dmachan)
 653             {
 654                 /* Setup for Tx DMA */
 655                 wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
 656             } else {
 657                 /* No interrupts */
 658                 wrtscc(lp->cardbase, cmd, R1, 0);
 659             }
 660         
 661             if (!lp->clockmode)
 662             {
 663                 if (lp->speed)
 664                 {
 665                     br = lp->speed;
 666                     tc = (lp->xtal / (br * 2)) - 2;
 667                     wrtscc(lp->cardbase, cmd, R12, tc & 0xff);
 668                     wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xff);
 669                 }
 670             }
 671             /* Turn on Tx by raising RTS */
 672             wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
 673             /* Transmitter on now */
 674         } else {                /* turning off Tx */
 675             lp->tstate = IDLE;
 676             
 677             /* Turn off Tx by dropping RTS */
 678             wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
 679             if (!lp->clockmode)
 680             {
 681                 if (lp->speed)          /* internally clocked */
 682                 {
 683                     /* Repogram BRG from 32x clock for Rx DPLL */
 684                     /* BRG off, keep PClk source */
 685                     wrtscc(lp->cardbase, cmd, R14, BRSRC);
 686                     br = lp->speed;
 687                     tc = ((lp->xtal / 32) / (br * 2)) - 2;
 688                     wrtscc(lp->cardbase, cmd, R12, tc & 0xff);
 689                     wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xff);
 690                     
 691                     /* SEARCH mode, BRG source */
 692                     wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
 693                     /* Enalbe the BRG */
 694                     wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
 695                 }
 696             }
 697             /* Flush Rx fifo */
 698             /* Turn Rx off */
 699             wrtscc(lp->cardbase, cmd, R3, AUTO_ENAB | Rx8);
 700             
 701             /* Reset error latch */
 702             wrtscc(lp->cardbase, cmd, R0, ERR_RES);
 703             
 704             /* get status byte from R1 */
 705             (void) rdscc(lp->cardbase, cmd, R1);
 706             
 707             /* Read and dump data in queue */
 708             (void) rdscc(lp->cardbase, cmd, R8);
 709             (void) rdscc(lp->cardbase, cmd, R8);
 710             (void) rdscc(lp->cardbase, cmd, R8);
 711             
 712             /* Now, turn on Rx and hunt for a flag */
 713               wrtscc(lp->cardbase, cmd, R3, RxENABLE | AUTO_ENAB | Rx8 );
 714               
 715             lp->rstate = ACTIVE;
 716             
 717             if (lp->dmachan)
 718             {
 719                 setup_rx_dma(lp);
 720             } else {
 721                 /* Reset buffer pointers */
 722                 lp->rcp = lp->rcvbuf->data;
 723                 lp->rcvbuf->cnt = 0;
 724                 /* Allow aborts to interrupt us */
 725                 wrtscc(lp->cardbase, cmd, R1, INT_ALL_Rx | EXT_INT_ENAB);
 726 
 727         }
 728         wrtscc(lp->cardbase, cmd, R15, BRKIE );
 729     }
 730 } /* pt_rts() */        
 731                 
 732                                 
 733 static int valid_dma_page(unsigned long addr, unsigned long dev_bufsize)
     /*  */
 734 {
 735     if (((addr & 0xffff) + dev_bufsize) <= 0x10000)
 736         return 1;
 737     else
 738         return 0;
 739 }
 740 
 741 static int pt_set_mac_address(struct device *dev, struct sockaddr *sa)
     /*  */
 742 {
 743         memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);              /* addr is an AX.25 shifted ASCII */
 744         return 0;               /* mac address */
 745 }
 746         
 747 
 748 /* Allocate a buffer which does not cross a DMA page boundary */
 749 static char * get_dma_buffer(unsigned long *mem_ptr)
     /*  */
 750 {
 751     char *ret;
 752 
 753     ret = (char *) *mem_ptr;
 754 
 755     if (!valid_dma_page(*mem_ptr, DMA_BUFF_SIZE + sizeof(struct mbuf))) {
 756         *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
 757         ret = (char *) *mem_ptr;
 758     }
 759     *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
 760     return (ret);
 761 } /* get_dma_buffer() */
 762 
 763 
 764 /*
 765  * Sets up all the structures for the PT device
 766  */
 767 static int pt_probe(struct device *dev)
     /*  */
 768 {
 769     short ioaddr;
 770     struct pt_local *lp;
 771     int i;
 772     unsigned long flags;
 773     unsigned long mem_ptr;
 774 
 775     ioaddr = dev->base_addr;
 776 
 777     /*
 778      * Initialise the device structure.
 779      * Must be done before chipset_init()
 780      * Make sure data structures used by  the PT are aligned
 781      */
 782     dev->priv = (void *) (((int) dev->priv + 7) & ~7);
 783     lp = (struct pt_local*) dev->priv;
 784 
 785     memset(dev->priv, 0, sizeof(struct pt_local));
 786 
 787     /* Allocate some buffers which do not cross DMA boundaries */
 788     mem_ptr = (unsigned long) dev->priv + sizeof(struct pt_local);
 789     lp->txdmabuf = get_dma_buffer(&mem_ptr);
 790     lp->rxdmabuf1 = (struct mbuf *) get_dma_buffer(&mem_ptr);
 791     lp->rxdmabuf2 = (struct mbuf *) get_dma_buffer(&mem_ptr);
 792 
 793     /* Initialise the Rx buffer */
 794     lp->rcvbuf = lp->rxdmabuf1;
 795     lp->rcp = lp->rcvbuf->data;
 796     lp->rcvbuf->cnt = 0;
 797 
 798     /* Initialise the transmit queue head structure */
 799     skb_queue_head_init(&lp->sndq);
 800 
 801     lp->base = dev->base_addr;
 802     lp->cardbase = dev->base_addr & 0x3f0;
 803         
 804     /* These need to be initialsed before scc_init() is called.
 805      */
 806     lp->xtal = XTAL;
 807     
 808     if (dev->base_addr & CHANA) {
 809         lp->speed = DEF_A_SPEED;
 810         lp->txdelay = DEF_A_TXDELAY;
 811         lp->persist = DEF_A_PERSIST;
 812         lp->slotime = DEF_A_SLOTIME;
 813         lp->squeldelay = DEF_A_SQUELDELAY;
 814         lp->clockmode = DEF_A_CLOCKMODE;
 815         lp->nrzi = DEF_A_NRZI;
 816     } else {
 817         lp->speed = DEF_B_SPEED;
 818         lp->txdelay = DEF_B_TXDELAY;
 819         lp->persist = DEF_B_PERSIST;
 820         lp->slotime = DEF_B_SLOTIME;
 821         lp->squeldelay = DEF_B_SQUELDELAY;
 822         lp->clockmode = DEF_B_CLOCKMODE;
 823         lp->nrzi = DEF_B_NRZI;
 824     }
 825     lp->bufsiz = DMA_BUFF_SIZE;
 826     lp->tstate = IDLE;
 827 
 828     chipset_init(dev);
 829 
 830     if (dev->base_addr & CHANA) {
 831         /* Note that a single IRQ services 2 devices (A and B channels)
 832         */
 833 
 834         /*
 835          * We disable the dma for a while, we have to get ints working
 836          * properly first!!
 837          */
 838         lp->dmachan = 0;
 839         
 840         if (dev->irq < 2) {
 841             autoirq_setup(0);
 842             
 843             /* Turn on PT interrupts */
 844             save_flags(flags);
 845             cli();
 846             outb_p( pt_sercfg |= PT_EI, lp->cardbase + INT_CFG);
 847             restore_flags(flags);
 848 
 849             /* Set a timer interrupt */
 850             tdelay(lp, 1);
 851             dev->irq = autoirq_report(20);
 852 
 853             /* Turn off PT interrupts */
 854             save_flags(flags);
 855             cli();
 856             outb_p( (pt_sercfg  &= ~ PT_EI), lp->cardbase + INT_CFG);            
 857             restore_flags(flags);
 858 
 859             if (!dev->irq) {
 860                 printk("PT: ERROR: Failed to detect IRQ line, assuming IRQ7.\n");
 861             }
 862         }
 863 
 864         printk("PT: Autodetected IRQ %d, assuming DMA %d\n", dev->irq, dev->dma);
 865 
 866         /* This board has jumpered interrupts. Snarf the interrupt vector
 867          * now.  There is no point in waiting since no other device can use
 868          * the interrupt, and this marks the 'irqaction' as busy.
 869          */
 870         {
 871             int irqval = request_irq(dev->irq, &pt_interrupt,0, "pt", NULL);
 872             if (irqval) {
 873                 printk("PT: ERROR: Unable to get IRQ %d (irqval = %d).\n",
 874                     dev->irq, irqval);
 875                 return EAGAIN;
 876             }
 877         }
 878 
 879         /* Grab the region */
 880         request_region(ioaddr & 0x3f0, PT_TOTAL_SIZE, "pt" );
 881     } /* A port */
 882     dev->open = pt_open;
 883     dev->stop = pt_close;
 884     dev->do_ioctl = pt_ioctl;
 885     dev->hard_start_xmit = pt_send_packet;
 886     dev->get_stats = pt_get_stats;
 887 
 888     /* Fill in the fields of the device structure */
 889     for (i=0; i < DEV_NUMBUFFS; i++)
 890         skb_queue_head_init(&dev->buffs[i]);
 891 
 892     dev->hard_header = pt_header;
 893     dev->rebuild_header = pt_rebuild_header;
 894     dev->set_mac_address = pt_set_mac_address;
 895 
 896     dev->type = ARPHRD_AX25;            /* AF_AX25 device */
 897     dev->hard_header_len = 73;      /* We do digipeaters now */
 898     dev->mtu = 1500;                /* eth_mtu is default */
 899     dev->addr_len = 7;               /* sizeof an ax.25 address */
 900     memcpy(dev->broadcast, ax25_bcast, 7);
 901     memcpy(dev->dev_addr, ax25_test, 7);
 902 
 903     /* New style flags */
 904     dev->flags = 0;
 905     dev->family = AF_INET;
 906     dev->pa_addr = 0;
 907     dev->pa_brdaddr = 0;
 908     dev->pa_mask = 0;
 909     dev->pa_alen = sizeof(unsigned long);
 910 
 911     return 0;
 912 } /* pt_probe() */
 913 
 914 
 915 /* Open/initialise the board.  This is called (in the current kernel)
 916  * sometime after booting when the 'ifconfig' program is run.
 917  *
 918  * This routine should set everything up anew at each open, even
 919  * registers that 'should' only be set once at bott, so that there is
 920  * a non-reboot way to recover if something goes wrong.
 921  * derived from last half of tsync_attach()
 922  */
 923 static int pt_open(struct device *dev)
     /*  */
 924 {
 925     unsigned long flags;
 926     struct pt_local *lp = dev->priv;
 927     static first_time = 1;
 928     
 929     if (dev->base_addr & CHANA)
 930     {
 931         if (first_time)
 932         {
 933             if (request_dma(dev->dma, "pt"))
 934             {
 935                 free_irq(dev->irq, NULL);
 936                 return -EAGAIN;
 937             }
 938         }
 939         irq2dev_map[dev->irq] = dev;
 940  
 941          /* Reset hardware */   
 942          chipset_init(dev);
 943      }
 944      lp->tstate = IDLE;
 945     
 946      if (dev->base_addr & CHANA)
 947      {
 948          scc_init(dev);
 949          scc_init(dev->next);
 950      }
 951      /* Save a copy of register RR0 for comparing with later on */
 952      /* We always put 0 in zero count */
 953      lp->saved_RR0 = rdscc(lp->cardbase, lp->base + CTL, R0) & ~ZCOUNT;
 954     
 955     /* master interrupt enable */
 956     save_flags(flags);
 957     cli();
 958     wrtscc(lp->cardbase, lp->base + CTL, R9, MIE | NV);
 959     outb_p( pt_sercfg |= PT_EI, lp->cardbase + INT_CFG);    
 960     restore_flags(flags);
 961 
 962     lp->open_time = jiffies;
 963 
 964     dev->tbusy = 0;
 965     dev->interrupt = 0;
 966     dev->start = 1;
 967     first_time = 0;
 968         
 969     return 0;
 970 } /* pt_open() */
 971 
 972 static int pt_send_packet(struct sk_buff *skb, struct device *dev)
     /*  */
 973 {
 974         struct pt_local *lp = (struct pt_local *) dev->priv;
 975 
 976 #ifdef PT_DEBUG
 977         printk("PTd pt_send_packet(): (%d)\n", lp->base & CHANA);
 978 #endif                  
 979         /* If some higher layer thinks we've missed an tx-done interrupt
 980            we are passed NULL. Caution: dev_tint() handles the cli()/sti()
 981            itself.*/
 982         if (skb == NULL) {
 983                 dev_tint(dev);
 984                 return 0;
 985         }
 986         hardware_send_packet(lp, skb);
 987         dev->trans_start = jiffies;
 988         
 989         return 0;
 990 }
 991                                    
 992            
 993 
 994 /* The inverse routine to pt_open() */
 995 static int pt_close(struct device *dev)
     /*  */
 996 {
 997         unsigned long flags;
 998         struct pt_local *lp = dev->priv;
 999         struct sk_buff *ptr = NULL;
1000         int cmd;
1001 
1002         cmd = lp->base + CTL;
1003                 
1004         save_flags(flags);
1005         cli();
1006         
1007         /* Reset SCC or channel */
1008         chipset_init(dev);      
1009         disable_dma(lp->dmachan);
1010 
1011         lp->open_time = 0;
1012         dev->tbusy = 1;
1013         dev->start = 0;
1014 
1015         /* Free any buffers left in the hardware transmit queue */
1016         while ((ptr = skb_dequeue(&lp->sndq)) != NULL)
1017                 free_p(ptr);
1018                 
1019         restore_flags(flags);
1020         
1021 #ifdef PT_DEBUG
1022         printk("PTd pt_close(): Closing down channel (%d).\n", lp->base & CHANA);       
1023 #endif  
1024         
1025         return 0;
1026 } /* pt_close() */
1027 
1028 
1029 static int pt_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
     /*  */
1030 {
1031     unsigned long flags;
1032     struct pt_req rq;
1033     struct pt_local *lp = (struct pt_local *) dev->priv;
1034 
1035     int ret = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct pt_req));
1036     if (ret)
1037         return ret;
1038 
1039     if (cmd != SIOCDEVPRIVATE)
1040         return -EINVAL;
1041         
1042     memcpy_fromfs(&rq, ifr->ifr_data, sizeof(struct pt_req));
1043 
1044     switch (rq.cmd) {
1045     case SIOCSPIPARAM:
1046 
1047         if (!suser())
1048             return -EPERM;
1049         save_flags(flags);
1050         cli();
1051         lp->txdelay = rq.txdelay;
1052         lp->persist = rq.persist;
1053         lp->slotime = rq.slotime;
1054         lp->squeldelay = rq.squeldelay;
1055         lp->clockmode = rq.clockmode;
1056         lp->speed = rq.speed;
1057         pt_open(&pt0a);
1058         restore_flags(flags);
1059         ret = 0;
1060         break;
1061 
1062     case SIOCSPIDMA:
1063 
1064         if (!suser())
1065             return -EPERM;
1066         ret = 0;
1067         if (dev->base_addr & CHANA) {   /* if A channel */
1068            if (rq.dmachan < 1 || rq.dmachan > 3)
1069                 return -EINVAL;
1070            save_flags(flags);
1071            cli();
1072            pt_close(dev);
1073            free_dma(lp->dmachan);
1074            dev->dma = lp->dmachan = rq.dmachan;
1075            if (request_dma(lp->dmachan,"pt")) 
1076                 ret = -EAGAIN;
1077            pt_open(dev);
1078            restore_flags(flags);
1079         }
1080         break;
1081 
1082     case SIOCSPIIRQ:
1083         ret = -EINVAL;      /* add this later */
1084         break;
1085 
1086     case SIOCGPIPARAM:
1087     case SIOCGPIDMA:
1088     case SIOCGPIIRQ:
1089 
1090         rq.speed = lp->speed;
1091         rq.txdelay = lp->txdelay;
1092         rq.persist = lp->persist;
1093         rq.slotime = lp->slotime;
1094         rq.squeldelay = lp->squeldelay;
1095         rq.clockmode = lp->clockmode;
1096         rq.dmachan = lp->dmachan;
1097         rq.irq = dev->irq;
1098         memcpy_tofs(ifr->ifr_data, &rq, sizeof(struct pt_req));
1099         ret = 0;
1100         break;
1101 
1102     default:
1103         ret = -EINVAL;
1104     }
1105     return ret;
1106 }
1107 
1108 /* Get the current statistics.  This may be called with the card open or
1109    closed. */
1110 static struct netstats *
1111  pt_get_stats(struct device *dev)
     /*  */
1112 {
1113     struct pt_local *lp = (struct pt_local *) dev->priv;
1114 
1115     return &lp->stats;
1116 }
1117 
1118 
1119 /*
1120  * Local variables:
1121  *  compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1122  *  version-control: t
1123  *  kept-new-versions: 5
1124  *  tab-width: 4
1125  * End:
1126  */
1127 
1128 
1129 static void tdelay(struct pt_local *lp, int time)
     /*  */
1130 {
1131         /* For some reason, we turn off the Tx interrupts here! */
1132         if (!lp->dmachan)
1133                 wrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
1134         
1135     if (lp->base & CHANA) {
1136         outb_p(time & 0xff, lp->cardbase + TMR1);
1137         outb_p((time >> 8)&0xff, lp->cardbase + TMR1);
1138     } else {
1139         outb_p(time & 0xff, lp->cardbase + TMR2);
1140         outb_p((time >> 8)&0xff, lp->cardbase + TMR2);
1141     }
1142 } /* tdelay */
1143 
1144 
1145 static void pt_txisr(struct pt_local *lp)
     /*  */
1146 {
1147         unsigned long flags;
1148         int cmd;
1149         unsigned char c;
1150         
1151         save_flags(flags);
1152         cli();
1153         cmd = lp->base + CTL;
1154 
1155 #ifdef PT_DEBUG
1156         printk("PTd pt_txisr(): tstate = %d (%d).\n", lp->tstate, lp->base & CHANA);
1157 #endif  
1158         
1159         switch (lp->tstate) 
1160         {
1161         case CRCOUT:
1162             lp->tstate = FLAGOUT;
1163             tdelay(lp, lp->squeldelay);
1164             restore_flags(flags);
1165             return;
1166             
1167         case IDLE:
1168             /* Transmitter idle. Find a frame for transmission */
1169             if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL)
1170             {
1171                 /* Nothing to send - return to receive mode
1172                  * Tx off now - flag should have gone
1173                  */
1174                 pt_rts(lp, OFF);
1175                 
1176                 restore_flags(flags);
1177                 return;
1178             }
1179             if (!lp->dmachan)
1180             {
1181                     lp->txptr = lp->sndbuf->data;
1182                     lp->txptr++;                /* Ignore KISS control byte */
1183                     lp->txcnt = (int) lp->sndbuf->len - 1;
1184                 }
1185             /* If a buffer to send, drop though here */
1186         
1187         case DEFER:
1188             /* Check DCD - debounce it */
1189             /* See Intel Microcommunications Handbook p2-308 */
1190             wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
1191             wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
1192             if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0)
1193             {
1194                 lp->tstate = DEFER;
1195                 tdelay(lp, 100);
1196                 /* DEFER until DCD transistion or timeout */
1197                 wrtscc(lp->cardbase, cmd, R15, DCDIE);
1198                 restore_flags(flags);
1199                 return;
1200             }
1201             if (random() > lp->persist)
1202             {
1203                 lp->tstate = DEFER;
1204                 tdelay(lp, lp->slotime);
1205                 restore_flags(flags);
1206                 return;
1207             }
1208             pt_rts(lp, ON);             /* Tx on */
1209             if (lp->dmachan)
1210                 wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
1211             lp->tstate = ST_TXDELAY;
1212             tdelay(lp, lp->txdelay);
1213             restore_flags(flags);
1214             return;
1215         
1216         case ACTIVE:
1217             /* Here we are actively sending a frame */
1218             if (lp->txcnt--)
1219             {
1220                 /* XLZ - checkout Gracilis PT code to see if the while 
1221                  * loop is better or not.
1222                  */
1223                 c = *lp->txptr++;
1224                 /* next char is gone */
1225                 wrtscc(lp->cardbase, cmd, R8, c);
1226                 /* stuffing a char satisfies interrupt condition */
1227             } else {
1228                 /* No more to send */
1229                 free_p(lp->sndbuf);
1230                 lp->sndbuf = NULL;
1231                 if ((rdscc(lp->cardbase, cmd, R0) & TxEOM))
1232                 {
1233                     /* Did we underrum */
1234                     lp->stats.tx_errors++;
1235                     lp->stats.tx_fifo_errors++;
1236                     wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
1237                     lp->tstate = FLAGOUT;
1238                     tdelay(lp, lp->squeldelay);
1239                     restore_flags(flags);
1240                     return;
1241                 }
1242                 lp->tstate = UNDERRUN;
1243                 /* Send flags on underrun */
1244                if (lp->nrzi)
1245                {
1246                    wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
1247                } else {
1248                    wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZ);
1249                }
1250                /* Reset Tx interrupt pending */
1251                wrtscc(lp->cardbase, cmd, R0, RES_Tx_P);
1252            }
1253            restore_flags(flags);
1254            return;
1255         default:
1256                 printk("PT: pt_txisr(): Invlaid tstate (%d) for chan %s.\n", lp->tstate, (cmd & CHANA? "A": "B") );
1257                 pt_rts(lp, OFF);
1258                 lp->tstate = IDLE;
1259                 break;          
1260     }                           /*switch */
1261     restore_flags(flags);
1262 }
1263 
1264 static void pt_rxisr(struct device *dev)
     /*  */
1265 {
1266     struct pt_local *lp = (struct pt_local*) dev->priv;
1267     int cmd = lp->base + CTL;
1268     int bytecount;
1269     unsigned long flags;
1270     char rse;
1271     struct sk_buff *skb;
1272     int sksize, pkt_len;
1273     struct mbuf *cur_buf;
1274     unsigned char *cfix;
1275 
1276     save_flags(flags);
1277     cli();
1278 
1279     /* Get status byte from R1 */
1280     rse = rdscc(lp->cardbase, cmd, R1);
1281     
1282 #ifdef PT_DEBUG
1283     printk("PTd pt_rxisr(): R1 = %#3x. (%d)\n", rse, lp->base & CHANA);
1284 #endif        
1285 
1286         if (lp->dmachan && (rse & Rx_OVR))
1287                 lp->rstate = RXERROR;
1288                 
1289     if (rdscc(lp->cardbase, cmd, R0) & Rx_CH_AV && !lp->dmachan) 
1290     {
1291         /* There is a char to be stored
1292          * Read special condition bits before reading the data char
1293          */
1294         if (rse & Rx_OVR)
1295         {
1296              /* Rx overrun - toss buffer */
1297              /* wind back the pointers */
1298              lp->rcp = lp->rcvbuf->data;
1299              lp->rcvbuf->cnt = 0;
1300              lp->rstate = RXERROR;
1301              lp->stats.rx_errors++;
1302              lp->stats.rx_fifo_errors++;
1303          } else if (lp->rcvbuf->cnt >= lp->bufsiz)
1304              {
1305                  /* Too large packet
1306                   * wind back Rx buffer pointers
1307                   */
1308                  lp->rcp = lp->rcvbuf->data;
1309                  lp->rcvbuf->cnt = 0;
1310                  lp->rstate = TOOBIG;
1311              }
1312          /* ok, we can store the Rx char if no errors */
1313          if (lp->rstate == ACTIVE)
1314          {
1315              *lp->rcp++ = rdscc(lp->cardbase, cmd, R8);
1316              lp->rcvbuf->cnt++;
1317          } else {
1318              /* we got an error, dump the FIFO */
1319              (void) rdscc(lp->cardbase, cmd, R8);
1320              (void) rdscc(lp->cardbase, cmd, R8);
1321              (void) rdscc(lp->cardbase, cmd, R8);
1322              
1323              /* Reset error latch */
1324              wrtscc(lp->cardbase, cmd, R0, ERR_RES);
1325              lp->rstate = ACTIVE;
1326              
1327              /* Resync the SCC */
1328              wrtscc(lp->cardbase, cmd, R3, RxENABLE | ENT_HM | AUTO_ENAB | Rx8);
1329              
1330          }
1331      }
1332      
1333      if (rse & END_FR)
1334      {
1335 #ifdef PT_DEBUG
1336         printk("PTd pt_rxisr() Got end of a %u byte frame.\n", lp->rcvbuf->cnt);
1337 #endif       
1338                 if (lp->dmachan)
1339                 {
1340                         clear_dma_ff(lp->dmachan);
1341                         bytecount = lp->bufsiz - get_dma_residue(lp->dmachan);
1342                 } else {
1343                         bytecount = lp->rcvbuf->cnt;
1344                 }
1345                         
1346          /* END OF FRAME - Make sure Rx was active */
1347          if (lp->rcvbuf->cnt > 0 || lp->dmachan)
1348          {
1349              if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (bytecount < 10))
1350              {
1351                  if ((bytecount >= 10) && (rse & CRC_ERR))
1352                  {
1353                      lp->stats.rx_crc_errors++;
1354                  }
1355                  if (lp->dmachan)
1356                  {
1357                         if (lp->rstate == RXERROR)
1358                         {
1359                                 lp->stats.rx_errors++;
1360                                 lp->stats.rx_over_errors++;
1361                         }
1362                         lp->rstate = ACTIVE;
1363                         setup_rx_dma(lp);
1364                  } else {
1365                          /* wind back Rx buffer pointers */
1366                      lp->rcp = lp->rcvbuf->data;
1367                          lp->rcvbuf->cnt = 0;
1368 
1369                                         /* Re-sync the SCC */
1370                                         wrtscc(lp->cardbase, cmd, R3, RxENABLE | ENT_HM | AUTO_ENAB | Rx8);                     
1371                          
1372                      }
1373 #ifdef PT_DEBUG
1374         printk("PTd pt_rxisr() %s error.\n", (rse & CRC_ERR)? "CRC" : "state");
1375 #endif                 
1376              } else {
1377                  /* We have a valid frame */
1378                  if (lp->dmachan)
1379                  {
1380                         pkt_len = lp->rcvbuf->cnt = bytecount - 2 +1;
1381                                         /* Get buffer for next frame */
1382                         cur_buf = lp->rcvbuf;
1383                         switchbuffers(lp);
1384                         setup_rx_dma(lp);                       
1385                  } else {
1386                          pkt_len = lp->rcvbuf->cnt -= 2;  /* Toss 2 CRC bytes */
1387                      pkt_len += 1;      /* make room for KISS control byte */
1388                         }         
1389 
1390                  /* Malloc up new buffer */
1391                  sksize = pkt_len;
1392                  skb = dev_alloc_skb(sksize);
1393                  if (skb == NULL)
1394                  {
1395                      printk("PT: %s: Memory squeze, dropping packet.\n", dev->name);
1396                      lp->stats.rx_dropped++;
1397                      restore_flags(flags);
1398                      return;
1399                  }
1400                  skb->dev = dev;
1401                  
1402                  /* KISS kludge = prefix with a 0 byte */
1403                  cfix=skb_put(skb,pkt_len);
1404                  *cfix++=0;
1405                  /* skb->data points to the start of sk_buff area */
1406                  if (lp->dmachan)
1407                         memcpy(cfix, (char*)cur_buf->data, pkt_len - 1);
1408                  else
1409                     memcpy(cfix, lp->rcvbuf->data, pkt_len - 1);
1410                  skb->protocol = ntohs(ETH_P_AX25);
1411                  skb->mac.raw=skb->data;
1412                  IS_SKB(skb);
1413                  netif_rx(skb);
1414                  lp->stats.rx_packets++;
1415                  if (!lp->dmachan)
1416                  {
1417                          /* packet queued - wind back buffer for next frame */
1418                      lp->rcp = lp->rcvbuf->data;
1419                          lp->rcvbuf->cnt = 0;
1420                      }
1421              } /* good frame */
1422          } /* check active Rx */
1423          /* Clear error status */
1424          lp->rstate = ACTIVE;
1425          /* Reset error latch */
1426      } /* end EOF check */
1427      wrtscc(lp->cardbase, cmd, R0, ERR_RES);
1428      restore_flags(flags);
1429 } /* pt_rxisr() */
1430 
1431 /* Read the SCC channel till no more data in receiver */
1432 static void empty_scc(struct pt_local *lp)
     /*  */
1433 {
1434     while( rdscc(lp->cardbase, lp->base + CTL, R0) & Rx_CH_AV) {
1435         /* Get data from Rx buffer and toss it */
1436         (void) inb_p(lp->base + DATA);
1437     }
1438 } /* empty_scc()*/
1439 
1440 /*
1441  * This handles the two timer interrupts.
1442  * This is a real bugger, cause you have to rip it out of the pi's
1443  * external status code.  They use the CTS line or something.
1444  */
1445 static void pt_tmrisr(struct pt_local *lp)
     /*  */
1446 {
1447     unsigned long flags;
1448 
1449 #ifdef PT_DEBUG
1450         printk("PTd pt_tmrisr(): tstate = %d (%d).\n", lp->tstate, lp->base & CHANA);
1451 #endif          
1452         
1453     save_flags(flags);
1454     cli();
1455     
1456     
1457     switch (lp->tstate) 
1458     {
1459     /* Most of this stuff is in pt_exisr() */
1460     case FLAGOUT:
1461     case ST_TXDELAY:
1462     case DEFER:
1463 /*    case ACTIVE:
1464     case UNDERRUN:*/
1465         pt_exisr(lp);
1466         break; 
1467       
1468     default:
1469         if (lp->base & CHANA)
1470             printk("PT: pt_tmrisr(): Invalid tstate %d for Channel A\n", lp->tstate);
1471         else
1472             printk("PT: pt_tmrisr(): Invalid tstate %d for Channel B\n", lp->tstate);
1473         break;          
1474     } /* end switch */
1475     restore_flags(flags);
1476 } /* pt_tmrisr() */
1477 
1478         
1479 /*
1480  * This routine is called by the kernel when there is an interrupt for the
1481  * PT.
1482  */
1483 static void pt_interrupt(int irq, void *dev_id, struct pt_regs *regs)
     /*  */
1484 {
1485     /* It's a tad dodgy here, but we assume pt0a until proven otherwise */
1486     struct device *dev = &pt0a;
1487     struct pt_local *lp = dev->priv;
1488     unsigned char intreg;
1489     unsigned char st;
1490     register int cbase = dev->base_addr & 0x3f0;
1491     unsigned long flags;
1492     
1493     /* Read the PT's interrupt register, this is not the SCC one! */
1494     intreg = inb_p(cbase + INT_REG);
1495     while(( intreg & 0x07) != 0x07) {
1496         /* Read interrupt register pending from Channel A */
1497         while ((st = rdscc(cbase, cbase + CHANA + CTL, R3)) != 0)
1498         {
1499                 /* Read interrupt vector from R2, channel B */
1500 #ifdef PT_DEBUG
1501                 printk("PTd pt_interrupt(): R3 = %#3x", st);
1502 #endif                  
1503 /*              st = rdscc(lp->cardbase, cbase + CHANB + CTL, R2) & 0x0e;*/
1504 #ifdef PT_DEBUG
1505                 printk(" R2 = %#3x.\n", st);
1506 #endif  
1507                         if (st & CHARxIP) {
1508                             /* Channel A Rx */
1509                     lp = (struct pt_local*)pt0a.priv;
1510                     pt_rxisr(&pt0a);
1511                 } else if (st & CHATxIP) {
1512                     /* Channel A Tx */
1513                     lp = (struct pt_local*)pt0a.priv;
1514                     pt_txisr(lp);
1515                 } else if (st & CHAEXT) {
1516                         /* Channel A External Status */
1517                         lp = (struct pt_local*)pt0a.priv;
1518                         pt_exisr(lp);
1519                 } else if (st & CHBRxIP) {
1520                         /* Channel B Rx */
1521                     lp= (struct pt_local*)pt0b.priv;
1522                     pt_rxisr(&pt0b);
1523                 } else if (st & CHBTxIP) {
1524                 /* Channel B Tx */
1525                     lp = (struct pt_local*)pt0b.priv;
1526                     pt_txisr(lp);
1527                         } else if (st & CHBEXT) {
1528                         /* Channel B External Status */
1529                         lp = (struct pt_local*)pt0b.priv;
1530                         pt_exisr(lp);
1531                 }
1532             /* Reset highest interrupt under service */
1533             save_flags(flags);
1534             cli();
1535             wrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
1536             restore_flags(flags);
1537         }  /* end of SCC ints */
1538         
1539         if (!(intreg & PT_TMR1_MSK))
1540         {
1541             /* Clear timer 1 */
1542             inb_p(cbase + TMR1CLR);
1543 
1544             pt_tmrisr( (struct pt_local*)pt0a.priv);
1545         }
1546 
1547         if (!(intreg & PT_TMR2_MSK))
1548         {
1549             /* Clear timer 2 */
1550             inb_p(cbase + TMR2CLR);
1551 
1552             pt_tmrisr( (struct pt_local*)pt0b.priv);
1553         }
1554 
1555         /* Get the next PT interrupt vector */
1556         intreg = inb_p(cbase + INT_REG);
1557     } /* while (intreg) */
1558 } /* pt_interrupt() */
1559 
1560 
1561 static void pt_exisr(struct pt_local *lp)
     /*  */
1562 {
1563     unsigned long flags;
1564     int cmd = lp->base + CTL;
1565     unsigned char st;
1566     char c;
1567     int length;
1568     
1569     save_flags(flags);
1570     cli();
1571     
1572     /* Get external status */
1573     st = rdscc(lp->cardbase, cmd, R0);
1574 
1575 #ifdef PT_DEBUG
1576         printk("PTd exisr(): R0 = %#3x tstate = %d (%d).\n", st, lp->tstate, lp->base & CHANA);
1577 #endif  
1578     /* Reset external status latch */
1579     wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
1580     
1581     if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT) && lp->dmachan)
1582     {
1583         setup_rx_dma(lp);
1584         lp->rstate = ACTIVE;
1585     }
1586 
1587     switch (lp->tstate)
1588     {
1589     case ACTIVE:                /* Unexpected underrun */
1590 #ifdef PT_DEBUG
1591         printk("PTd exisr(): unexpected underrun detected.\n");
1592 #endif      
1593         free_p(lp->sndbuf);
1594         lp->sndbuf = NULL;
1595         if (!lp->dmachan)
1596         {
1597                 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
1598                 lp->stats.tx_errors++;
1599                 lp->stats.tx_fifo_errors++;
1600             }
1601         lp->tstate = FLAGOUT;
1602         tdelay(lp, lp->squeldelay);
1603         restore_flags(flags);
1604         return;
1605     case UNDERRUN:              
1606         lp->tstate = CRCOUT;
1607         restore_flags(flags);
1608         return;
1609     case FLAGOUT:
1610         /* squeldelay has timed out */
1611         /* Find a frame for transmission */
1612         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL)
1613         {
1614             /* Nothing to send - return to Rx mode */
1615             pt_rts(lp, OFF);
1616             lp->tstate = IDLE;
1617             restore_flags(flags);
1618             return;
1619         }
1620         if (!lp->dmachan)
1621         {
1622                 lp->txptr = lp->sndbuf->data;
1623             lp->txptr++;                /* Ignore KISS control byte */
1624                 lp->txcnt = (int) lp->sndbuf->len - 1;
1625             }
1626         /* Fall through if we have a packet */
1627     
1628     case ST_TXDELAY:
1629         if (lp->dmachan)
1630         {
1631                 /* Disable DMA chan */
1632                 disable_dma(lp->dmachan);
1633                 
1634                 /* Set up for TX dma */
1635                 wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
1636                 
1637                 length = lp->sndbuf->len - 1;
1638                 memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
1639                 
1640                 /* Setup DMA controller for Tx */
1641                 setup_tx_dma(lp, length);
1642                 
1643                 enable_dma(lp->dmachan);
1644                 
1645                 /* Reset CRC, Txint pending */
1646                 wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
1647                 
1648                 /* Allow underrun only */
1649                 wrtscc(lp->cardbase, cmd, R15, TxUIE);
1650                 
1651                 /* Enable TX DMA */
1652                 wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
1653                 
1654                 /* Send CRC on underrun */
1655                 wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
1656                 
1657                 lp->tstate = ACTIVE;
1658                 break;
1659         } 
1660         /* Get first char to send */
1661         lp->txcnt--;
1662         c = *lp->txptr++;
1663         /* Reset CRC for next frame */
1664         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);
1665         
1666         /* send abort on underrun */
1667         if (lp->nrzi)   
1668         {
1669             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
1670         } else {
1671             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZ | ABUNDER);
1672         }
1673         /* send first char */
1674         wrtscc(lp->cardbase, cmd, R8, c);
1675         
1676         /* Reset end of message latch */
1677         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
1678         
1679         /* stuff an extra one in */
1680 /*        while ((rdscc(lp->cardbase, cmd, R0) & Tx_BUF_EMP) && lp->txcnt)
1681         {
1682             lp->txcnt--;
1683             c = *lp->txptr++;
1684             wrtscc(lp->cardbase, cmd, R8, c);
1685         }*/
1686         
1687         /* select Tx interrupts to enable */
1688         /* Allow underrun int only */
1689         wrtscc(lp->cardbase, cmd, R15, TxUIE);
1690         
1691         /* Reset external interrupts */
1692         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
1693         
1694         /* Tx and Rx ints enabled */
1695         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
1696         
1697         lp->tstate = ACTIVE;
1698         restore_flags(flags);
1699         return;
1700         
1701         /* slotime has timed out */
1702     case DEFER:
1703         /* Check DCD - debounce it
1704          * see Intel Micrommunications Handbook, p2-308
1705          */
1706         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
1707         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
1708         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0)
1709         {
1710             lp->tstate = DEFER;
1711             tdelay(lp, 100);
1712             /* DEFER until DCD transistion or timeout */
1713             wrtscc(lp->cardbase, cmd, R15, DCDIE);
1714             restore_flags(flags);
1715             return;
1716         }
1717         if (random() > lp->persist)
1718         {
1719             lp->tstate = DEFER;
1720             tdelay(lp, lp->slotime);
1721             restore_flags(flags);
1722             return;
1723         }
1724         if (lp->dmachan)
1725                 wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
1726         pt_rts(lp, ON);                 /* Tx on */
1727         lp->tstate = ST_TXDELAY;
1728         tdelay(lp, lp->txdelay);
1729         restore_flags(flags);
1730         return;
1731  
1732         /* Only for int driven parts */
1733         if (lp->dmachan)
1734         {
1735                 restore_flags(flags);
1736                 return;
1737         }
1738         
1739     } /* end switch */
1740     /*
1741      * Rx mode only
1742      * This triggers when hunt mode is entered, & since an ABORT
1743      * automatically enters hunt mode, we use that to clean up
1744      * any waiting garbage
1745      */
1746     if ((lp->rstate == ACTIVE) && (st & BRK_ABRT) )
1747     {
1748 #ifdef PT_DEBUG
1749         printk("PTd exisr(): abort detected.\n");
1750 #endif        
1751                 /* read and dump all of SCC Rx FIFO */
1752         (void) rdscc(lp->cardbase, cmd, R8);
1753         (void) rdscc(lp->cardbase, cmd, R8);
1754         (void) rdscc(lp->cardbase, cmd, R8);      
1755         
1756         lp->rcp = lp->rcvbuf->data;
1757         lp->rcvbuf->cnt = 0;
1758         
1759                 /* Re-sync the SCC */
1760                 wrtscc(lp->cardbase, cmd, R3, RxENABLE | ENT_HM | AUTO_ENAB | Rx8);                     
1761 
1762     }
1763     
1764     /* Check for DCD transistions */
1765     if ( (st & DCD) != (lp->saved_RR0 & DCD))
1766     {
1767 #ifdef PT_DEBUG    
1768         printk("PTd: pt_exisr(): DCD is now %s.\n", (st & DCD)? "ON" : "OFF" );
1769 #endif
1770                 if (st & DCD)
1771                 {
1772                         /* Check that we don't already have some data */
1773                         if (lp->rcvbuf->cnt > 0)
1774                         {
1775 #ifdef PT_DEBUG
1776                                 printk("PTd pt_exisr() dumping %u bytes from buffer.\n", lp->rcvbuf->cnt);
1777 #endif                                  
1778                                 /* wind back buffers */
1779                                 lp->rcp = lp->rcvbuf->data;
1780                                 lp->rcvbuf->cnt = 0;
1781                         }
1782                 } else {  /* DCD off */
1783                         
1784                         /* read and dump al SCC FIFO */
1785                         (void)rdscc(lp->cardbase, cmd, R8);
1786                         (void)rdscc(lp->cardbase, cmd, R8);
1787                         (void)rdscc(lp->cardbase, cmd, R8);
1788 
1789                         /* wind back buffers */
1790                         lp->rcp = lp->rcvbuf->data;
1791                         lp->rcvbuf->cnt = 0;
1792                         
1793                         /* Re-sync the SCC */
1794                         wrtscc(lp->cardbase, cmd, R3, RxENABLE | ENT_HM | AUTO_ENAB | Rx8);                     
1795                 }               
1796                         
1797     }
1798     /* Update the saved version of register RR) */
1799     lp->saved_RR0 = st &~ ZCOUNT;
1800     restore_flags(flags);
1801 
1802 } /* pt_exisr() */
1803 
1804 /* This function is used to send the KISS params back to the kernel itself,
1805  * just like the TNCs do (I think)
1806  * It's a (bit of a) kludge
1807  */
1808 static void send_kiss(struct device *dev, unsigned char arg, unsigned char val)
     /*  */
1809 {
1810         struct sk_buff *skb;
1811         unsigned char *cfix;
1812 /*      struct pt_local *lp = (struct pt_local*)dev->priv;*/
1813         
1814         
1815         skb = dev_alloc_skb(2);
1816         if (skb == NULL)
1817         {
1818                 printk("PT: send_kiss(): Memory squeeze, dropping KISS reply.\n");
1819                 return;
1820         }
1821         skb->dev = dev;
1822         cfix = skb_put(skb, 2);
1823         cfix[0]=arg;
1824         cfix[1]=val;
1825         skb->protocol=htons(ETH_P_AX25);
1826         skb->mac.raw=skb->data;
1827         IS_SKB(skb);
1828         netif_rx(skb);
1829 }
1830
/* */
root/drivers/net/pt.c

DEFINITIONS
