include/asm-sparc/ross.h

/* */
This source file includes following definitions.
hyper_flush_i_page
hyper_flush_i_seg
hyper_flush_i_region
hyper_flush_i_ctx
hyper_flush_i_user
hyper_flush_whole_icache
get_ross_icr
put_ross_icr
hyper_flush_all_combined
   1 /* $Id: ross.h,v 1.4 1996/01/03 03:53:20 davem Exp $
   2  * ross.h: Ross module specific definitions and defines.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _SPARC_ROSS_H
   8 #define _SPARC_ROSS_H
   9 
  10 #include <asm/asi.h>
  11 
  12 /* Ross made Hypersparcs have a %psr 'impl' field of '0001'.  The 'vers'
  13  * field has '1111'.
  14  */
  15 
  16 /* The MMU control register fields on the HyperSparc.
  17  *
  18  * -----------------------------------------------------------------
  19  * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
  20  * -----------------------------------------------------------------
  21  *  31    24 23-22 21  20  19 18-15 14 13 12 11 10  9   8 7-2  1  0
  22  *
  23  * Phew, lots of fields there ;-)
  24  *
  25  * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
  26  * SE: Snoop Enable, turns on bus snooping for cache activity if one.
  27  * WBE: Write Buffer Enable, one turns it on.
  28  * MID: The ModuleID of the chip for MBus transactions.
  29  * BM: Boot-Mode. One indicates the MMU is in boot mode.
  30  * C: Indicates whether accesses are cachable while the MMU is
  31  *    disabled.
  32  * CS: Cache Size -- 0 = 128k, 1 = 256k
  33  * MR: Memory Reflection, one indicates that the memory bus connected
  34  *     to the MBus supports memory reflection.
  35  * CM: Cache Mode -- 0 = write-through, 1 = copy-back
  36  * CE: Cache Enable -- 0 = no caching, 1 = cache is on
  37  * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
  38  *                 1 = faults from supervisor mode do not generate traps
  39  * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
  40  */
  41 
  42 #define HYPERSPARC_CWENABLE   0x00200000
  43 #define HYPERSPARC_SBENABLE   0x00100000
  44 #define HYPERSPARC_WBENABLE   0x00080000
  45 #define HYPERSPARC_MIDMASK    0x00078000
  46 #define HYPERSPARC_BMODE      0x00004000
  47 #define HYPERSPARC_ACENABLE   0x00002000
  48 #define HYPERSPARC_CSIZE      0x00001000
  49 #define HYPERSPARC_MRFLCT     0x00000800
  50 #define HYPERSPARC_CMODE      0x00000400
  51 #define HYPERSPARC_CENABLE    0x00000100
  52 #define HYPERSPARC_NFAULT     0x00000002
  53 #define HYPERSPARC_MENABLE    0x00000001
  54 
  55 /* Flushes which clear out only the on-chip Ross HyperSparc ICACHE. */
  56 extern inline void hyper_flush_i_page(unsigned int addr)
     /*  */
  57 {
  58         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  59                              "r" (addr), "i" (ASI_M_IFLUSH_PAGE) :
  60                              "memory");
  61         return;
  62 }
  63 
  64 extern inline void hyper_flush_i_seg(unsigned int addr)
     /*  */
  65 {
  66         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  67                              "r" (addr), "i" (ASI_M_IFLUSH_SEG) :
  68                              "memory");
  69         return;
  70 }
  71 
  72 extern inline void hyper_flush_i_region(unsigned int addr)
     /*  */
  73 {
  74         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  75                              "r" (addr), "i" (ASI_M_IFLUSH_REGION) :
  76                              "memory");
  77         return;
  78 }
  79 
  80 extern inline void hyper_flush_i_ctx(unsigned int addr)
     /*  */
  81 {
  82         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  83                              "r" (addr), "i" (ASI_M_IFLUSH_CTX) :
  84                              "memory");
  85         return;
  86 }
  87 
  88 extern inline void hyper_flush_i_user(unsigned int addr)
     /*  */
  89 {
  90         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  91                              "r" (addr), "i" (ASI_M_IFLUSH_USER) :
  92                              "memory");
  93         return;
  94 }
  95 
  96 /* Finally, flush the entire ICACHE. */
  97 extern inline void hyper_flush_whole_icache(void)
     /*  */
  98 {
  99         __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
 100                              "i" (ASI_M_FLUSH_IWHOLE));
 101         return;
 102 }
 103 
 104 
 105 /* The ICCR instruction cache register on the HyperSparc.
 106  *
 107  * -----------------------------------------------
 108  * |                                 | FTD | IDC |
 109  * -----------------------------------------------
 110  *  31                                  1     0
 111  *
 112  * This register is accessed using the V8 'wrasr' and 'rdasr'
 113  * opcodes, since not all assemblers understand them and those
 114  * that do use different semantics I will just hard code the
 115  * instruction with a '.word' statement.
 116  *
 117  * FTD:  If set to one flush instructions executed during an
 118  *       instruction cache hit occurs, the corresponding line
 119  *       for said cache-hit is invalidated.  If FTD is zero,
 120  *       an unimplemented 'flush' trap will occur when any
 121  *       flush is executed by the processor.
 122  *
 123  * ICE:  If set to one, the instruction cache is enabled.  If
 124  *       zero, the cache will not be used for instruction fetches.
 125  *
 126  * All other bits are read as zeros, and writes to them have no
 127  * effect.
 128  */
 129 
 130 extern inline unsigned int get_ross_icr(void)
     /*  */
 131 {
 132         unsigned int icreg;
 133 
 134         __asm__ __volatile__(".word 0xbf402000\n\t" : /* rd %iccr, %g1 */
 135                              "=r" (icreg) : :
 136                              "g1", "memory");
 137 
 138         return icreg;
 139 }
 140 
 141 extern inline void put_ross_icr(unsigned int icreg)
     /*  */
 142 {
 143         __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
 144                              ".word 0xbf802000\n\t" /* wr %g1, 0x0, %iccr */
 145                              "nop\n\t"
 146                              "nop\n\t"
 147                              "nop\n\t" : : 
 148                              "r" (icreg) :
 149                              "g1", "memory");
 150 
 151         return;
 152 }
 153 
 154 /* HyperSparc specific cache flushing. */
 155 
 156 extern int hyper_cache_size;
 157 
 158 extern inline void hyper_flush_all_combined(void)
     /*  */
 159 {
 160         unsigned long addr;
 161 
 162         for(addr = 0; addr < hyper_cache_size; addr += 32)
 163                 __asm__ __volatile__("sta %%g0, [%0] 0xe\n\t" : :
 164                                      "r" (addr));
 165 }
 166 
 167 
 168 
 169 #endif /* !(_SPARC_ROSS_H) */
/* */
root/include/asm-sparc/ross.h

INCLUDED FROM

DEFINITIONS
