This source file includes following definitions.
- readisac_0
- readisac_3
- writeisac_0
- writeisac_3
- readisac_s
- writeisac_s
- readhscx_0
- readhscx_3
- writehscx_0
- writehscx_3
- readhscx_s
- writehscx_s
- waitforCEC_0
- waitforCEC_3
- waitforXFW_0
- waitforXFW_3
- writehscxCMDR_0
- writehscxCMDR_3
- teles_hscxreport
- teles_report
- hscx_sched_event
- hscx_empty_fifo
- hscx_fill_fifo
- hscx_interrupt
- isac_sched_event
- empty_fifo
- fill_fifo
- act_wanted
- ph_command
- isac_new_ph
- teles_interrupt
- act_ivated
- process_new_ph
- process_xmt
- process_rcv
- isac_bh
- hscx_process_xmt
- hscx_process_rcv
- hscx_bh
- restart_ph
- initisac
- checkcard
- modehscx
- teles_addlist
- teles_rmlist
- teles_l2l1
- check_ph_act
- teles_manl1
- teles_l2l1discardq
- setstack_teles
- init_hscxstate
- initcard
- get_irq
- release_irq
- close_hscxstate
- closecard
- teles_shiftcards
- teles_inithardware
- teles_closehardware
- hscx_l2l1
- hscx_l2l1discardq
- open_hscxstate
- hscx_manl1
- setstack_hscx
- teles_reportcard
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13
14 #define __NO_VERSION__
15 #include "teles.h"
16
17 #define INCLUDE_INLINE_FUNCS
18 #include <linux/tqueue.h>
19 #include <linux/interrupt.h>
20
21 #undef DCHAN_VERBOSE
22
23 extern void tei_handler(struct PStack *st, byte pr,
24 struct BufHeader *ibh);
25 extern struct IsdnCard cards[];
26 extern int nrcards;
27
28 #define byteout(addr,val) outb_p(val,addr)
29 #define bytein(addr) inb_p(addr)
30
31 static inline byte
32 readisac_0(byte * cardm, byte offset)
33 {
34 return *(byte *) (cardm + 0x100 + ((offset & 1) ? 0x1ff : 0) + offset);
35 }
36
37 static inline byte
38 readisac_3(int iobase, byte offset)
39 {
40 return (bytein(iobase - 0x420 + offset));
41 }
42
43 #define READISAC(mbase,ibase,ofs) \
44 ((mbase)?readisac_0(mbase,ofs):readisac_3(ibase,ofs))
45
46 static inline void
47 writeisac_0(byte * cardm, byte offset, byte value)
48 {
49 *(byte *) (cardm + 0x100 + ((offset & 1) ? 0x1ff : 0) + offset) = value;
50 }
51
52 static inline void
53 writeisac_3(int iobase, byte offset, byte value)
54 {
55 byteout(iobase - 0x420 + offset, value);
56 }
57
58 #define WRITEISAC(mbase,ibase,ofs,val) \
59 ((mbase)?writeisac_0(mbase,ofs,val):writeisac_3(ibase,ofs,val))
60
61 static inline void
62 readisac_s(int iobase, byte offset, byte * dest, int count)
63 {
64 insb(iobase - 0x420 + offset, dest, count);
65 }
66
67 static inline void
68 writeisac_s(int iobase, byte offset, byte * src, int count)
69 {
70 outsb(iobase - 0x420 + offset, src, count);
71 }
72
73 static inline byte
74 readhscx_0(byte * base, byte hscx, byte offset)
75 {
76 return *(byte *) (base + 0x180 + ((offset & 1) ? 0x1FF : 0) +
77 ((hscx & 1) ? 0x40 : 0) + offset);
78 }
79
80 static inline byte
81 readhscx_3(int iobase, byte hscx, byte offset)
82 {
83 return (bytein(iobase - (hscx ? 0x820 : 0xc20) + offset));
84 }
85
86 #define READHSCX(mbase,ibase,hscx,ofs) \
87 ((mbase)?readhscx_0(mbase,hscx,ofs):readhscx_3(ibase,hscx,ofs))
88
89 static inline void
90 writehscx_0(byte * base, byte hscx, byte offset, byte data)
91 {
92 *(byte *) (base + 0x180 + ((offset & 1) ? 0x1FF : 0) +
93 ((hscx & 1) ? 0x40 : 0) + offset) = data;
94 }
95
96 static inline void
97 writehscx_3(int iobase, byte hscx, byte offset, byte data)
98 {
99 byteout(iobase - (hscx ? 0x820 : 0xc20) + offset, data);
100 }
101
102 static inline void
103 readhscx_s(int iobase, byte hscx, byte offset, byte * dest, int count)
104 {
105 insb(iobase - (hscx ? 0x820 : 0xc20) + offset, dest, count);
106 }
107
108 static inline void
109 writehscx_s(int iobase, byte hscx, byte offset, byte * src, int count)
110 {
111 outsb(iobase - (hscx ? 0x820 : 0xc20) + offset, src, count);
112 }
113
114 #define ISAC_MASK 0x20
115 #define ISAC_ISTA 0x20
116 #define ISAC_STAR 0x21
117 #define ISAC_CMDR 0x21
118 #define ISAC_EXIR 0x24
119
120 #define ISAC_RBCH 0x2a
121
122 #define ISAC_ADF2 0x39
123 #define ISAC_SPCR 0x30
124 #define ISAC_ADF1 0x38
125 #define ISAC_CIX0 0x31
126 #define ISAC_STCR 0x37
127 #define ISAC_MODE 0x22
128 #define ISAC_RSTA 0x27
129 #define ISAC_RBCL 0x25
130 #define ISAC_TIMR 0x23
131 #define ISAC_SQXR 0x3b
132
133 #define HSCX_ISTA 0x20
134 #define HSCX_CCR1 0x2f
135 #define HSCX_CCR2 0x2c
136 #define HSCX_TSAR 0x31
137 #define HSCX_TSAX 0x30
138 #define HSCX_XCCR 0x32
139 #define HSCX_RCCR 0x33
140 #define HSCX_MODE 0x22
141 #define HSCX_CMDR 0x21
142 #define HSCX_EXIR 0x24
143 #define HSCX_XAD1 0x24
144 #define HSCX_XAD2 0x25
145 #define HSCX_RAH2 0x27
146 #define HSCX_RSTA 0x27
147 #define HSCX_TIMR 0x23
148 #define HSCX_STAR 0x21
149 #define HSCX_RBCL 0x25
150 #define HSCX_XBCH 0x2d
151 #define HSCX_VSTR 0x2e
152 #define HSCX_RLCR 0x2e
153 #define HSCX_MASK 0x20
154
155 static inline void
156 waitforCEC_0(byte * base, byte hscx)
157 {
158 long to = 10;
159
160 while ((readhscx_0(base, hscx, HSCX_STAR) & 0x04) && to) {
161 udelay(5);
162 to--;
163 }
164 if (!to)
165 printk(KERN_WARNING "waitforCEC timeout\n");
166 }
167
168 static inline void
169 waitforCEC_3(int iobase, byte hscx)
170 {
171 long to = 10;
172
173 while ((readhscx_3(iobase, hscx, HSCX_STAR) & 0x04) && to) {
174 udelay(5);
175 to--;
176 }
177 if (!to)
178 printk(KERN_WARNING "waitforCEC timeout\n");
179 }
180
181 static inline void
182 waitforXFW_0(byte * base, byte hscx)
183 {
184 long to = 10;
185
186 waitforCEC_0(base, hscx);
187
188 while ((!(readhscx_0(base, hscx, HSCX_STAR) & 0x40)) && to) {
189 udelay(5);
190 to--;
191 }
192 if (!to)
193 printk(KERN_WARNING "waitforXFW timeout\n");
194 }
195
196 static inline void
197 waitforXFW_3(int iobase, byte hscx)
198 {
199 long to = 10;
200
201 waitforCEC_3(iobase, hscx);
202
203 while ((!(readhscx_3(iobase, hscx, HSCX_STAR) & 0x40)) && to) {
204 udelay(5);
205 to--;
206 }
207 if (!to)
208 printk(KERN_WARNING "waitforXFW timeout\n");
209 }
210
211 static inline void
212 writehscxCMDR_0(byte * base, byte hscx, byte data)
213 {
214 long flags;
215
216 save_flags(flags);
217 cli();
218 waitforCEC_0(base, hscx);
219 writehscx_0(base, hscx, HSCX_CMDR, data);
220 restore_flags(flags);
221 }
222
223 static inline void
224 writehscxCMDR_3(int iobase, byte hscx, byte data)
225 {
226 long flags;
227
228 save_flags(flags);
229 cli();
230 waitforCEC_3(iobase, hscx);
231 writehscx_3(iobase, hscx, HSCX_CMDR, data);
232 restore_flags(flags);
233 }
234
235 #define WRITEHSCX_CMDR(mbase,ibase,hscx,data) \
236 ((mbase)?writehscxCMDR_0(mbase,hscx,data):writehscxCMDR_3(ibase,hscx,data))
237
238
239
240
241
242 #define ISAC_RCVBUFREADY 0
243 #define ISAC_XMTBUFREADY 1
244 #define ISAC_PHCHANGE 2
245
246 #define HSCX_RCVBUFREADY 0
247 #define HSCX_XMTBUFREADY 1
248
249 void
250 teles_hscxreport(struct IsdnCardState *sp, int hscx)
251 {
252 printk(KERN_DEBUG "HSCX %d\n", hscx);
253 if (sp->membase) {
254 printk(KERN_DEBUG " ISTA %x\n", readhscx_0(sp->membase,
255 hscx, HSCX_ISTA));
256 printk(KERN_DEBUG " STAR %x\n", readhscx_0(sp->membase,
257 hscx, HSCX_STAR));
258 printk(KERN_DEBUG " EXIR %x\n", readhscx_0(sp->membase,
259 hscx, HSCX_EXIR));
260 } else {
261 printk(KERN_DEBUG " ISTA %x\n", readhscx_3(sp->iobase,
262 hscx, HSCX_ISTA));
263 printk(KERN_DEBUG " STAR %x\n", readhscx_3(sp->iobase,
264 hscx, HSCX_STAR));
265 printk(KERN_DEBUG " EXIR %x\n", readhscx_3(sp->iobase,
266 hscx, HSCX_EXIR));
267 }
268 }
269
270 void
271 teles_report(struct IsdnCardState *sp)
272 {
273 printk(KERN_DEBUG "ISAC\n");
274 if (sp->membase) {
275 printk(KERN_DEBUG " ISTA %x\n", readisac_0(sp->membase,
276 ISAC_ISTA));
277 printk(KERN_DEBUG " STAR %x\n", readisac_0(sp->membase,
278 ISAC_STAR));
279 printk(KERN_DEBUG " EXIR %x\n", readisac_0(sp->membase,
280 ISAC_EXIR));
281 } else {
282 printk(KERN_DEBUG " ISTA %x\n", readisac_3(sp->iobase,
283 ISAC_ISTA));
284 printk(KERN_DEBUG " STAR %x\n", readisac_3(sp->iobase,
285 ISAC_STAR));
286 printk(KERN_DEBUG " EXIR %x\n", readisac_3(sp->iobase,
287 ISAC_EXIR));
288 }
289 teles_hscxreport(sp, 0);
290 teles_hscxreport(sp, 1);
291 }
292
293
294
295
296
297 static void
298 hscx_sched_event(struct HscxState *hsp, int event)
299 {
300 hsp->event |= 1 << event;
301 queue_task_irq_off(&hsp->tqueue, &tq_immediate);
302 mark_bh(IMMEDIATE_BH);
303 }
304
305 static void
306 hscx_empty_fifo(struct HscxState *hsp, int count)
307 {
308 byte *ptr;
309 struct BufHeader *ibh = hsp->rcvibh;
310
311 if (hsp->sp->debug)
312 printk(KERN_DEBUG "hscx_empty_fifo\n");
313
314 if (hsp->rcvptr + count > BUFFER_SIZE(HSCX_RBUF_ORDER,
315 HSCX_RBUF_BPPS)) {
316 printk(KERN_WARNING
317 "hscx_empty_fifo: incoming packet too large\n");
318 WRITEHSCX_CMDR(hsp->membase, hsp->iobase, hsp->hscx, 0x80);
319 return;
320 }
321 ptr = DATAPTR(ibh);
322 ptr += hsp->rcvptr;
323
324 hsp->rcvptr += count;
325 if (hsp->membase) {
326 while (count--)
327 *ptr++ = readhscx_0(hsp->membase, hsp->hscx, 0x0);
328 writehscxCMDR_0(hsp->membase, hsp->hscx, 0x80);
329 } else {
330 readhscx_s(hsp->iobase, hsp->hscx, 0x3e, ptr, count);
331 writehscxCMDR_3(hsp->iobase, hsp->hscx, 0x80);
332 }
333 #ifdef BCHAN_VERBOSE
334 {
335 int i;
336 printk(KERN_DEBUG "hscx_empty_fifo");
337 for (i = 0; i < count; i++)
338 printk(" %2x", ptr[i]);
339 printk("\n");
340 }
341 #endif
342 }
343
344 static void
345 hscx_fill_fifo(struct HscxState *hsp)
346 {
347 struct BufHeader *ibh;
348 int more, count;
349 byte *ptr;
350
351 if (hsp->sp->debug)
352 printk(KERN_DEBUG "hscx_fill_fifo\n");
353
354 ibh = hsp->xmtibh;
355 if (!ibh)
356 return;
357
358 count = ibh->datasize - hsp->sendptr;
359 if (count <= 0)
360 return;
361
362 #if 0
363 if (!hsp->sendptr) {
364 ptr = DATAPTR(ibh);
365 printk(KERN_DEBUG "snd bytes %2x %2x %2x %2x %2x\n", ptr[0], ptr[1], ptr[2],
366 ptr[3], ptr[4]);
367 }
368 #endif
369
370 more = 0;
371 if (count > 32) {
372 more = !0;
373 count = 32;
374 }
375 ptr = DATAPTR(ibh);
376 ptr += hsp->sendptr;
377 hsp->sendptr += count;
378
379 #ifdef BCHAN_VERBOSE
380 {
381 int i;
382 printk(KERN_DEBUG "hscx_fill_fifo ");
383 for (i = 0; i < count; i++)
384 printk(" %2x", ptr[i]);
385 printk("\n");
386 }
387 #endif
388 if (hsp->membase) {
389 waitforXFW_0(hsp->membase, hsp->hscx);
390 while (count--)
391 writehscx_0(hsp->membase, hsp->hscx, 0x0, *ptr++);
392 writehscxCMDR_0(hsp->membase, hsp->hscx, more ? 0x8 : 0xa);
393 } else {
394 waitforXFW_3(hsp->iobase, hsp->hscx);
395 writehscx_s(hsp->iobase, hsp->hscx, 0x3e, ptr, count);
396 writehscxCMDR_3(hsp->iobase, hsp->hscx, more ? 0x8 : 0xa);
397 }
398 }
399
400 static inline void
401 hscx_interrupt(struct IsdnCardState *sp, byte val, byte hscx)
402 {
403 byte r;
404 struct HscxState *hsp = sp->hs + hscx;
405 int count;
406
407 if (!hsp->init)
408 return;
409
410 if (val & 0x80) {
411
412 r = READHSCX(hsp->membase, sp->iobase, hsp->hscx, HSCX_RSTA);
413 if ((r & 0xf0) != 0xa0) {
414 if (!r & 0x80)
415 printk(KERN_WARNING
416 "Teles: HSCX invalid frame\n");
417 if (r & 0x40)
418 printk(KERN_WARNING "Teles: HSCX RDO\n");
419 if (!r & 0x20)
420 printk(KERN_WARNING "Teles: HSCX CRC error\n");
421 if (hsp->rcvibh)
422 BufPoolRelease(hsp->rcvibh);
423 hsp->rcvibh = NULL;
424 WRITEHSCX_CMDR(hsp->membase, hsp->iobase, hsp->hscx,
425 0x80);
426 goto afterRME;
427 }
428 if (!hsp->rcvibh)
429 if (BufPoolGet(&hsp->rcvibh, &hsp->rbufpool,
430 GFP_ATOMIC, (void *) 1, 1)) {
431 printk(KERN_WARNING
432 "HSCX RME out of buffers at %ld\n",
433 jiffies);
434 WRITEHSCX_CMDR(hsp->membase, hsp->iobase,
435 hsp->hscx, 0x80);
436 goto afterRME;
437 } else
438 hsp->rcvptr = 0;
439
440 count = READHSCX(hsp->membase, sp->iobase, hsp->hscx,
441 HSCX_RBCL) & 0x1f;
442 if (count == 0)
443 count = 32;
444 hscx_empty_fifo(hsp, count);
445 hsp->rcvibh->datasize = hsp->rcvptr - 1;
446 BufQueueLink(&hsp->rq, hsp->rcvibh);
447 hsp->rcvibh = NULL;
448 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
449 }
450 afterRME:
451 if (val & 0x40) {
452 if (!hsp->rcvibh)
453 if (BufPoolGet(&hsp->rcvibh, &hsp->rbufpool,
454 GFP_ATOMIC, (void *) 1, 2)) {
455 printk(KERN_WARNING
456 "HSCX RME out of buffers at %ld\n",
457 jiffies);
458 WRITEHSCX_CMDR(hsp->membase, hsp->iobase,
459 hsp->hscx, 0x80);
460 goto afterRPF;
461 } else
462 hsp->rcvptr = 0;
463
464 hscx_empty_fifo(hsp, 32);
465 #ifdef VOICE
466 hsp->rcvibh->datasize = hsp->rcvptr - 1;
467 BufQueueLink(&hsp->rq, hsp->rcvibh);
468 hsp->rcvibh = NULL;
469 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
470 #endif
471 }
472 afterRPF:
473 if (val & 0x10) {
474 if (hsp->xmtibh)
475 if (hsp->xmtibh->datasize > hsp->sendptr) {
476 hscx_fill_fifo(hsp);
477 goto afterXPR;
478 } else {
479 if (hsp->releasebuf)
480 BufPoolRelease(hsp->xmtibh);
481 hsp->xmtibh = NULL;
482 hsp->sendptr = 0;
483 if (hsp->st->l4.l1writewakeup)
484 hsp->st->l4.l1writewakeup(hsp->st);
485 }
486 if (!BufQueueUnlink(&hsp->xmtibh, &hsp->sq)) {
487 hsp->releasebuf = !0;
488 hscx_fill_fifo(hsp);
489 } else
490 hscx_sched_event(hsp, HSCX_XMTBUFREADY);
491 }
492 afterXPR:
493 }
494
495
496
497
498
499 static void
500 isac_sched_event(struct IsdnCardState *sp, int event)
501 {
502 sp->event |= 1 << event;
503 queue_task_irq_off(&sp->tqueue, &tq_immediate);
504 mark_bh(IMMEDIATE_BH);
505 }
506
507 static void
508 empty_fifo(struct IsdnCardState *sp, int count)
509 {
510 byte *ptr;
511 struct BufHeader *ibh = sp->rcvibh;
512
513 if (sp->debug)
514 printk(KERN_DEBUG "empty_fifo\n");
515
516 if (sp->rcvptr >= 3072) {
517 printk(KERN_WARNING "empty_fifo rcvptr %d\n", sp->rcvptr);
518 return;
519 }
520 ptr = DATAPTR(ibh);
521 ptr += sp->rcvptr;
522 sp->rcvptr += count;
523
524 if (sp->membase) {
525 #ifdef DCHAN_VERBOSE
526 printk(KERN_DEBUG "empty_fifo ");
527 while (count--) {
528 *ptr = readisac_0(sp->membase, 0x0);
529 printk("%2x ", *ptr);
530 ptr++;
531 }
532 printk("\n");
533 #else
534 while (count--)
535 *ptr++ = readisac_0(sp->membase, 0x0);
536 #endif
537 writeisac_0(sp->membase, ISAC_CMDR, 0x80);
538 } else {
539 #ifdef DCHAN_VERBOSE
540 int i;
541 printk(KERN_DEBUG "empty_fifo ");
542 readisac_s(sp->iobase, 0x3e, ptr, count);
543 for (i = 0; i < count; i++)
544 printk("%2x ", ptr[i]);
545 printk("\n");
546 #else
547 readisac_s(sp->iobase, 0x3e, ptr, count);
548 #endif
549 writeisac_3(sp->iobase, ISAC_CMDR, 0x80);
550 }
551 }
552
553 static void
554 fill_fifo(struct IsdnCardState *sp)
555 {
556 struct BufHeader *ibh;
557 int count, more;
558 byte *ptr;
559
560 if (sp->debug)
561 printk(KERN_DEBUG "fill_fifo\n");
562
563 ibh = sp->xmtibh;
564 if (!ibh)
565 return;
566
567 count = ibh->datasize - sp->sendptr;
568 if (count <= 0)
569 return;
570 if (count >= 3072)
571 return;
572
573 more = 0;
574 if (count > 32) {
575 more = !0;
576 count = 32;
577 }
578 ptr = DATAPTR(ibh);
579 ptr += sp->sendptr;
580 sp->sendptr += count;
581
582 if (sp->membase) {
583 #ifdef DCHAN_VERBOSE
584 printk(KERN_DEBUG "fill_fifo ");
585 while (count--) {
586 writeisac_0(sp->membase, 0x0, *ptr);
587 printk("%2x ", *ptr);
588 ptr++;
589 }
590 printk("\n");
591 #else
592 while (count--)
593 writeisac_0(sp->membase, 0x0, *ptr++);
594 #endif
595 writeisac_0(sp->membase, ISAC_CMDR, more ? 0x8 : 0xa);
596 } else {
597 #ifdef DCHAN_VERBOSE
598 int i;
599 writeisac_s(sp->iobase, 0x3e, ptr, count);
600 printk(KERN_DEBUG "fill_fifo ");
601 for (i = 0; i < count; i++)
602 printk("%2x ", ptr[i]);
603 printk("\n");
604 #else
605 writeisac_s(sp->iobase, 0x3e, ptr, count);
606 #endif
607 writeisac_3(sp->iobase, ISAC_CMDR, more ? 0x8 : 0xa);
608 }
609 }
610
611 static int
612 act_wanted(struct IsdnCardState *sp)
613 {
614 struct PStack *st;
615
616 st = sp->stlist;
617 while (st)
618 if (st->l1.act_state)
619 return (!0);
620 else
621 st = st->next;
622 return (0);
623 }
624
625 static void
626 ph_command(struct IsdnCardState *sp, unsigned int command)
627 {
628 printk(KERN_DEBUG "ph_command %d\n", command);
629 WRITEISAC(sp->membase, sp->iobase, ISAC_CIX0, (command << 2) | 3);
630 }
631
632 static void
633 isac_new_ph(struct IsdnCardState *sp)
634 {
635 int enq;
636
637 enq = act_wanted(sp);
638
639 switch (sp->ph_state) {
640 case (0):
641 case (6):
642 if (enq)
643 ph_command(sp, 0);
644 else
645 ph_command(sp, 15);
646 break;
647 case (7):
648 if (enq)
649 ph_command(sp, 9);
650 break;
651 case (12):
652 case (13):
653 sp->ph_active = 5;
654 isac_sched_event(sp, ISAC_PHCHANGE);
655 if (!sp->xmtibh)
656 if (!BufQueueUnlink(&sp->xmtibh, &sp->sq))
657 sp->sendptr = 0;
658 if (sp->xmtibh)
659 fill_fifo(sp);
660 break;
661 case (4):
662 case (8):
663 break;
664 default:
665 sp->ph_active = 0;
666 break;
667 }
668 }
669
670 static void
671 teles_interrupt(int intno, void *dev_id, struct pt_regs *regs)
672 {
673 byte val, val2, r;
674 struct IsdnCardState *sp;
675 unsigned int count;
676 struct HscxState *hsp;
677
678 sp = (struct IsdnCardState *) irq2dev_map[intno];
679
680 if (!sp) {
681 printk(KERN_WARNING "Teles: Spurious interrupt!\n");
682 return;
683 }
684 val = READHSCX(sp->membase, sp->iobase, 1, HSCX_ISTA);
685
686 if (val & 0x01) {
687 hsp = sp->hs + 1;
688 printk(KERN_WARNING "HSCX B EXIR %x xmitbh %lx rcvibh %lx\n",
689 READHSCX(sp->membase, sp->iobase, 1, HSCX_EXIR),
690 (long) hsp->xmtibh,
691 (long) hsp->rcvibh);
692 }
693 if (val & 0xf8) {
694 if (sp->debug)
695 printk(KERN_DEBUG "HSCX B interrupt %x\n", val);
696 hscx_interrupt(sp, val, 1);
697 }
698 if (val & 0x02) {
699 printk(KERN_WARNING "HSCX A EXIR %x\n",
700 READHSCX(sp->membase, sp->iobase, 0, HSCX_EXIR));
701 }
702
703
704 if (sp->membase) {
705 if (val & 0x04) {
706 val = readhscx_0(sp->membase, 0, HSCX_ISTA);
707 if (sp->debug)
708 printk(KERN_DEBUG "HSCX A interrupt %x\n",
709 val);
710 hscx_interrupt(sp, val, 0);
711 }
712 } else {
713 val2 = readhscx_3(sp->iobase, 0, HSCX_ISTA);
714 if (sp->debug)
715 printk(KERN_DEBUG "HSCX A ISTA %x\n", val2);
716 if (val & 0x04) {
717 if (sp->debug)
718 printk(KERN_DEBUG "HSCX A interrupt %x\n",
719 val2);
720 hscx_interrupt(sp, val2, 0);
721 }
722 }
723
724
725 val = READISAC(sp->membase, sp->iobase, ISAC_ISTA);
726
727 if (sp->debug)
728 printk(KERN_DEBUG "ISAC interrupt %x\n", val);
729
730 if (val & 0x80) {
731
732 r = READISAC(sp->membase, sp->iobase, ISAC_RSTA);
733 if ((r & 0x70) != 0x20) {
734 if (r & 0x40)
735 printk(KERN_WARNING "Teles: ISAC RDO\n");
736 if (!r & 0x20)
737 printk(KERN_WARNING "Teles: ISAC CRC error\n");
738 if (sp->rcvibh)
739 BufPoolRelease(sp->rcvibh);
740 sp->rcvibh = NULL;
741 WRITEISAC(sp->membase, sp->iobase, ISAC_CMDR, 0x80);
742 goto afterRME;
743 }
744 if (!sp->rcvibh)
745 if (BufPoolGet(&(sp->rcvibh), &(sp->rbufpool),
746 GFP_ATOMIC,
747 (void *) 1, 3)) {
748 printk(KERN_WARNING
749 "ISAC RME out of buffers!\n");
750 WRITEISAC(sp->membase, sp->iobase,
751 ISAC_CMDR, 0x80);
752 goto afterRME;
753 } else
754 sp->rcvptr = 0;
755
756 count = READISAC(sp->membase, sp->iobase, ISAC_RBCL) & 0x1f;
757 if (count == 0)
758 count = 32;
759 empty_fifo(sp, count);
760 sp->rcvibh->datasize = sp->rcvptr;
761 BufQueueLink(&(sp->rq), sp->rcvibh);
762 sp->rcvibh = NULL;
763 isac_sched_event(sp, ISAC_RCVBUFREADY);
764 }
765 afterRME:
766 if (val & 0x40) {
767 if (!sp->rcvibh)
768 if (BufPoolGet(&(sp->rcvibh), &(sp->rbufpool),
769 GFP_ATOMIC,
770 (void *) 1, 4)) {
771 printk(KERN_WARNING
772 "ISAC RME out of buffers!\n");
773 WRITEISAC(sp->membase, sp->iobase,
774 ISAC_CMDR, 0x80);
775 goto afterRPF;
776 } else
777 sp->rcvptr = 0;
778 empty_fifo(sp, 32);
779 }
780 afterRPF:
781 if (val & 0x20) {
782 }
783 if (val & 0x10) {
784 if (sp->xmtibh)
785 if (sp->xmtibh->datasize > sp->sendptr) {
786 fill_fifo(sp);
787 goto afterXPR;
788 } else {
789 if (sp->releasebuf)
790 BufPoolRelease(sp->xmtibh);
791 sp->xmtibh = NULL;
792 sp->sendptr = 0;
793 }
794 if (!BufQueueUnlink(&sp->xmtibh, &sp->sq)) {
795 sp->releasebuf = !0;
796 fill_fifo(sp);
797 } else
798 isac_sched_event(sp, ISAC_XMTBUFREADY);
799 }
800 afterXPR:
801 if (val & 0x04) {
802 sp->ph_state = (READISAC(sp->membase, sp->iobase, ISAC_CIX0)
803 >> 2) & 0xf;
804 printk(KERN_DEBUG "l1state %d\n", sp->ph_state);
805 isac_new_ph(sp);
806 }
807 if (sp->membase) {
808 writeisac_0(sp->membase, ISAC_MASK, 0xFF);
809 writehscx_0(sp->membase, 0, HSCX_MASK, 0xFF);
810 writehscx_0(sp->membase, 1, HSCX_MASK, 0xFF);
811 writeisac_0(sp->membase, ISAC_MASK, 0x0);
812 writehscx_0(sp->membase, 0, HSCX_MASK, 0x0);
813 writehscx_0(sp->membase, 1, HSCX_MASK, 0x0);
814 } else {
815 writeisac_3(sp->iobase, ISAC_MASK, 0xFF);
816 writehscx_3(sp->iobase, 0, HSCX_MASK, 0xFF);
817 writehscx_3(sp->iobase, 1, HSCX_MASK, 0xFF);
818 writeisac_3(sp->iobase, ISAC_MASK, 0x0);
819 writehscx_3(sp->iobase, 0, HSCX_MASK, 0x0);
820 writehscx_3(sp->iobase, 1, HSCX_MASK, 0x0);
821 }
822 }
823
824
825
826
827
828 static void
829 act_ivated(struct IsdnCardState *sp)
830 {
831 struct PStack *st;
832
833 st = sp->stlist;
834 while (st) {
835 if (st->l1.act_state == 1) {
836 st->l1.act_state = 2;
837 st->l1.l1man(st, PH_ACTIVATE, NULL);
838 }
839 st = st->next;
840 }
841 }
842
843 static void
844 process_new_ph(struct IsdnCardState *sp)
845 {
846 if (sp->ph_active == 5)
847 act_ivated(sp);
848 }
849
850 static void
851 process_xmt(struct IsdnCardState *sp)
852 {
853 struct PStack *stptr;
854
855 if (sp->xmtibh)
856 return;
857
858 stptr = sp->stlist;
859 while (stptr != NULL)
860 if (stptr->l1.requestpull) {
861 stptr->l1.requestpull = 0;
862 stptr->l1.l1l2(stptr, PH_PULL_ACK, NULL);
863 break;
864 } else
865 stptr = stptr->next;
866 }
867
868 static void
869 process_rcv(struct IsdnCardState *sp)
870 {
871 struct BufHeader *ibh, *cibh;
872 struct PStack *stptr;
873 byte *ptr;
874 int found, broadc;
875 char tmp[64];
876
877 while (!BufQueueUnlink(&ibh, &sp->rq)) {
878 stptr = sp->stlist;
879 ptr = DATAPTR(ibh);
880 broadc = (ptr[1] >> 1) == 127;
881
882 if (broadc && sp->dlogflag && (!(ptr[0] >> 2)))
883 dlogframe(sp, ptr + 3, ibh->datasize - 3,
884 "Q.931 frame network->user broadcast");
885
886 if (broadc) {
887 while (stptr != NULL) {
888 if ((ptr[0] >> 2) == stptr->l2.sap)
889 if (!BufPoolGet(&cibh, &sp->rbufpool, GFP_ATOMIC,
890 (void *) 1, 5)) {
891 memcpy(DATAPTR(cibh), DATAPTR(ibh), ibh->datasize);
892 cibh->datasize = ibh->datasize;
893 stptr->l1.l1l2(stptr, PH_DATA, cibh);
894 } else
895 printk(KERN_WARNING "isdn broadcast buffer shortage\n");
896 stptr = stptr->next;
897 }
898 BufPoolRelease(ibh);
899 } else {
900 found = 0;
901 while (stptr != NULL)
902 if (((ptr[0] >> 2) == stptr->l2.sap) &&
903 ((ptr[1] >> 1) == stptr->l2.tei)) {
904 stptr->l1.l1l2(stptr, PH_DATA, ibh);
905 found = !0;
906 break;
907 } else
908 stptr = stptr->next;
909 if (!found) {
910
911
912
913
914
915 if ((!(ptr[0] >> 2)) && (!(ptr[2] & 0x01))) {
916 sprintf(tmp, "Q.931 frame network->user with tei %d (not for us)", ptr[1] >> 1);
917 dlogframe(sp, ptr + 4, ibh->datasize - 4, tmp);
918 }
919 BufPoolRelease(ibh);
920 }
921 }
922
923 }
924
925 }
926
927 static void
928 isac_bh(struct IsdnCardState *sp)
929 {
930 if (!sp)
931 return;
932
933 if (clear_bit(ISAC_PHCHANGE, &sp->event))
934 process_new_ph(sp);
935 if (clear_bit(ISAC_RCVBUFREADY, &sp->event))
936 process_rcv(sp);
937 if (clear_bit(ISAC_XMTBUFREADY, &sp->event))
938 process_xmt(sp);
939 }
940
941
942 static void
943 hscx_process_xmt(struct HscxState *hsp)
944 {
945 struct PStack *st = hsp->st;
946
947 if (hsp->xmtibh)
948 return;
949
950 if (st->l1.requestpull) {
951 st->l1.requestpull = 0;
952 st->l1.l1l2(st, PH_PULL_ACK, NULL);
953 }
954 if (!hsp->active)
955 if ((!hsp->xmtibh) && (!hsp->sq.head))
956 modehscx(hsp, 0, 0);
957 }
958
959 static void
960 hscx_process_rcv(struct HscxState *hsp)
961 {
962 struct BufHeader *ibh;
963
964 #ifdef DEBUG_MAGIC
965 if (hsp->magic != 301270) {
966 printk(KERN_DEBUG "hscx_process_rcv magic not 301270\n");
967 return;
968 }
969 #endif
970 while (!BufQueueUnlink(&ibh, &hsp->rq)) {
971 hsp->st->l1.l1l2(hsp->st, PH_DATA, ibh);
972 }
973 }
974
975 static void
976 hscx_bh(struct HscxState *hsp)
977 {
978
979 if (!hsp)
980 return;
981
982 if (clear_bit(HSCX_RCVBUFREADY, &hsp->event))
983 hscx_process_rcv(hsp);
984 if (clear_bit(HSCX_XMTBUFREADY, &hsp->event))
985 hscx_process_xmt(hsp);
986
987 }
988
989
990
991
992
993 static void
994 restart_ph(struct IsdnCardState *sp)
995 {
996 switch (sp->ph_active) {
997 case (0):
998 if (sp->ph_state == 6)
999 ph_command(sp, 0);
1000 else
1001 ph_command(sp, 1);
1002 sp->ph_active = 1;
1003 break;
1004 }
1005 }
1006
1007 static void
1008 initisac(byte * cardmem, int iobase)
1009 {
1010 if (cardmem) {
1011 writeisac_0(cardmem, ISAC_MASK, 0xff);
1012 writeisac_0(cardmem, ISAC_ADF2, 0x0);
1013 writeisac_0(cardmem, ISAC_SPCR, 0xa);
1014 writeisac_0(cardmem, ISAC_ADF1, 0x2);
1015 writeisac_0(cardmem, ISAC_STCR, 0x70);
1016 writeisac_0(cardmem, ISAC_MODE, 0xc9);
1017 writeisac_0(cardmem, ISAC_CMDR, 0x41);
1018 writeisac_0(cardmem, ISAC_CIX0, (1 << 2) | 3);
1019 } else {
1020 writeisac_3(iobase, ISAC_MASK, 0xff);
1021 writeisac_3(iobase, ISAC_ADF2, 0x80);
1022 writeisac_3(iobase, ISAC_SQXR, 0x2f);
1023 writeisac_3(iobase, ISAC_SPCR, 0x00);
1024 writeisac_3(iobase, ISAC_ADF1, 0x02);
1025 writeisac_3(iobase, ISAC_STCR, 0x70);
1026 writeisac_3(iobase, ISAC_MODE, 0xc9);
1027 writeisac_3(iobase, ISAC_TIMR, 0x00);
1028 writeisac_3(iobase, ISAC_ADF1, 0x00);
1029 writeisac_3(iobase, ISAC_CMDR, 0x41);
1030 writeisac_3(iobase, ISAC_CIX0, (1 << 2) | 3);
1031 }
1032 }
1033
1034 static int
1035 checkcard(int cardnr)
1036 {
1037 int timout;
1038 byte cfval, val;
1039 struct IsdnCard *card = cards + cardnr;
1040
1041 if (!card->iobase) {
1042 if (card->membase) {
1043 printk(KERN_NOTICE
1044 "Teles 8 assumed, mem: %lx irq: %d proto: %s\n",
1045 (long) card->membase, card->interrupt,
1046 (card->protocol == ISDN_PTYPE_1TR6) ?
1047 "1TR6" : "EDSS1");
1048 printk(KERN_INFO "HSCX version A: %x B:%x\n",
1049 readhscx_0(card->membase, 0, HSCX_VSTR) & 0xf,
1050 readhscx_0(card->membase, 1, HSCX_VSTR) & 0xf);
1051 }
1052 } else {
1053 switch (card->iobase) {
1054 case 0x180:
1055 case 0x280:
1056 case 0x380:
1057 printk(KERN_INFO "teles: port 0x%x specified, assuming 0x%x\n",
1058 card->iobase, (card->iobase | 0xc00));
1059 card->iobase |= 0xc00;
1060 break;
1061 }
1062 if (check_region(card->iobase, 8)) {
1063 printk(KERN_WARNING
1064 "teles: ports %x-%x already in use\n",
1065 card->iobase,
1066 card->iobase + 8 );
1067 return -1;
1068 }
1069 switch (card->interrupt) {
1070 case 2:
1071 cfval = 0x00;
1072 break;
1073 case 3:
1074 cfval = 0x02;
1075 break;
1076 case 4:
1077 cfval = 0x04;
1078 break;
1079 case 5:
1080 cfval = 0x06;
1081 break;
1082 case 10:
1083 cfval = 0x08;
1084 break;
1085 case 11:
1086 cfval = 0x0A;
1087 break;
1088 case 12:
1089 cfval = 0x0C;
1090 break;
1091 case 15:
1092 cfval = 0x0E;
1093 break;
1094 default:
1095 cfval = 0x00;
1096 break;
1097 }
1098 if (card->membase) {
1099 cfval |= (((unsigned int) card->membase >> 9) & 0xF0);
1100
1101 if (bytein(card->iobase + 0) != 0x51) {
1102 printk(KERN_INFO "XXX Byte at %x is %x\n",
1103 card->iobase + 0,
1104 bytein(card->iobase + 0));
1105 return -2;
1106 }
1107 if (bytein(card->iobase + 1) != 0x93) {
1108 printk(KERN_INFO "XXX Byte at %x is %x\n",
1109 card->iobase + 1,
1110 bytein(card->iobase + 1));
1111 return -2;
1112 }
1113 val = bytein(card->iobase + 2);
1114
1115
1116 if (val != 0x1e && val != 0x1f) {
1117 printk(KERN_INFO "XXX Byte at %x is %x\n",
1118 card->iobase + 2,
1119 bytein(card->iobase + 2));
1120 return -2;
1121 }
1122 }
1123 request_region(card->iobase, 8, "teles");
1124 cli();
1125 timout = jiffies + (HZ / 10) + 1;
1126 byteout(card->iobase + 4, cfval);
1127 sti();
1128 while (jiffies <= timout);
1129
1130 cli();
1131 timout = jiffies + (HZ / 10) + 1;
1132 byteout(card->iobase + 4, cfval | 1);
1133 sti();
1134 while (jiffies <= timout);
1135
1136 if (card->membase)
1137 printk(KERN_NOTICE
1138 "Teles 16.0 found, io: %x mem: %lx irq: %d proto: %s\n",
1139 card->iobase, (long) card->membase,
1140 card->interrupt,
1141 (card->protocol == ISDN_PTYPE_1TR6) ?
1142 "1TR6" : "EDSS1");
1143 else
1144 printk(KERN_NOTICE
1145 "Teles 16.3 found, io: %x irq: %d proto: %s\n",
1146 card->iobase, card->interrupt,
1147 (card->protocol == ISDN_PTYPE_1TR6) ?
1148 "1TR6" : "EDSS1");
1149 printk(KERN_INFO "HSCX version A:%x B:%x\n",
1150 READHSCX(card->membase, card->iobase, 0,
1151 HSCX_VSTR) & 0xf,
1152 READHSCX(card->membase, card->iobase, 1,
1153 HSCX_VSTR) & 0xf);
1154
1155 }
1156 if (card->membase) {
1157 cli();
1158 timout = jiffies + (HZ / 5) + 1;
1159 *(byte *) (card->membase + 0x80) = 0;
1160 sti();
1161 while (jiffies <= timout);
1162
1163 cli();
1164 *(byte *) (card->membase + 0x80) = 1;
1165 timout = jiffies + (HZ / 5) + 1;
1166 sti();
1167 while (jiffies <= timout);
1168 }
1169 return (0);
1170 }
1171
1172 void
1173 modehscx(struct HscxState *hs, int mode,
1174 int ichan)
1175 {
1176 struct IsdnCardState *sp = hs->sp;
1177 int hscx = hs->hscx;
1178
1179 printk(KERN_DEBUG "modehscx hscx %d mode %d ichan %d\n",
1180 hscx, mode, ichan);
1181
1182 if (hscx == 0)
1183 ichan = 1 - ichan;
1184
1185 if (sp->membase) {
1186 writehscx_0(sp->membase, hscx, HSCX_CCR1, 0x85);
1187 writehscx_0(sp->membase, hscx, HSCX_XAD1, 0xFF);
1188 writehscx_0(sp->membase, hscx, HSCX_XAD2, 0xFF);
1189 writehscx_0(sp->membase, hscx, HSCX_RAH2, 0xFF);
1190 writehscx_0(sp->membase, hscx, HSCX_XBCH, 0x0);
1191
1192 switch (mode) {
1193 case (0):
1194 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1195 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0xff);
1196 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0xff);
1197 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1198 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1199 writehscx_0(sp->membase, hscx, HSCX_MODE, 0x84);
1200 break;
1201 case (1):
1202 if (ichan == 0) {
1203 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1204 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x7);
1205 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x7);
1206 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1207 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1208 } else {
1209 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1210 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x3);
1211 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x3);
1212 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1213 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1214 }
1215 writehscx_0(sp->membase, hscx, HSCX_MODE, 0xe4);
1216 writehscx_0(sp->membase, hscx, HSCX_CMDR, 0x41);
1217 break;
1218 case (2):
1219 if (ichan == 0) {
1220 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1221 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x7);
1222 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x7);
1223 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1224 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1225 } else {
1226 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1227 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x3);
1228 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x3);
1229 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1230 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1231 }
1232 writehscx_0(sp->membase, hscx, HSCX_MODE, 0x8c);
1233 writehscx_0(sp->membase, hscx, HSCX_CMDR, 0x41);
1234 break;
1235 }
1236 writehscx_0(sp->membase, hscx, HSCX_ISTA, 0x00);
1237 } else {
1238 writehscx_3(sp->iobase, hscx, HSCX_CCR1, 0x85);
1239 writehscx_3(sp->iobase, hscx, HSCX_XAD1, 0xFF);
1240 writehscx_3(sp->iobase, hscx, HSCX_XAD2, 0xFF);
1241 writehscx_3(sp->iobase, hscx, HSCX_RAH2, 0xFF);
1242 writehscx_3(sp->iobase, hscx, HSCX_XBCH, 0x00);
1243 writehscx_3(sp->iobase, hscx, HSCX_RLCR, 0x00);
1244
1245 switch (mode) {
1246 case (0):
1247 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1248 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0xff);
1249 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0xff);
1250 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1251 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1252 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0x84);
1253 break;
1254 case (1):
1255 if (ichan == 0) {
1256 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1257 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x2f);
1258 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x2f);
1259 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1260 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1261 } else {
1262 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1263 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x3);
1264 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x3);
1265 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1266 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1267 }
1268 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0xe4);
1269 writehscx_3(sp->iobase, hscx, HSCX_CMDR, 0x41);
1270 break;
1271 case (2):
1272 if (ichan == 0) {
1273 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1274 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x2f);
1275 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x2f);
1276 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1277 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1278 } else {
1279 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1280 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x3);
1281 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x3);
1282 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1283 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1284 }
1285 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0x8c);
1286 writehscx_3(sp->iobase, hscx, HSCX_CMDR, 0x41);
1287 break;
1288 }
1289 writehscx_3(sp->iobase, hscx, HSCX_ISTA, 0x00);
1290 }
1291 }
1292
1293 void
1294 teles_addlist(struct IsdnCardState *sp,
1295 struct PStack *st)
1296 {
1297 st->next = sp->stlist;
1298 sp->stlist = st;
1299 }
1300
1301 void
1302 teles_rmlist(struct IsdnCardState *sp,
1303 struct PStack *st)
1304 {
1305 struct PStack *p;
1306
1307 if (sp->stlist == st)
1308 sp->stlist = st->next;
1309 else {
1310 p = sp->stlist;
1311 while (p)
1312 if (p->next == st) {
1313 p->next = st->next;
1314 return;
1315 } else
1316 p = p->next;
1317 }
1318 }
1319
1320
1321 static void
1322 teles_l2l1(struct PStack *st, int pr,
1323 struct BufHeader *ibh)
1324 {
1325 struct IsdnCardState *sp = (struct IsdnCardState *)
1326 st->l1.hardware;
1327
1328
1329 switch (pr) {
1330 case (PH_DATA):
1331 if (sp->xmtibh)
1332 BufQueueLink(&sp->sq, ibh);
1333 else {
1334 sp->xmtibh = ibh;
1335 sp->sendptr = 0;
1336 sp->releasebuf = !0;
1337 fill_fifo(sp);
1338 }
1339 break;
1340 case (PH_DATA_PULLED):
1341 if (sp->xmtibh) {
1342 printk(KERN_DEBUG "teles_l2l1: this shouldn't happen\n");
1343 break;
1344 }
1345 sp->xmtibh = ibh;
1346 sp->sendptr = 0;
1347 sp->releasebuf = 0;
1348 fill_fifo(sp);
1349 break;
1350 case (PH_REQUEST_PULL):
1351 if (!sp->xmtibh) {
1352 st->l1.requestpull = 0;
1353 st->l1.l1l2(st, PH_PULL_ACK, NULL);
1354 } else
1355 st->l1.requestpull = !0;
1356 break;
1357 }
1358 }
1359
1360 static void
1361 check_ph_act(struct IsdnCardState *sp)
1362 {
1363 struct PStack *st = sp->stlist;
1364
1365 while (st) {
1366 if (st->l1.act_state)
1367 return;
1368 st = st->next;
1369 }
1370 sp->ph_active = 0;
1371 }
1372
1373 static void
1374 teles_manl1(struct PStack *st, int pr,
1375 void *arg)
1376 {
1377 struct IsdnCardState *sp = (struct IsdnCardState *)
1378 st->l1.hardware;
1379 long flags;
1380
1381 switch (pr) {
1382 case (PH_ACTIVATE):
1383 save_flags(flags);
1384 cli();
1385 if (sp->ph_active == 5) {
1386 st->l1.act_state = 2;
1387 restore_flags(flags);
1388 st->l1.l1man(st, PH_ACTIVATE, NULL);
1389 } else {
1390 st->l1.act_state = 1;
1391 if (sp->ph_active == 0)
1392 restart_ph(sp);
1393 restore_flags(flags);
1394 }
1395 break;
1396 case (PH_DEACTIVATE):
1397 st->l1.act_state = 0;
1398 check_ph_act(sp);
1399 break;
1400 }
1401 }
1402
1403 static void
1404 teles_l2l1discardq(struct PStack *st, int pr,
1405 void *heldby, int releasetoo)
1406 {
1407 struct IsdnCardState *sp = (struct IsdnCardState *) st->l1.hardware;
1408
1409 #ifdef DEBUG_MAGIC
1410 if (sp->magic != 301271) {
1411 printk(KERN_DEBUG "isac_discardq magic not 301271\n");
1412 return;
1413 }
1414 #endif
1415
1416 BufQueueDiscard(&sp->sq, pr, heldby, releasetoo);
1417 }
1418
1419 void
1420 setstack_teles(struct PStack *st, struct IsdnCardState *sp)
1421 {
1422 st->l1.hardware = sp;
1423 st->l1.sbufpool = &(sp->sbufpool);
1424 st->l1.rbufpool = &(sp->rbufpool);
1425 st->l1.smallpool = &(sp->smallpool);
1426 st->protocol = sp->teistack->protocol;
1427
1428 setstack_tei(st);
1429
1430 st->l1.stlistp = &(sp->stlist);
1431 st->l1.act_state = 0;
1432 st->l2.l2l1 = teles_l2l1;
1433 st->l2.l2l1discardq = teles_l2l1discardq;
1434 st->ma.manl1 = teles_manl1;
1435 st->l1.requestpull = 0;
1436 }
1437
1438 void
1439 init_hscxstate(struct IsdnCardState *sp,
1440 int hscx)
1441 {
1442 struct HscxState *hsp = sp->hs + hscx;
1443
1444 hsp->sp = sp;
1445 hsp->hscx = hscx;
1446 hsp->membase = sp->membase;
1447 hsp->iobase = sp->iobase;
1448
1449 hsp->tqueue.next = 0;
1450 hsp->tqueue.sync = 0;
1451 hsp->tqueue.routine = (void *) (void *) hscx_bh;
1452 hsp->tqueue.data = hsp;
1453
1454 hsp->inuse = 0;
1455 hsp->init = 0;
1456 hsp->active = 0;
1457
1458 #ifdef DEBUG_MAGIC
1459 hsp->magic = 301270;
1460 #endif
1461 }
1462
1463 void
1464 initcard(int cardnr)
1465 {
1466 struct IsdnCardState *sp;
1467 struct IsdnCard *card = cards + cardnr;
1468
1469 sp = (struct IsdnCardState *)
1470 Smalloc(sizeof(struct IsdnCardState), GFP_KERNEL,
1471 "struct IsdnCardState");
1472
1473 sp->membase = card->membase;
1474 sp->iobase = card->iobase;
1475 sp->cardnr = cardnr;
1476
1477 BufPoolInit(&sp->sbufpool, ISAC_SBUF_ORDER, ISAC_SBUF_BPPS,
1478 ISAC_SBUF_MAXPAGES);
1479 BufPoolInit(&sp->rbufpool, ISAC_RBUF_ORDER, ISAC_RBUF_BPPS,
1480 ISAC_RBUF_MAXPAGES);
1481 BufPoolInit(&sp->smallpool, ISAC_SMALLBUF_ORDER, ISAC_SMALLBUF_BPPS,
1482 ISAC_SMALLBUF_MAXPAGES);
1483
1484 sp->dlogspace = Smalloc(4096, GFP_KERNEL, "dlogspace");
1485
1486 initisac(card->membase, card->iobase);
1487
1488 sp->rcvibh = NULL;
1489 sp->rcvptr = 0;
1490 sp->xmtibh = NULL;
1491 sp->sendptr = 0;
1492 sp->event = 0;
1493 sp->tqueue.next = 0;
1494 sp->tqueue.sync = 0;
1495 sp->tqueue.routine = (void *) (void *) isac_bh;
1496 sp->tqueue.data = sp;
1497
1498 BufQueueInit(&sp->rq);
1499 BufQueueInit(&sp->sq);
1500
1501 sp->stlist = NULL;
1502
1503 sp->ph_active = 0;
1504
1505 sp->dlogflag = 0;
1506 sp->debug = 0;
1507
1508 sp->releasebuf = 0;
1509 #ifdef DEBUG_MAGIC
1510 sp->magic = 301271;
1511 #endif
1512
1513 cards[sp->cardnr].sp = sp;
1514
1515 init_hscxstate(sp, 0);
1516 init_hscxstate(sp, 1);
1517
1518 modehscx(sp->hs, 0, 0);
1519 modehscx(sp->hs + 1, 0, 0);
1520
1521 WRITEISAC(sp->membase, sp->iobase, ISAC_MASK, 0x0);
1522 }
1523
1524 static int
1525 get_irq(int cardnr)
1526 {
1527 struct IsdnCard *card = cards + cardnr;
1528 long flags;
1529
1530 save_flags(flags);
1531 cli();
1532 if (request_irq(card->interrupt, &teles_interrupt,
1533 SA_INTERRUPT, "teles", NULL)) {
1534 printk(KERN_WARNING "Teles couldn't get interrupt %d\n",
1535 card->interrupt);
1536 restore_flags(flags);
1537 return (!0);
1538 }
1539 irq2dev_map[card->interrupt] = (void *) card->sp;
1540 restore_flags(flags);
1541 return (0);
1542 }
1543
1544 static void
1545 release_irq(int cardnr)
1546 {
1547 struct IsdnCard *card = cards + cardnr;
1548
1549 irq2dev_map[card->interrupt] = NULL;
1550 free_irq(card->interrupt, NULL);
1551 }
1552
1553 void
1554 close_hscxstate(struct HscxState *hs)
1555 {
1556 modehscx(hs, 0, 0);
1557 hs->inuse = 0;
1558
1559 if (hs->init) {
1560 BufPoolFree(&hs->smallpool);
1561 BufPoolFree(&hs->rbufpool);
1562 BufPoolFree(&hs->sbufpool);
1563 }
1564 hs->init = 0;
1565 }
1566
1567 void
1568 closecard(int cardnr)
1569 {
1570 struct IsdnCardState *sp = cards[cardnr].sp;
1571
1572 cards[cardnr].sp = NULL;
1573
1574 Sfree(sp->dlogspace);
1575
1576 BufPoolFree(&sp->smallpool);
1577 BufPoolFree(&sp->rbufpool);
1578 BufPoolFree(&sp->sbufpool);
1579
1580 close_hscxstate(sp->hs + 1);
1581 close_hscxstate(sp->hs);
1582
1583 if (cards[cardnr].iobase)
1584 release_region(cards[cardnr].iobase, 8);
1585
1586 Sfree((void *) sp);
1587 }
1588
1589 void
1590 teles_shiftcards(int idx)
1591 {
1592 int i;
1593
1594 for (i = idx; i < 15; i++)
1595 memcpy(&cards[i],&cards[i+1],sizeof(cards[i]));
1596 }
1597
1598 int
1599 teles_inithardware(void)
1600 {
1601 int foundcards = 0;
1602 int i = 0;
1603
1604 while (i < nrcards) {
1605 if (!cards[i].protocol)
1606 break;
1607 switch (checkcard(i)) {
1608 case (0):
1609 initcard(i);
1610 if (get_irq(i)) {
1611 closecard(i);
1612 teles_shiftcards(i);
1613 } else {
1614 foundcards++;
1615 i++;
1616 }
1617 break;
1618 case (-1):
1619 teles_shiftcards(i);
1620 break;
1621 case (-2):
1622 release_region(cards[i].iobase, 8);
1623 teles_shiftcards(i);
1624 printk(KERN_WARNING "NO Teles card found at 0x%x!\n", cards[i].iobase);
1625 break;
1626 }
1627 }
1628 return foundcards;
1629 }
1630
1631 void
1632 teles_closehardware(void)
1633 {
1634 int i;
1635
1636 for (i = 0; i < nrcards; i++)
1637 if (cards[i].sp) {
1638 release_irq(i);
1639 closecard(i);
1640 }
1641 }
1642
1643 static void
1644 hscx_l2l1(struct PStack *st, int pr,
1645 struct BufHeader *ibh)
1646 {
1647 struct IsdnCardState *sp = (struct IsdnCardState *)
1648 st->l1.hardware;
1649 struct HscxState *hsp = sp->hs + st->l1.hscx;
1650
1651 switch (pr) {
1652 case (PH_DATA):
1653 if (hsp->xmtibh)
1654 BufQueueLink(&hsp->sq, ibh);
1655 else {
1656 hsp->xmtibh = ibh;
1657 hsp->sendptr = 0;
1658 hsp->releasebuf = !0;
1659 hscx_fill_fifo(hsp);
1660 }
1661 break;
1662 case (PH_DATA_PULLED):
1663 if (hsp->xmtibh) {
1664 printk(KERN_DEBUG "hscx_l2l1: this shouldn't happen\n");
1665 break;
1666 }
1667 hsp->xmtibh = ibh;
1668 hsp->sendptr = 0;
1669 hsp->releasebuf = 0;
1670 hscx_fill_fifo(hsp);
1671 break;
1672 case (PH_REQUEST_PULL):
1673 if (!hsp->xmtibh) {
1674 st->l1.requestpull = 0;
1675 st->l1.l1l2(st, PH_PULL_ACK, NULL);
1676 } else
1677 st->l1.requestpull = !0;
1678 break;
1679 }
1680
1681 }
1682
1683 extern struct IsdnBuffers *tracebuf;
1684
1685 static void
1686 hscx_l2l1discardq(struct PStack *st, int pr, void *heldby,
1687 int releasetoo)
1688 {
1689 struct IsdnCardState *sp = (struct IsdnCardState *)
1690 st->l1.hardware;
1691 struct HscxState *hsp = sp->hs + st->l1.hscx;
1692
1693 #ifdef DEBUG_MAGIC
1694 if (hsp->magic != 301270) {
1695 printk(KERN_DEBUG "hscx_discardq magic not 301270\n");
1696 return;
1697 }
1698 #endif
1699
1700 BufQueueDiscard(&hsp->sq, pr, heldby, releasetoo);
1701 }
1702
1703 static int
1704 open_hscxstate(struct IsdnCardState *sp,
1705 int hscx)
1706 {
1707 struct HscxState *hsp = sp->hs + hscx;
1708
1709 if (!hsp->init) {
1710 BufPoolInit(&hsp->sbufpool, HSCX_SBUF_ORDER, HSCX_SBUF_BPPS,
1711 HSCX_SBUF_MAXPAGES);
1712 BufPoolInit(&hsp->rbufpool, HSCX_RBUF_ORDER, HSCX_RBUF_BPPS,
1713 HSCX_RBUF_MAXPAGES);
1714 BufPoolInit(&hsp->smallpool, HSCX_SMALLBUF_ORDER, HSCX_SMALLBUF_BPPS,
1715 HSCX_SMALLBUF_MAXPAGES);
1716 }
1717 hsp->init = !0;
1718
1719 BufQueueInit(&hsp->rq);
1720 BufQueueInit(&hsp->sq);
1721
1722 hsp->releasebuf = 0;
1723 hsp->rcvibh = NULL;
1724 hsp->xmtibh = NULL;
1725 hsp->rcvptr = 0;
1726 hsp->sendptr = 0;
1727 hsp->event = 0;
1728 return (0);
1729 }
1730
1731 static void
1732 hscx_manl1(struct PStack *st, int pr,
1733 void *arg)
1734 {
1735 struct IsdnCardState *sp = (struct IsdnCardState *)
1736 st->l1.hardware;
1737 struct HscxState *hsp = sp->hs + st->l1.hscx;
1738
1739 switch (pr) {
1740 case (PH_ACTIVATE):
1741 hsp->active = !0;
1742 modehscx(hsp, st->l1.hscxmode, st->l1.hscxchannel);
1743 st->l1.l1man(st, PH_ACTIVATE, NULL);
1744 break;
1745 case (PH_DEACTIVATE):
1746 if (!hsp->xmtibh)
1747 modehscx(hsp, 0, 0);
1748
1749 hsp->active = 0;
1750 break;
1751 }
1752 }
1753
1754 int
1755 setstack_hscx(struct PStack *st, struct HscxState *hs)
1756 {
1757 if (open_hscxstate(st->l1.hardware, hs->hscx))
1758 return (-1);
1759
1760 st->l1.hscx = hs->hscx;
1761 st->l2.l2l1 = hscx_l2l1;
1762 st->ma.manl1 = hscx_manl1;
1763 st->l2.l2l1discardq = hscx_l2l1discardq;
1764
1765 st->l1.sbufpool = &hs->sbufpool;
1766 st->l1.rbufpool = &hs->rbufpool;
1767 st->l1.smallpool = &hs->smallpool;
1768 st->l1.act_state = 0;
1769 st->l1.requestpull = 0;
1770
1771 hs->st = st;
1772 return (0);
1773 }
1774
1775 void
1776 teles_reportcard(int cardnr)
1777 {
1778
1779 printk(KERN_DEBUG "teles_reportcard\n");
1780
1781 }
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