include/linux/cd1400.h

/* */
   1 /*****************************************************************************/
   2 
   3 /*
   4  *      cd1400.h  -- cd1400 UART hardware info.
   5  *
   6  *      Copyright (C) 1994-1996  Greg Ungerer (gerg@stallion.oz.au).
   7  *
   8  *      This program is free software; you can redistribute it and/or modify
   9  *      it under the terms of the GNU General Public License as published by
  10  *      the Free Software Foundation; either version 2 of the License, or
  11  *      (at your option) any later version.
  12  *
  13  *      This program is distributed in the hope that it will be useful,
  14  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *      GNU General Public License for more details.
  17  *
  18  *      You should have received a copy of the GNU General Public License
  19  *      along with this program; if not, write to the Free Software
  20  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22 
  23 /*****************************************************************************/
  24 #ifndef _CD1400_H
  25 #define _CD1400_H
  26 /*****************************************************************************/
  27 
  28 /*
  29  *      Define the number of async ports per cd1400 uart chip.
  30  */
  31 #define CD1400_PORTS            4
  32 
  33 /*
  34  *      Define the cd1400 uarts internal FIFO sizes.
  35  */
  36 #define CD1400_TXFIFOSIZE       12
  37 #define CD1400_RXFIFOSIZE       12
  38 
  39 /*
  40  *      Local RX FIFO thresh hold level. Also define the RTS thresh hold
  41  *      based on the RX thresh hold.
  42  */
  43 #define FIFO_RXTHRESHOLD        6
  44 #define FIFO_RTSTHRESHOLD       7
  45 
  46 /*****************************************************************************/
  47 
  48 /*
  49  *      Define the cd1400 register addresses. These are all the valid
  50  *      registers with the cd1400. Some are global, some virtual, some
  51  *      per port.
  52  */
  53 #define GFRCR           0x40
  54 #define CAR             0x68
  55 #define GCR             0x4b
  56 #define SVRR            0x67
  57 #define RICR            0x44
  58 #define TICR            0x45
  59 #define MICR            0x46
  60 #define RIR             0x6b
  61 #define TIR             0x6a
  62 #define MIR             0x69
  63 #define PPR             0x7e
  64 
  65 #define RIVR            0x43
  66 #define TIVR            0x42
  67 #define MIVR            0x41
  68 #define TDR             0x63
  69 #define RDSR            0x62
  70 #define MISR            0x4c
  71 #define EOSRR           0x60
  72 
  73 #define LIVR            0x18
  74 #define CCR             0x05
  75 #define SRER            0x06
  76 #define COR1            0x08
  77 #define COR2            0x09
  78 #define COR3            0x0a
  79 #define COR4            0x1e
  80 #define COR5            0x1f
  81 #define CCSR            0x0b
  82 #define RDCR            0x0e
  83 #define SCHR1           0x1a
  84 #define SCHR2           0x1b
  85 #define SCHR3           0x1c
  86 #define SCHR4           0x1d
  87 #define SCRL            0x22
  88 #define SCRH            0x23
  89 #define LNC             0x24
  90 #define MCOR1           0x15
  91 #define MCOR2           0x16
  92 #define RTPR            0x21
  93 #define MSVR1           0x6c
  94 #define MSVR2           0x6d
  95 #define PSVR            0x6f
  96 #define RBPR            0x78
  97 #define RCOR            0x7c
  98 #define TBPR            0x72
  99 #define TCOR            0x76
 100 
 101 /*****************************************************************************/
 102 
 103 /*
 104  *      Define the set of baud rate clock divisors.
 105  */
 106 #define CD1400_CLK0     8
 107 #define CD1400_CLK1     32
 108 #define CD1400_CLK2     128
 109 #define CD1400_CLK3     512
 110 #define CD1400_CLK4     2048
 111 
 112 #define CD1400_NUMCLKS  5
 113 
 114 /*****************************************************************************/
 115 
 116 /*
 117  *      Define the clock pre-scalar value to be a 5 ms clock. This should be
 118  *      OK for now. It would probably be better to make it 10 ms, but we
 119  *      can't fit that divisor into 8 bits!
 120  */
 121 #define PPR_SCALAR      244
 122 
 123 /*****************************************************************************/
 124 
 125 /*
 126  *      Define values used to set character size options.
 127  */
 128 #define COR1_CHL5       0x00
 129 #define COR1_CHL6       0x01
 130 #define COR1_CHL7       0x02
 131 #define COR1_CHL8       0x03
 132 
 133 /*
 134  *      Define values used to set the number of stop bits.
 135  */
 136 #define COR1_STOP1      0x00
 137 #define COR1_STOP15     0x04
 138 #define COR1_STOP2      0x08
 139 
 140 /*
 141  *      Define values used to set the parity scheme in use.
 142  */
 143 #define COR1_PARNONE    0x00
 144 #define COR1_PARFORCE   0x20
 145 #define COR1_PARENB     0x40
 146 #define COR1_PARIGNORE  0x10
 147 
 148 #define COR1_PARODD     0x80
 149 #define COR1_PAREVEN    0x00
 150 
 151 #define COR2_IXM        0x80
 152 #define COR2_TXIBE      0x40
 153 #define COR2_ETC        0x20
 154 #define COR2_LLM        0x10
 155 #define COR2_RLM        0x08
 156 #define COR2_RTSAO      0x04
 157 #define COR2_CTSAE      0x02
 158 
 159 #define COR3_SCDRNG     0x80
 160 #define COR3_SCD34      0x40
 161 #define COR3_FCT        0x20
 162 #define COR3_SCD12      0x10
 163 
 164 /*
 165  *      Define values used by COR4.
 166  */
 167 #define COR4_BRKINT     0x08
 168 #define COR4_IGNBRK     0x18
 169 
 170 /*****************************************************************************/
 171 
 172 /*
 173  *      Define the modem control register values.
 174  *      Note that the actual hardware is a little different to the conventional
 175  *      pin names on the cd1400.
 176  */
 177 #define MSVR1_DTR       0x01
 178 #define MSVR1_DSR       0x10
 179 #define MSVR1_RI        0x20
 180 #define MSVR1_CTS       0x40
 181 #define MSVR1_DCD       0x80
 182 
 183 #define MSVR2_RTS       0x02
 184 #define MSVR2_DSR       0x10
 185 #define MSVR2_RI        0x20
 186 #define MSVR2_CTS       0x40
 187 #define MSVR2_DCD       0x80
 188 
 189 #define MCOR1_DCD       0x80
 190 #define MCOR1_CTS       0x40
 191 #define MCOR1_RI        0x20
 192 #define MCOR1_DSR       0x10
 193 
 194 #define MCOR2_DCD       0x80
 195 #define MCOR2_CTS       0x40
 196 #define MCOR2_RI        0x20
 197 #define MCOR2_DSR       0x10
 198 
 199 /*****************************************************************************/
 200 
 201 /*
 202  *      Define the bits used with the service (interrupt) enable register.
 203  */
 204 #define SRER_NNDT       0x01
 205 #define SRER_TXEMPTY    0x02
 206 #define SRER_TXDATA     0x04
 207 #define SRER_RXDATA     0x10
 208 #define SRER_MODEM      0x80
 209 
 210 /*****************************************************************************/
 211 
 212 /*
 213  *      Define operational commands for the command register.
 214  */
 215 #define CCR_RESET       0x80
 216 #define CCR_CORCHANGE   0x4e
 217 #define CCR_SENDCH      0x20
 218 #define CCR_CHANCTRL    0x10
 219 
 220 #define CCR_TXENABLE    (CCR_CHANCTRL | 0x08)
 221 #define CCR_TXDISABLE   (CCR_CHANCTRL | 0x04)
 222 #define CCR_RXENABLE    (CCR_CHANCTRL | 0x02)
 223 #define CCR_RXDISABLE   (CCR_CHANCTRL | 0x01)
 224 
 225 #define CCR_SENDSCHR1   (CCR_SENDCH | 0x01)
 226 #define CCR_SENDSCHR2   (CCR_SENDCH | 0x02)
 227 #define CCR_SENDSCHR3   (CCR_SENDCH | 0x03)
 228 #define CCR_SENDSCHR4   (CCR_SENDCH | 0x04)
 229 
 230 #define CCR_RESETCHAN   (CCR_RESET | 0x00)
 231 #define CCR_RESETFULL   (CCR_RESET | 0x01)
 232 #define CCR_TXFLUSHFIFO (CCR_RESET | 0x02)
 233 
 234 #define CCR_MAXWAIT     10000
 235 
 236 /*****************************************************************************/
 237 
 238 /*
 239  *      Define the valid acknowledgement types (for hw ack cycle).
 240  */
 241 #define ACK_TYPMASK     0x07
 242 #define ACK_TYPTX       0x02
 243 #define ACK_TYPMDM      0x01
 244 #define ACK_TYPRXGOOD   0x03
 245 #define ACK_TYPRXBAD    0x07
 246 
 247 #define SVRR_RX         0x01
 248 #define SVRR_TX         0x02
 249 #define SVRR_MDM        0x04
 250 
 251 #define ST_OVERRUN      0x01
 252 #define ST_FRAMING      0x02
 253 #define ST_PARITY       0x04
 254 #define ST_BREAK        0x08
 255 #define ST_SCHAR1       0x10
 256 #define ST_SCHAR2       0x20
 257 #define ST_SCHAR3       0x30
 258 #define ST_SCHAR4       0x40
 259 #define ST_RANGE        0x70
 260 #define ST_SCHARMASK    0x70
 261 #define ST_TIMEOUT      0x80
 262 
 263 #define MISR_DCD        0x80
 264 #define MISR_CTS        0x40
 265 #define MISR_RI         0x20
 266 #define MISR_DSR        0x10
 267 
 268 /*****************************************************************************/
 269 
 270 /*
 271  *      Defines for the CCSR status register.
 272  */
 273 #define CCSR_RXENABLED  0x80
 274 #define CCSR_RXFLOWON   0x40
 275 #define CCSR_RXFLOWOFF  0x20
 276 #define CCSR_TXENABLED  0x08
 277 #define CCSR_TXFLOWON   0x04
 278 #define CCSR_TXFLOWOFF  0x02
 279 
 280 /*****************************************************************************/
 281 
 282 /*
 283  *      Define the embedded commands.
 284  */
 285 #define ETC_CMD         0x00
 286 #define ETC_STARTBREAK  0x81
 287 #define ETC_DELAY       0x82
 288 #define ETC_STOPBREAK   0x83
 289 
 290 /*****************************************************************************/
 291 #endif
/* */
root/include/linux/cd1400.h

INCLUDED FROM
