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1 /*
2 * linux/drivers/block/triton.c Version 1.08 Mar 13, 1996
3 *
4 * Copyright (c) 1995-1996 Mark Lord
5 * May be copied or modified under the terms of the GNU General Public License
6 */
7
8 /*
9 * This module provides support for the Bus Master IDE DMA function
10 * of the Intel PCI Triton chipset (82371FB).
11 *
12 * DMA is currently supported only for hard disk drives (not cdroms).
13 *
14 * Support for cdroms will likely be added at a later date,
15 * after broader experience has been obtained with hard disks.
16 *
17 * Up to four drives may be enabled for DMA, and the Triton chipset will
18 * (hopefully) arbitrate the PCI bus among them. Note that the 82371FB chip
19 * provides a single "line buffer" for the BM IDE function, so performance of
20 * multiple (two) drives doing DMA simultaneously will suffer somewhat,
21 * as they contest for that resource bottleneck. This is handled transparently
22 * inside the 82371FB chip.
23 *
24 * By default, DMA support is prepared for use, but is currently enabled only
25 * for drives which support multi-word DMA mode2 (mword2), or which are
26 * recognized as "good" (see table below). Drives with only mode0 or mode1
27 * (single or multi) DMA should also work with this chipset/driver (eg. MC2112A)
28 * but are not enabled by default. Use "hdparm -i" to view modes supported
29 * by a given drive.
30 *
31 * The hdparm-2.4 (or later) utility can be used for manually enabling/disabling
32 * DMA support, but must be (re-)compiled against this kernel version or later.
33 *
34 * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
35 * If problems arise, ide.c will disable DMA operation after a few retries.
36 * This error recovery mechanism works and has been extremely well exercised.
37 *
38 * IDE drives, depending on their vintage, may support several different modes
39 * of DMA operation. The boot-time modes are indicated with a "*" in
40 * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
41 * the "hdparm -X" feature. There is seldom a need to do this, as drives
42 * normally power-up with their "best" PIO/DMA modes enabled.
43 *
44 * Testing was done with an ASUS P55TP4XE/100 system and the following drives:
45 *
46 * Quantum Fireball 1080A (1Gig w/83kB buffer), DMA mode2, PIO mode4.
47 * - DMA mode2 works well (7.4MB/sec), despite the tiny on-drive buffer.
48 * - This drive also does PIO mode4, at about the same speed as DMA mode2.
49 * An awesome drive for the price!
50 *
51 * Fujitsu M1606TA (1Gig w/256kB buffer), DMA mode2, PIO mode4.
52 * - DMA mode2 gives horrible performance (1.6MB/sec), despite the good
53 * size of the on-drive buffer and a boasted 10ms average access time.
54 * - PIO mode4 was better, but peaked at a mere 4.5MB/sec.
55 *
56 * Micropolis MC2112A (1Gig w/508kB buffer), drive pre-dates EIDE and ATA2.
57 * - DMA works fine (2.2MB/sec), probably due to the large on-drive buffer.
58 * - This older drive can also be tweaked for fastPIO (3.7MB/sec) by using
59 * maximum clock settings (5,4) and setting all flags except prefetch.
60 *
61 * Western Digital AC31000H (1Gig w/128kB buffer), DMA mode1, PIO mode3.
62 * - DMA does not work reliably. The drive appears to be somewhat tardy
63 * in deasserting DMARQ at the end of a sector. This is evident in
64 * the observation that WRITEs work most of the time, depending on
65 * cache-buffer occupancy, but multi-sector reads seldom work.
66 *
67 * Testing was done with a Gigabyte GA-586 ATE system and the following drive:
68 * (Uwe Bonnes - bon@elektron.ikp.physik.th-darmstadt.de)
69 *
70 * Western Digital AC31600H (1.6Gig w/128kB buffer), DMA mode2, PIO mode4.
71 * - much better than its 1Gig cousin, this drive is reported to work
72 * very well with DMA (7.3MB/sec).
73 *
74 * Other drives:
75 *
76 * Maxtor 7540AV (515Meg w/32kB buffer), DMA modes mword0/sword2, PIO mode3.
77 * - a budget drive, with budget performance, around 3MB/sec.
78 *
79 * Western Digital AC2850F (814Meg w/64kB buffer), DMA mode1, PIO mode3.
80 * - another "caviar" drive, similar to the AC31000, except that this one
81 * worked with DMA in at least one system. Throughput is about 3.8MB/sec
82 * for both DMA and PIO.
83 *
84 * Conner CFS850A (812Meg w/64kB buffer), DMA mode2, PIO mode4.
85 * - like most Conner models, this drive proves that even a fast interface
86 * cannot improve slow media. Both DMA and PIO peak around 3.5MB/sec.
87 *
88 * Maxtor 71260AT (1204Meg w/256kB buffer), DMA mword0/sword2, PIO mode3.
89 * - works with DMA, giving 3-4MB/sec performance, about the same as mode3.
90 *
91 * If you have any drive models to add, email your results to: mlord@pobox.com
92 * Keep an eye on /var/adm/messages for "DMA disabled" messages.
93 *
94 * Some people have reported trouble with Intel Zappa motherboards.
95 * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
96 * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
97 * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this).
98 *
99 * And, yes, Intel Zappa boards really *do* use the Triton IDE ports.
100 */
101 #include <linux/config.h>
102 #include <linux/types.h>
103 #include <linux/kernel.h>
104 #include <linux/timer.h>
105 #include <linux/mm.h>
106 #include <linux/ioport.h>
107 #include <linux/interrupt.h>
108 #include <linux/blkdev.h>
109 #include <linux/hdreg.h>
110 #include <linux/pci.h>
111 #include <linux/bios32.h>
112
113 #include <asm/io.h>
114 #include <asm/dma.h>
115
116 #include "ide.h"
117
118 /*
119 * good_dma_drives() lists the model names (from "hdparm -i")
120 * of drives which do not support mword2 DMA but which are
121 * known to work fine with this interface under Linux.
122 */
123 const char *good_dma_drives[] = {"Micropolis 2112A",
124 "Maxtor 71260 AT",
125 "CONNER CTMA 4000"};
126
127 /*
128 * Our Physical Region Descriptor (PRD) table should be large enough
129 * to handle the biggest I/O request we are likely to see. Since requests
130 * can have no more than 256 sectors, and since the typical blocksize is
131 * two sectors, we could get by with a limit of 128 entries here for the
132 * usual worst case. Most requests seem to include some contiguous blocks,
133 * further reducing the number of table entries required.
134 *
135 * The driver reverts to PIO mode for individual requests that exceed
136 * this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling
137 * 100% of all crazy scenarios here is not necessary.
138 *
139 * As it turns out though, we must allocate a full 4KB page for this,
140 * so the two PRD tables (ide0 & ide1) will each get half of that,
141 * allowing each to have about 256 entries (8 bytes each) from this.
142 */
143 #define PRD_BYTES 8
144 #define PRD_ENTRIES (PAGE_SIZE / (2 * PRD_BYTES))
145 #define DEFAULT_BMIBA 0xe800 /* in case BIOS did not init it */
146
147 /*
148 * dma_intr() is the handler for disk read/write DMA interrupts
149 */
150 static void dma_intr (ide_drive_t *drive)
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151 {
152 byte stat, dma_stat;
153 int i;
154 struct request *rq = HWGROUP(drive)->rq;
155 unsigned short dma_base = HWIF(drive)->dma_base;
156
157 dma_stat = inb(dma_base+2); /* get DMA status */
158 outb(inb(dma_base)&~1, dma_base); /* stop DMA operation */
159 stat = GET_STAT(); /* get drive status */
160 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
161 if ((dma_stat & 7) == 4) { /* verify good DMA status */
162 rq = HWGROUP(drive)->rq;
163 for (i = rq->nr_sectors; i > 0;) {
164 i -= rq->current_nr_sectors;
165 ide_end_request(1, HWGROUP(drive));
166 }
167 return;
168 }
169 printk("%s: bad DMA status: 0x%02x\n", drive->name, dma_stat);
170 }
171 sti();
172 ide_error(drive, "dma_intr", stat);
173 }
174
175 /*
176 * build_dmatable() prepares a dma request.
177 * Returns 0 if all went okay, returns 1 otherwise.
178 */
179 static int build_dmatable (ide_drive_t *drive)
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180 {
181 struct request *rq = HWGROUP(drive)->rq;
182 struct buffer_head *bh = rq->bh;
183 unsigned long size, addr, *table = HWIF(drive)->dmatable;
184 unsigned int count = 0;
185
186 do {
187 /*
188 * Determine addr and size of next buffer area. We assume that
189 * individual virtual buffers are always composed linearly in
190 * physical memory. For example, we assume that any 8kB buffer
191 * is always composed of two adjacent physical 4kB pages rather
192 * than two possibly non-adjacent physical 4kB pages.
193 */
194 if (bh == NULL) { /* paging and tape requests have (rq->bh == NULL) */
195 addr = virt_to_bus (rq->buffer);
196 #ifdef CONFIG_BLK_DEV_IDETAPE
197 if (drive->media == ide_tape)
198 size = drive->tape.pc->request_transfer;
199 else
200 #endif /* CONFIG_BLK_DEV_IDETAPE */
201 size = rq->nr_sectors << 9;
202 } else {
203 /* group sequential buffers into one large buffer */
204 addr = virt_to_bus (bh->b_data);
205 size = bh->b_size;
206 while ((bh = bh->b_reqnext) != NULL) {
207 if ((addr + size) != virt_to_bus (bh->b_data))
208 break;
209 size += bh->b_size;
210 }
211 }
212
213 /*
214 * Fill in the dma table, without crossing any 64kB boundaries.
215 * We assume 16-bit alignment of all blocks.
216 */
217 while (size) {
218 if (++count >= PRD_ENTRIES) {
219 printk("%s: DMA table too small\n", drive->name);
220 return 1; /* revert to PIO for this request */
221 } else {
222 unsigned long bcount = 0x10000 - (addr & 0xffff);
223 if (bcount > size)
224 bcount = size;
225 *table++ = addr;
226 *table++ = bcount;
227 addr += bcount;
228 size -= bcount;
229 }
230 }
231 } while (bh != NULL);
232 if (count) {
233 *--table |= 0x80000000; /* set End-Of-Table (EOT) bit */
234 return 0;
235 }
236 printk("%s: empty DMA table?\n", drive->name);
237 return 1; /* let the PIO routines handle this weirdness */
238 }
239
240 static int config_drive_for_dma (ide_drive_t *drive)
/* */
241 {
242 const char **list;
243
244 struct hd_driveid *id = drive->id;
245 if (id && (id->capability & 1)) {
246 /* Enable DMA on any drive that supports mword2 DMA */
247 if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
248 drive->using_dma = 1;
249 return 0; /* DMA enabled */
250 }
251 /* Consult the list of known "good" drives */
252 list = good_dma_drives;
253 while (*list) {
254 if (!strcmp(*list++,id->model)) {
255 drive->using_dma = 1;
256 return 0; /* DMA enabled */
257 }
258 }
259 }
260 return 1; /* DMA not enabled */
261 }
262
263 /*
264 * triton_dmaproc() initiates/aborts DMA read/write operations on a drive.
265 *
266 * The caller is assumed to have selected the drive and programmed the drive's
267 * sector address using CHS or LBA. All that remains is to prepare for DMA
268 * and then issue the actual read/write DMA/PIO command to the drive.
269 *
270 * For ATAPI devices, we just prepare for DMA and return. The caller should
271 * then issue the packet command to the drive and call us again with
272 * ide_dma_begin afterwards.
273 *
274 * Returns 0 if all went well.
275 * Returns 1 if DMA read/write could not be started, in which case
276 * the caller should revert to PIO for the current request.
277 */
278 static int triton_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
/* */
279 {
280 unsigned long dma_base = HWIF(drive)->dma_base;
281 unsigned int reading = (1 << 3);
282
283 switch (func) {
284 case ide_dma_abort:
285 outb(inb(dma_base)&~1, dma_base); /* stop DMA */
286 return 0;
287 case ide_dma_check:
288 return config_drive_for_dma (drive);
289 case ide_dma_write:
290 reading = 0;
291 case ide_dma_read:
292 break;
293 case ide_dma_status_bad:
294 return ((inb(dma_base+2) & 7) != 4); /* verify good DMA status */
295 case ide_dma_transferred:
296 #if 0
297 return (number of bytes actually transferred);
298 #else
299 return (0);
300 #endif
301 case ide_dma_begin:
302 outb(inb(dma_base)|1, dma_base); /* begin DMA */
303 return 0;
304 default:
305 printk("triton_dmaproc: unsupported func: %d\n", func);
306 return 1;
307 }
308 if (build_dmatable (drive))
309 return 1;
310 outl(virt_to_bus (HWIF(drive)->dmatable), dma_base + 4); /* PRD table */
311 outb(reading, dma_base); /* specify r/w */
312 outb(0x26, dma_base+2); /* clear status bits */
313 #ifdef CONFIG_BLK_DEV_IDEATAPI
314 if (drive->media != ide_disk)
315 return 0;
316 #endif /* CONFIG_BLK_DEV_IDEATAPI */
317 ide_set_handler(drive, &dma_intr, WAIT_CMD); /* issue cmd to drive */
318 OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
319 outb(inb(dma_base)|1, dma_base); /* begin DMA */
320 return 0;
321 }
322
323 /*
324 * print_triton_drive_flags() displays the currently programmed options
325 * in the 430FX (Triton) chipset for a given drive.
326 *
327 * If fastDMA is "no", then slow ISA timings are used for DMA data xfers.
328 * If fastPIO is "no", then slow ISA timings are used for PIO data xfers.
329 * If IORDY is "no", then IORDY is assumed to always be asserted.
330 * If PreFetch is "no", then data pre-fetch/post are not used.
331 *
332 * When "fastPIO" and/or "fastDMA" are "yes", then faster PCI timings and
333 * back-to-back 16-bit data transfers are enabled, using the sample_CLKs
334 * and recovery_CLKs (PCI clock cycles) timing parameters for that interface.
335 */
336 static void print_triton_drive_flags (unsigned int unit, byte flags)
/* */
337 {
338 printk(" %s ", unit ? "slave :" : "master:");
339 printk( "fastDMA=%s", (flags&9) ? "on " : "off");
340 printk(" PreFetch=%s", (flags&4) ? "on " : "off");
341 printk(" IORDY=%s", (flags&2) ? "on " : "off");
342 printk(" fastPIO=%s\n", ((flags&9)==1) ? "on " : "off");
343 }
344
345 static void init_triton_dma (ide_hwif_t *hwif, unsigned short base)
/* */
346 {
347 static unsigned long dmatable = 0;
348
349 printk(" %s: BM-DMA at 0x%04x-0x%04x", hwif->name, base, base+7);
350 if (check_region(base, 8)) {
351 printk(" -- ERROR, PORTS ALREADY IN USE");
352 } else {
353 request_region(base, 8, "IDE DMA");
354 hwif->dma_base = base;
355 if (!dmatable) {
356 /*
357 * Since we know we are on a PCI bus, we could
358 * actually use __get_free_pages() here instead
359 * of __get_dma_pages() -- no ISA limitations.
360 */
361 dmatable = __get_dma_pages(GFP_KERNEL, 0);
362 }
363 if (dmatable) {
364 hwif->dmatable = (unsigned long *) dmatable;
365 dmatable += (PRD_ENTRIES * PRD_BYTES);
366 outl(virt_to_bus(hwif->dmatable), base + 4);
367 hwif->dmaproc = &triton_dmaproc;
368 }
369 }
370 printk("\n");
371 }
372
373 /*
374 * ide_init_triton() prepares the IDE driver for DMA operation.
375 * This routine is called once, from ide.c during driver initialization,
376 * for each triton chipset which is found (unlikely to be more than one).
377 */
378 void ide_init_triton (byte bus, byte fn)
/* ![[last]](../icons/n_last.png)
*/
379 {
380 int rc = 0, h;
381 int dma_enabled = 0;
382 unsigned short bmiba, pcicmd;
383 unsigned int timings;
384
385 printk("ide: 430FX (Triton) on PCI bus %d function %d\n", bus, fn);
386 /*
387 * See if IDE and BM-DMA features are enabled:
388 */
389 if ((rc = pcibios_read_config_word(bus, fn, 0x04, &pcicmd)))
390 goto quit;
391 if ((pcicmd & 1) == 0) {
392 printk("ide: ports are not enabled (BIOS)\n");
393 goto quit;
394 }
395 if ((pcicmd & 4) == 0) {
396 printk("ide: BM-DMA feature is not enabled (BIOS)\n");
397 } else {
398 /*
399 * Get the bmiba base address
400 */
401 int try_again = 1;
402 do {
403 if ((rc = pcibios_read_config_word(bus, fn, 0x20, &bmiba)))
404 goto quit;
405 bmiba &= 0xfff0; /* extract port base address */
406 if (bmiba) {
407 dma_enabled = 1;
408 } else {
409 printk("ide: BM-DMA base register is invalid (BIOS problem)\n");
410 if (inb(DEFAULT_BMIBA) == 0xff) {
411 printk("ide: setting BM-DMA base register to 0x%04x\n", DEFAULT_BMIBA);
412 if ((rc = pcibios_write_config_word(bus, fn, 0x20, DEFAULT_BMIBA)))
413 goto quit;
414 }
415 }
416 } while (!dma_enabled && try_again--);
417 }
418
419 /*
420 * See if ide port(s) are enabled
421 */
422 if ((rc = pcibios_read_config_dword(bus, fn, 0x40, &timings)))
423 goto quit;
424 if (!(timings & 0x80008000)) {
425 printk("ide: neither port is enabled\n");
426 goto quit;
427 }
428
429 /*
430 * Save the dma_base port addr for each interface
431 */
432 for (h = 0; h < MAX_HWIFS; ++h) {
433 byte s_clks, r_clks;
434 ide_hwif_t *hwif = &ide_hwifs[h];
435 unsigned short time;
436 if (hwif->io_base == 0x1f0) {
437 time = timings & 0xffff;
438 if ((timings & 0x8000) == 0) /* interface enabled? */
439 continue;
440 hwif->chipset = ide_triton;
441 if (dma_enabled)
442 init_triton_dma(hwif, bmiba);
443 } else if (hwif->io_base == 0x170) {
444 time = timings >> 16;
445 if ((timings & 0x8000) == 0) /* interface enabled? */
446 continue;
447 hwif->chipset = ide_triton;
448 if (dma_enabled)
449 init_triton_dma(hwif, bmiba + 8);
450 } else
451 continue;
452 s_clks = ((~time >> 12) & 3) + 2;
453 r_clks = ((~time >> 8) & 3) + 1;
454 printk(" %s timing: (0x%04x) sample_CLKs=%d, recovery_CLKs=%d\n",
455 hwif->name, time, s_clks, r_clks);
456 print_triton_drive_flags (0, time & 0xf);
457 print_triton_drive_flags (1, (time >> 4) & 0xf);
458 }
459
460 quit: if (rc) printk("ide: pcibios access failed - %s\n", pcibios_strerror(rc));
461 }
462
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*/