This source file includes following definitions.
- sparc_dma_pause
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7 #ifndef _ASM_SPARC_DMA_H
8 #define _ASM_SPARC_DMA_H
9
10 #include <linux/kernel.h>
11
12 #include <asm/vac-ops.h>
13 #include <asm/sbus.h>
14 #include <asm/delay.h>
15 #include <asm/oplib.h>
16
17
18
19
20 #define MAX_DMA_CHANNELS 8
21 #define MAX_DMA_ADDRESS (~0UL)
22 #define DMA_MODE_READ 1
23 #define DMA_MODE_WRITE 2
24
25
26 #define SIZE_16MB (16*1024*1024)
27 #define SIZE_64K (64*1024)
28
29
30 struct sparc_dma_registers {
31 volatile unsigned long cond_reg;
32 volatile char * st_addr;
33 volatile unsigned long cnt;
34 volatile unsigned long dma_test;
35 };
36
37
38 enum dvma_rev {
39 dvmarev0,
40 dvmaesc1,
41 dvmarev1,
42 dvmarev2,
43 dvmarev3,
44 dvmarevplus
45 };
46
47 #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
48
49
50 struct Linux_SBus_DMA {
51 struct Linux_SBus_DMA *next;
52 struct linux_sbus_device *SBus_dev;
53 struct sparc_dma_registers *regs;
54
55
56 int node;
57 int running;
58 int allocated;
59
60
61 unsigned long addr;
62 int nbytes;
63 int realbytes;
64
65
66 enum dvma_rev revision;
67 };
68
69 extern struct Linux_SBus_DMA *dma_chain;
70
71
72 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
73 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
74
75
76 extern void dump_dma_regs(struct sparc_dma_registers *);
77 extern unsigned long dvma_init(struct linux_sbus *, unsigned long);
78
79
80
81 #define DMA_DEVICE_ID 0xf0000000
82 #define DMA_VERS0 0x00000000
83 #define DMA_ESCV1 0x40000000
84 #define DMA_VERS1 0x80000000
85 #define DMA_VERS2 0xa0000000
86 #define DMA_VERSPLUS 0x90000000
87
88 #define DMA_HNDL_INTR 0x00000001
89 #define DMA_HNDL_ERROR 0x00000002
90 #define DMA_FIFO_ISDRAIN 0x0000000c
91 #define DMA_INT_ENAB 0x00000010
92 #define DMA_FIFO_INV 0x00000020
93 #define DMA_ACC_SZ_ERR 0x00000040
94 #define DMA_FIFO_STDRAIN 0x00000040
95 #define DMA_RST_SCSI 0x00000080
96 #define DMA_RST_ENET DMA_RST_SCSI
97 #define DMA_ST_WRITE 0x00000100
98 #define DMA_ENABLE 0x00000200
99 #define DMA_PEND_READ 0x00000400
100 #define DMA_BCNT_ENAB 0x00002000
101 #define DMA_TERM_CNTR 0x00004000
102 #define DMA_CSR_DISAB 0x00010000
103 #define DMA_SCSI_DISAB 0x00020000
104 #define DMA_ADD_ENABLE 0x00040000
105 #define DMA_BRST_SZ 0x000c0000
106 #define DMA_ADDR_DISAB 0x00100000
107 #define DMA_2CLKS 0x00200000
108 #define DMA_3CLKS 0x00400000
109 #define DMA_CNTR_DISAB 0x00800000
110 #define DMA_AUTO_NADDR 0x01000000
111 #define DMA_SCSI_ON 0x02000000
112 #define DMA_LOADED_ADDR 0x04000000
113 #define DMA_LOADED_NADDR 0x08000000
114
115
116 #define DMA_BURST1 0x01
117 #define DMA_BURST2 0x02
118 #define DMA_BURST4 0x04
119 #define DMA_BURST8 0x08
120 #define DMA_BURST16 0x10
121 #define DMA_BURST32 0x20
122 #define DMA_BURST64 0x40
123 #define DMA_BURSTBITS 0x7f
124
125
126 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
127
128
129 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
130 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & DMA_HNDL_INTR))
131 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
132 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
133 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
134 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
135 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
136 #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
137 #define DMA_BEGINDMA_W(regs) \
138 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
139 #define DMA_BEGINDMA_R(regs) \
140 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
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145
146
147 #define DMA_IRQ_ENTRY(dma, dregs) do { \
148 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
149 } while (0)
150
151 #define DMA_IRQ_EXIT(dma, dregs) do { \
152 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
153 } while(0)
154
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157
158 extern inline void sparc_dma_pause(struct sparc_dma_registers *regs,
159 unsigned long bit)
160 {
161 int ctr = 50000;
162
163
164 while((regs->cond_reg&bit) && (ctr>0)) {
165 ctr--;
166 __delay(5);
167 }
168
169
170 if(!ctr)
171 panic("DMA timeout");
172 }
173
174
175 #define DMA_RESET(dma) do { \
176 struct sparc_dma_registers *regs = dma->regs; \
177 \
178 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
179 \
180 regs->cond_reg |= (DMA_RST_SCSI); \
181 __delay(400); \
182 regs->cond_reg &= ~(DMA_RST_SCSI); \
183 sparc_dma_enable_interrupts(regs); \
184 \
185 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
186 dma->running = 0; \
187 } while(0)
188
189 #define for_each_dvma(dma) \
190 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
191
192 extern int get_dma_list(char *);
193 extern int request_dma(unsigned int, const char *);
194 extern void free_dma(unsigned int);
195
196 #endif