This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- get_hw_addr
- EISA_signature
- ewrk3_ioctl
- init_module
- cleanup_module
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139 static const char *version = "ewrk3.c:v0.41 96/1/20 davies@wanton.lkg.dec.com\n";
140
141 #include <linux/module.h>
142
143 #include <linux/kernel.h>
144 #include <linux/sched.h>
145 #include <linux/string.h>
146 #include <linux/ptrace.h>
147 #include <linux/errno.h>
148 #include <linux/ioport.h>
149 #include <linux/malloc.h>
150 #include <linux/interrupt.h>
151 #include <linux/delay.h>
152 #include <asm/bitops.h>
153 #include <asm/io.h>
154 #include <asm/dma.h>
155 #include <asm/segment.h>
156
157 #include <linux/netdevice.h>
158 #include <linux/etherdevice.h>
159 #include <linux/skbuff.h>
160
161 #include <linux/time.h>
162 #include <linux/types.h>
163 #include <linux/unistd.h>
164
165 #include "ewrk3.h"
166
167 #ifdef EWRK3_DEBUG
168 static int ewrk3_debug = EWRK3_DEBUG;
169 #else
170 static int ewrk3_debug = 1;
171 #endif
172
173 #define EWRK3_NDA 0xffe0
174
175 #define PROBE_LENGTH 32
176 #define ETH_PROM_SIG 0xAA5500FFUL
177
178 #ifndef EWRK3_SIGNATURE
179 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
180 #define EWRK3_STRLEN 8
181 #endif
182
183 #ifndef EWRK3_RAM_BASE_ADDRESSES
184 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
185 #endif
186
187
188
189
190 #define EWRK3_IO_BASE 0x100
191 #define EWRK3_IOP_INC 0x20
192 #define EWRK3_TOTAL_SIZE 0x20
193
194 #ifndef MAX_NUM_EWRK3S
195 #define MAX_NUM_EWRK3S 21
196 #endif
197
198 #ifndef EWRK3_EISA_IO_PORTS
199 #define EWRK3_EISA_IO_PORTS 0x0c00
200 #endif
201
202 #ifndef MAX_EISA_SLOTS
203 #define MAX_EISA_SLOTS 16
204 #define EISA_SLOT_INC 0x1000
205 #endif
206
207 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
208 #define CRC_POLYNOMIAL_LE 0xedb88320UL
209
210 #define QUEUE_PKT_TIMEOUT (1*HZ)
211
212
213
214
215 #define IO_ONLY 0x00
216 #define SHMEM_2K 0x800
217 #define SHMEM_32K 0x8000
218 #define SHMEM_64K 0x10000
219
220
221
222
223 #define ENABLE_IRQs { \
224 icr |= lp->irq_mask;\
225 outb(icr, EWRK3_ICR); \
226 }
227
228 #define DISABLE_IRQs { \
229 icr = inb(EWRK3_ICR);\
230 icr &= ~lp->irq_mask;\
231 outb(icr, EWRK3_ICR); \
232 }
233
234
235
236
237 #define START_EWRK3 { \
238 csr = inb(EWRK3_CSR);\
239 csr &= ~(CSR_TXD|CSR_RXD);\
240 outb(csr, EWRK3_CSR); \
241 }
242
243 #define STOP_EWRK3 { \
244 csr = (CSR_TXD|CSR_RXD);\
245 outb(csr, EWRK3_CSR); \
246 }
247
248
249
250
251 #define EWRK3_PKT_STAT_SZ 16
252 #define EWRK3_PKT_BIN_SZ 128
253
254
255 struct ewrk3_private {
256 char adapter_name[80];
257 u_long shmem_base;
258 u_long shmem_length;
259 struct enet_statistics stats;
260 struct {
261 u32 bins[EWRK3_PKT_STAT_SZ];
262 u32 unicast;
263 u32 multicast;
264 u32 broadcast;
265 u32 excessive_collisions;
266 u32 tx_underruns;
267 u32 excessive_underruns;
268 } pktStats;
269 u_char irq_mask;
270 u_char mPage;
271 u_char lemac;
272 u_char hard_strapped;
273 u_char lock;
274 u_char txc;
275 u_char *mctbl;
276 };
277
278
279
280
281 #define FORCE_2K_MODE { \
282 shmem_length = SHMEM_2K;\
283 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
284 }
285
286
287
288
289 static int ewrk3_open(struct device *dev);
290 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
291 static void ewrk3_interrupt(int irq, void *dev_id, struct pt_regs *regs);
292 static int ewrk3_close(struct device *dev);
293 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
294 static void set_multicast_list(struct device *dev);
295 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
296
297
298
299
300 static int ewrk3_hw_init(struct device *dev, u_long iobase);
301 static void ewrk3_init(struct device *dev);
302 static int ewrk3_rx(struct device *dev);
303 static int ewrk3_tx(struct device *dev);
304
305 static void EthwrkSignature(char * name, char *eeprom_image);
306 static int DevicePresent(u_long iobase);
307 static void SetMulticastFilter(struct device *dev);
308 static int EISA_signature(char *name, s32 eisa_id);
309
310 static int Read_EEPROM(u_long iobase, u_char eaddr);
311 static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
312 static u_char get_hw_addr (struct device *dev, u_char *eeprom_image, char chipType);
313
314 static void isa_probe(struct device *dev, u_long iobase);
315 static void eisa_probe(struct device *dev, u_long iobase);
316 static struct device *alloc_device(struct device *dev, u_long iobase);
317
318
319 #ifdef MODULE
320 int init_module(void);
321 void cleanup_module(void);
322 static int autoprobed = 1, loading_module = 1;
323
324 # else
325 static u_char irq[] = {5,0,10,3,11,9,15,12};
326 static int autoprobed = 0, loading_module = 0;
327
328 #endif
329
330 static char name[EWRK3_STRLEN + 1];
331 static int num_ewrk3s = 0, num_eth = 0;
332
333
334
335
336 #define INIT_EWRK3 {\
337 outb(EEPROM_INIT, EWRK3_IOPR);\
338 udelay(1000);\
339 }
340
341
342
343
344 int ewrk3_probe(struct device *dev)
345 {
346 int tmp = num_ewrk3s, status = -ENODEV;
347 u_long iobase = dev->base_addr;
348
349 if ((iobase == 0) && loading_module){
350 printk("Autoprobing is not supported when loading a module based driver.\n");
351 status = -EIO;
352 } else {
353
354 isa_probe(dev, iobase);
355 eisa_probe(dev, iobase);
356
357 if ((tmp == num_ewrk3s) && (iobase != 0) && loading_module) {
358 printk("%s: ewrk3_probe() cannot find device at 0x%04lx.\n", dev->name,
359 iobase);
360 }
361
362
363
364
365
366 for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
367
368 if (dev->priv) status = 0;
369 if (iobase == 0) autoprobed = 1;
370 }
371
372 return status;
373 }
374
375 static int
376 ewrk3_hw_init(struct device *dev, u_long iobase)
377 {
378 struct ewrk3_private *lp;
379 int i, status=0;
380 u_long mem_start, shmem_length;
381 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
382 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
383
384
385
386
387
388 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
389 INIT_EWRK3;
390
391 nicsr = inb(EWRK3_CSR);
392
393 icr = inb(EWRK3_ICR);
394 icr &= 0x70;
395 outb(icr, EWRK3_ICR);
396
397 if (nicsr == (CSR_TXD|CSR_RXD)) {
398
399
400 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
401 union {
402 short val;
403 char c[2];
404 } tmp;
405
406 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
407 eeprom_image[i] = tmp.c[0];
408 eeprom_image[i+1] = tmp.c[1];
409 chksum += eeprom_image[i] + eeprom_image[i+1];
410 }
411
412 if (chksum != 0) {
413 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
414 status = -ENXIO;
415 } else {
416 EthwrkSignature(name, eeprom_image);
417 if (*name != '\0') {
418 dev->base_addr = iobase;
419
420 if (iobase > 0x400) {
421 outb(eisa_cr, EISA_CR);
422 }
423
424 lemac = eeprom_image[EEPROM_CHIPVER];
425 cmr = inb(EWRK3_CMR);
426
427 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
428 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
429 printk("%s: %s at %#4lx", dev->name, name, iobase);
430 hard_strapped = 1;
431 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
432
433 printk("%s: %s at %#4lx (EISA slot %ld)",
434 dev->name, name, iobase, ((iobase>>12)&0x0f));
435 } else {
436 printk("%s: %s at %#4lx", dev->name, name, iobase);
437 }
438
439 if (!status) {
440 printk(", h/w address ");
441 if (lemac!=LeMAC2) DevicePresent(iobase);
442 status = get_hw_addr(dev, eeprom_image, lemac);
443 for (i = 0; i < ETH_ALEN - 1; i++) {
444 printk("%2.2x:", dev->dev_addr[i]);
445 }
446 printk("%2.2x,\n", dev->dev_addr[i]);
447
448 if (status) {
449 printk(" which has an EEPROM CRC error.\n");
450 status = -ENXIO;
451 } else {
452 if (lemac == LeMAC2) {
453 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
454 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= CMR_RA;
455 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= CMR_WB;
456 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= CMR_POLARITY;
457 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= CMR_LINK;
458 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= CMR_0WS;
459 }
460 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= CMR_DRAM;
461 outb(cmr, EWRK3_CMR);
462
463 cr = inb(EWRK3_CR);
464 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
465 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
466 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
467 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
468 outb(cr, EWRK3_CR);
469
470
471
472
473
474 mem_start = inb(EWRK3_MBR);
475 shmem_length = 0;
476 if (mem_start != 0) {
477 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
478 mem_start *= SHMEM_64K;
479 shmem_length = SHMEM_64K;
480 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
481 mem_start *= SHMEM_32K;
482 shmem_length = SHMEM_32K;
483 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
484 mem_start = mem_start * SHMEM_2K + 0x80000;
485 shmem_length = SHMEM_2K;
486 } else {
487 status = -ENXIO;
488 }
489 }
490
491
492
493
494
495
496
497 if (!status) {
498 if (hard_strapped) {
499 printk(" is hard strapped.\n");
500 } else if (mem_start) {
501 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
502 printk(" at 0x%.5lx", mem_start);
503 } else {
504 printk(" is in I/O only mode");
505 }
506
507
508 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
509 GFP_KERNEL);
510 if (dev->priv == NULL) {
511 return -ENOMEM;
512 }
513 lp = (struct ewrk3_private *)dev->priv;
514 memset(dev->priv, 0, sizeof(struct ewrk3_private));
515 lp->shmem_base = mem_start;
516 lp->shmem_length = shmem_length;
517 lp->lemac = lemac;
518 lp->hard_strapped = hard_strapped;
519
520 lp->mPage = 64;
521 if (cmr & CMR_DRAM) lp->mPage <<= 1 ;
522
523 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
524 request_region(iobase, EWRK3_TOTAL_SIZE, lp->adapter_name);
525
526 lp->irq_mask = ICR_TNEM|ICR_TXDM|ICR_RNEM|ICR_RXDM;
527
528 if (!hard_strapped) {
529
530
531
532 icr |= ICR_IE;
533 outb(icr, EWRK3_ICR);
534
535
536 dev->dma = 0;
537
538
539
540 if (dev->irq < 2) {
541 #ifndef MODULE
542 u_char irqnum;
543
544 autoirq_setup(0);
545
546
547
548
549 icr |=ICR_TNEM;
550 outb(1,EWRK3_TDQ);
551 outb(icr, EWRK3_ICR);
552
553 irqnum = irq[((icr & IRQ_SEL) >> 4)];
554
555 dev->irq = autoirq_report(1);
556 if ((dev->irq) && (irqnum == dev->irq)) {
557 printk(" and uses IRQ%d.\n", dev->irq);
558 } else {
559 if (!dev->irq) {
560 printk(" and failed to detect IRQ line.\n");
561 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
562 printk(" and an illegal IRQ line detected.\n");
563 } else {
564 printk(", but incorrect IRQ line detected.\n");
565 }
566 status = -ENXIO;
567 }
568
569 DISABLE_IRQs;
570
571 #endif
572 } else {
573 printk(" and requires IRQ%d.\n", dev->irq);
574 }
575 }
576 if (status) release_region(iobase, EWRK3_TOTAL_SIZE);
577 } else {
578 status = -ENXIO;
579 }
580 }
581 }
582 } else {
583 status = -ENXIO;
584 }
585 }
586
587 if (!status) {
588 if (ewrk3_debug > 0) {
589 printk(version);
590 }
591
592
593 dev->open = &ewrk3_open;
594 dev->hard_start_xmit = &ewrk3_queue_pkt;
595 dev->stop = &ewrk3_close;
596 dev->get_stats = &ewrk3_get_stats;
597 dev->set_multicast_list = &set_multicast_list;
598 dev->do_ioctl = &ewrk3_ioctl;
599
600 dev->mem_start = 0;
601
602
603 ether_setup(dev);
604 }
605 } else {
606 status = -ENXIO;
607 }
608
609 return status;
610 }
611
612
613 static int
614 ewrk3_open(struct device *dev)
615 {
616 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
617 u_long iobase = dev->base_addr;
618 int i, status = 0;
619 u_char icr, csr;
620
621
622
623
624 STOP_EWRK3;
625
626 if (!lp->hard_strapped) {
627 irq2dev_map[dev->irq] = dev;
628
629 if (request_irq(dev->irq, (void *)ewrk3_interrupt, 0, "ewrk3", NULL)) {
630 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
631 status = -EAGAIN;
632 } else {
633
634
635
636
637 ewrk3_init(dev);
638
639 if (ewrk3_debug > 1){
640 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
641 printk(" physical address: ");
642 for (i=0;i<5;i++){
643 printk("%2.2x:",(u_char)dev->dev_addr[i]);
644 }
645 printk("%2.2x\n",(u_char)dev->dev_addr[i]);
646 if (lp->shmem_length == 0) {
647 printk(" no shared memory, I/O only mode\n");
648 } else {
649 printk(" start of shared memory: 0x%08lx\n",lp->shmem_base);
650 printk(" window length: 0x%04lx\n",lp->shmem_length);
651 }
652 printk(" # of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
653 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
654 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
655 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
656 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
657 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
658 }
659
660 dev->tbusy = 0;
661 dev->start = 1;
662 dev->interrupt = UNMASK_INTERRUPTS;
663
664
665
666
667 icr = inb(EWRK3_ICR);
668 ENABLE_IRQs;
669
670 }
671 } else {
672 dev->start = 0;
673 dev->tbusy = 1;
674 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
675 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
676 }
677
678 MOD_INC_USE_COUNT;
679
680 return status;
681 }
682
683
684
685
686 static void
687 ewrk3_init(struct device *dev)
688 {
689 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
690 u_char csr, page;
691 u_long iobase = dev->base_addr;
692
693
694
695
696 set_multicast_list(dev);
697
698
699
700
701 while (inb(EWRK3_TQ));
702 while (inb(EWRK3_TDQ));
703 while (inb(EWRK3_RQ));
704 while (inb(EWRK3_FMQ));
705
706
707
708
709 for (page=1;page<lp->mPage;page++) {
710 outb(page, EWRK3_FMQ);
711 }
712
713 lp->lock = 0;
714
715 START_EWRK3;
716 }
717
718
719
720
721 static int
722 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
723 {
724 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
725 u_long iobase = dev->base_addr;
726 int status = 0;
727 u_char icr, csr;
728
729
730 if (dev->tbusy || lp->lock) {
731 int tickssofar = jiffies - dev->trans_start;
732 if (tickssofar < QUEUE_PKT_TIMEOUT) {
733 status = -1;
734 } else if (!lp->hard_strapped) {
735 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
736 dev->name, inb(EWRK3_CSR));
737
738
739
740
741 DISABLE_IRQs;
742
743
744
745
746 STOP_EWRK3;
747
748 ewrk3_init(dev);
749
750
751
752
753 ENABLE_IRQs;
754
755 dev->tbusy=0;
756 dev->trans_start = jiffies;
757 }
758 } else if (skb == NULL) {
759 dev_tint(dev);
760 } else if (skb->len > 0) {
761
762
763
764
765
766 if (set_bit(0, (void*)&dev->tbusy) != 0)
767 printk("%s: Transmitter access conflict.\n", dev->name);
768
769 DISABLE_IRQs;
770
771
772
773
774 if (inb(EWRK3_FMQC) > 0) {
775 u_long buf = 0;
776 u_char page;
777
778 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
779
780
781
782 while (set_bit(0, (void *)&lp->lock) != 0);
783 if (lp->shmem_length == IO_ONLY) {
784 outb(page, EWRK3_IOPR);
785 } else if (lp->shmem_length == SHMEM_2K) {
786 buf = lp->shmem_base;
787 outb(page, EWRK3_MPR);
788 } else if (lp->shmem_length == SHMEM_32K) {
789 buf = ((((short)page << 11) & 0x7800) + lp->shmem_base);
790 outb((page >> 4), EWRK3_MPR);
791 } else if (lp->shmem_length == SHMEM_64K) {
792 buf = ((((short)page << 11) & 0xf800) + lp->shmem_base);
793 outb((page >> 5), EWRK3_MPR);
794 } else {
795 status = -1;
796 printk("%s: Oops - your private data area is hosed!\n",dev->name);
797 }
798
799 if (!status) {
800
801
802
803
804
805
806 if (lp->shmem_length == IO_ONLY) {
807 int i;
808 u_char *p = skb->data;
809
810 outb((char)(TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
811 outb((char)(skb->len & 0xff), EWRK3_DATA);
812 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
813 outb((char)0x04, EWRK3_DATA);
814 for (i=0; i<skb->len; i++) {
815 outb(*p++, EWRK3_DATA);
816 }
817 outb(page, EWRK3_TQ);
818 } else {
819 writeb((char)(TCR_QMODE|TCR_PAD|TCR_IFC), (char *)buf);
820 buf+=1;
821 writeb((char)(skb->len & 0xff), (char *)buf);
822 buf+=1;
823 if (lp->txc) {
824 writeb((char)(((skb->len >> 8) & 0xff) | XCT), (char *)buf);
825 buf+=1;
826 writeb(0x04, (char *)buf);
827 buf+=1;
828 writeb(0x00, (char *)(buf + skb->len));
829 memcpy_toio(buf, skb->data, PRELOAD);
830 outb(page, EWRK3_TQ);
831 memcpy_toio(buf+PRELOAD, skb->data+PRELOAD, skb->len-PRELOAD);
832 writeb(0xff, (char *)(buf + skb->len));
833 } else {
834 writeb((char)((skb->len >> 8) & 0xff), (char *)buf);
835 buf+=1;
836 writeb(0x04, (char *)buf);
837 buf+=1;
838 memcpy_toio((char *)buf, skb->data, skb->len);
839 outb(page, EWRK3_TQ);
840 }
841 }
842
843 dev->trans_start = jiffies;
844 dev_kfree_skb (skb, FREE_WRITE);
845
846 } else {
847 outb(page, EWRK3_FMQ);
848 }
849 lp->lock = 0;
850 } else {
851 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
852 (u_char) page);
853 }
854 } else {
855 printk("ewrk3_queue_pkt(): No free resources...\n");
856 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
857 }
858
859
860 if (inb(EWRK3_FMQC) > 0) {
861 dev->tbusy = 0;
862 }
863
864 ENABLE_IRQs;
865 }
866
867 return status;
868 }
869
870
871
872
873 static void
874 ewrk3_interrupt(int irq, void *dev_id, struct pt_regs * regs)
875 {
876 struct device *dev = (struct device *)(irq2dev_map[irq]);
877 struct ewrk3_private *lp;
878 u_long iobase;
879 u_char icr, cr, csr;
880
881 if (dev == NULL) {
882 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
883 } else {
884 lp = (struct ewrk3_private *)dev->priv;
885 iobase = dev->base_addr;
886
887 if (dev->interrupt)
888 printk("%s: Re-entering the interrupt handler.\n", dev->name);
889
890 dev->interrupt = MASK_INTERRUPTS;
891
892
893 csr = inb(EWRK3_CSR);
894
895
896
897
898 DISABLE_IRQs;
899
900 cr = inb(EWRK3_CR);
901 cr |= CR_LED;
902 outb(cr, EWRK3_CR);
903
904 if (csr & CSR_RNE)
905 ewrk3_rx(dev);
906
907 if (csr & CSR_TNE)
908 ewrk3_tx(dev);
909
910
911
912
913
914
915
916 if (inb(EWRK3_FMQC)) {
917 lp->irq_mask |= ICR_TXDM|ICR_RXDM;
918 csr &= ~(CSR_TXD|CSR_RXD);
919 outb(csr, EWRK3_CSR);
920 dev->tbusy = 0;
921 mark_bh(NET_BH);
922 } else {
923 lp->irq_mask &= ~(ICR_TXDM|ICR_RXDM);
924 }
925
926
927 cr &= ~CR_LED;
928 outb(cr, EWRK3_CR);
929
930 dev->interrupt = UNMASK_INTERRUPTS;
931 ENABLE_IRQs;
932 }
933
934 return;
935 }
936
937 static int
938 ewrk3_rx(struct device *dev)
939 {
940 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
941 u_long iobase = dev->base_addr;
942 int i, status = 0;
943 u_char page, tmpPage = 0, tmpLock = 0;
944 u_long buf = 0;
945
946 while (inb(EWRK3_RQC) && !status) {
947 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
948
949
950
951
952 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
953 if (lp->shmem_length == IO_ONLY) {
954 tmpPage = inb(EWRK3_IOPR);
955 } else {
956 tmpPage = inb(EWRK3_MPR);
957 }
958 }
959
960
961
962
963 if (lp->shmem_length == IO_ONLY) {
964 outb(page, EWRK3_IOPR);
965 } else if (lp->shmem_length == SHMEM_2K) {
966 buf = lp->shmem_base;
967 outb(page, EWRK3_MPR);
968 } else if (lp->shmem_length == SHMEM_32K) {
969 buf = ((((short)page << 11) & 0x7800) + lp->shmem_base);
970 outb((page >> 4), EWRK3_MPR);
971 } else if (lp->shmem_length == SHMEM_64K) {
972 buf = ((((short)page << 11) & 0xf800) + lp->shmem_base);
973 outb((page >> 5), EWRK3_MPR);
974 } else {
975 status = -1;
976 printk("%s: Oops - your private data area is hosed!\n",dev->name);
977 }
978
979 if (!status) {
980 char rx_status;
981 int pkt_len;
982
983 if (lp->shmem_length == IO_ONLY) {
984 rx_status = inb(EWRK3_DATA);
985 pkt_len = inb(EWRK3_DATA);
986 pkt_len |= ((u_short)inb(EWRK3_DATA) << 8);
987 } else {
988 rx_status = readb(buf);
989 buf+=1;
990 pkt_len = readw(buf);
991 buf+=3;
992 }
993
994 if (!(rx_status & R_ROK)) {
995 lp->stats.rx_errors++;
996 if (rx_status & R_DBE) lp->stats.rx_frame_errors++;
997 if (rx_status & R_CRC) lp->stats.rx_crc_errors++;
998 if (rx_status & R_PLL) lp->stats.rx_fifo_errors++;
999 } else {
1000 struct sk_buff *skb;
1001
1002 if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1003 unsigned char *p;
1004 skb->dev = dev;
1005 skb_reserve(skb,2);
1006 p = skb_put(skb,pkt_len);
1007
1008 if (lp->shmem_length == IO_ONLY) {
1009 *p = inb(EWRK3_DATA);
1010 for (i=0; i<pkt_len; i++) {
1011 *p++ = inb(EWRK3_DATA);
1012 }
1013 } else {
1014 memcpy_fromio(p, buf, pkt_len);
1015 }
1016
1017
1018
1019
1020
1021 skb->protocol=eth_type_trans(skb,dev);
1022 netif_rx(skb);
1023
1024
1025
1026
1027 lp->stats.rx_packets++;
1028 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1029 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1030 lp->pktStats.bins[i]++;
1031 i = EWRK3_PKT_STAT_SZ;
1032 }
1033 }
1034 p = skb->data;
1035 if (p[0] & 0x01) {
1036 if ((*(s32 *)&p[0] == -1) && (*(s16 *)&p[4] == -1)) {
1037 lp->pktStats.broadcast++;
1038 } else {
1039 lp->pktStats.multicast++;
1040 }
1041 } else if ((*(s32 *)&p[0] == *(s32 *)&dev->dev_addr[0]) &&
1042 (*(s16 *)&p[4] == *(s16 *)&dev->dev_addr[4])) {
1043 lp->pktStats.unicast++;
1044 }
1045
1046 lp->pktStats.bins[0]++;
1047 if (lp->pktStats.bins[0] == 0) {
1048 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1049 }
1050 } else {
1051 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1052 lp->stats.rx_dropped++;
1053 break;
1054 }
1055 }
1056 }
1057
1058
1059
1060 outb(page, EWRK3_FMQ);
1061
1062 if (tmpLock) {
1063 if (lp->shmem_length == IO_ONLY) {
1064 outb(tmpPage, EWRK3_IOPR);
1065 } else {
1066 outb(tmpPage, EWRK3_MPR);
1067 }
1068 }
1069 lp->lock = 0;
1070 } else {
1071 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1072 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1073 }
1074 }
1075 return status;
1076 }
1077
1078
1079
1080
1081 static int
1082 ewrk3_tx(struct device *dev)
1083 {
1084 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1085 u_long iobase = dev->base_addr;
1086 u_char tx_status;
1087
1088 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1089 if (tx_status & T_VSTS) {
1090 if (tx_status & T_TXE) {
1091 lp->stats.tx_errors++;
1092 if (tx_status & T_NCL) lp->stats.tx_carrier_errors++;
1093 if (tx_status & T_LCL) lp->stats.tx_window_errors++;
1094 if (tx_status & T_CTU) {
1095 if ((tx_status & T_COLL) ^ T_XUR) {
1096 lp->pktStats.tx_underruns++;
1097 } else {
1098 lp->pktStats.excessive_underruns++;
1099 }
1100 } else if (tx_status & T_COLL) {
1101 if ((tx_status & T_COLL) ^ T_XCOLL) {
1102 lp->stats.collisions++;
1103 } else {
1104 lp->pktStats.excessive_collisions++;
1105 }
1106 }
1107 } else {
1108 lp->stats.tx_packets++;
1109 }
1110 }
1111 }
1112
1113 return 0;
1114 }
1115
1116 static int
1117 ewrk3_close(struct device *dev)
1118 {
1119 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1120 u_long iobase = dev->base_addr;
1121 u_char icr, csr;
1122
1123 dev->start = 0;
1124 dev->tbusy = 1;
1125
1126 if (ewrk3_debug > 1) {
1127 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1128 dev->name, inb(EWRK3_CSR));
1129 }
1130
1131
1132
1133
1134 DISABLE_IRQs;
1135
1136 STOP_EWRK3;
1137
1138
1139
1140
1141
1142
1143
1144 while (inb(EWRK3_TQ));
1145 while (inb(EWRK3_TDQ));
1146 while (inb(EWRK3_RQ));
1147
1148 if (!lp->hard_strapped) {
1149 free_irq(dev->irq, NULL);
1150
1151 irq2dev_map[dev->irq] = 0;
1152 }
1153
1154 MOD_DEC_USE_COUNT;
1155
1156 return 0;
1157 }
1158
1159 static struct enet_statistics *
1160 ewrk3_get_stats(struct device *dev)
1161 {
1162 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1163
1164
1165
1166 return &lp->stats;
1167 }
1168
1169
1170
1171
1172 static void
1173 set_multicast_list(struct device *dev)
1174 {
1175 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1176 u_long iobase = dev->base_addr;
1177 u_char csr;
1178
1179 if (irq2dev_map[dev->irq] != NULL) {
1180 csr = inb(EWRK3_CSR);
1181
1182 if (lp->shmem_length == IO_ONLY) {
1183 lp->mctbl = (char *) PAGE0_HTE;
1184 } else {
1185 lp->mctbl = (char *)(lp->shmem_base + PAGE0_HTE);
1186 }
1187
1188 csr &= ~(CSR_PME | CSR_MCE);
1189 if (dev->flags & IFF_PROMISC) {
1190 csr |= CSR_PME;
1191 outb(csr, EWRK3_CSR);
1192 } else {
1193 SetMulticastFilter(dev);
1194 csr |= CSR_MCE;
1195 outb(csr, EWRK3_CSR);
1196 }
1197 }
1198 }
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208 static void SetMulticastFilter(struct device *dev)
1209 {
1210 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1211 struct dev_mc_list *dmi=dev->mc_list;
1212 u_long iobase = dev->base_addr;
1213 int i;
1214 char *addrs, j, bit, byte;
1215 short *p = (short *) lp->mctbl;
1216 u16 hashcode;
1217 s32 crc, poly = CRC_POLYNOMIAL_LE;
1218
1219 while (set_bit(0, (void *)&lp->lock) != 0);
1220
1221 if (lp->shmem_length == IO_ONLY) {
1222 outb(0, EWRK3_IOPR);
1223 outw(EEPROM_OFFSET(lp->mctbl), EWRK3_PIR1);
1224 } else {
1225 outb(0, EWRK3_MPR);
1226 }
1227
1228 if (dev->flags & IFF_ALLMULTI) {
1229 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1230 if (lp->shmem_length == IO_ONLY) {
1231 outb(0xff, EWRK3_DATA);
1232 } else {
1233 writew(0xffff, p);
1234 p++; i++;
1235 }
1236 }
1237 } else {
1238
1239 if (lp->shmem_length == IO_ONLY) {
1240 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++) {
1241 outb(0x00, EWRK3_DATA);
1242 }
1243 outb(0x80, EWRK3_DATA); i++;
1244 for (; i<(HASH_TABLE_LEN >> 3); i++) {
1245 outb(0x00, EWRK3_DATA);
1246 }
1247 } else {
1248 memset_io(lp->mctbl, 0, (HASH_TABLE_LEN >> 3));
1249 writeb(0x80, (char *)(lp->mctbl + (HASH_TABLE_LEN >> 4) - 1));
1250 }
1251
1252
1253 for (i=0;i<dev->mc_count;i++) {
1254 addrs=dmi->dmi_addr;
1255 dmi=dmi->next;
1256 if ((*addrs & 0x01) == 1) {
1257 crc = 0xffffffff;
1258 for (byte=0;byte<ETH_ALEN;byte++) {
1259
1260 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1261 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1262 }
1263 }
1264 hashcode = crc & ((1 << 9) - 1);
1265
1266 byte = hashcode >> 3;
1267 bit = 1 << (hashcode & 0x07);
1268
1269 if (lp->shmem_length == IO_ONLY) {
1270 u_char tmp;
1271
1272 outw((short)((long)lp->mctbl) + byte, EWRK3_PIR1);
1273 tmp = inb(EWRK3_DATA);
1274 tmp |= bit;
1275 outw((short)((long)lp->mctbl) + byte, EWRK3_PIR1);
1276 outb(tmp, EWRK3_DATA);
1277 } else {
1278 writeb(readb(lp->mctbl + byte) | bit, lp->mctbl + byte);
1279 }
1280 }
1281 }
1282 }
1283
1284 lp->lock = 0;
1285
1286 return;
1287 }
1288
1289
1290
1291
1292 static void isa_probe(struct device *dev, u_long ioaddr)
1293 {
1294 int i = num_ewrk3s, maxSlots;
1295 u_long iobase;
1296
1297 if (!ioaddr && autoprobed) return ;
1298 if (ioaddr >= 0x400) return;
1299
1300 if (ioaddr == 0) {
1301 iobase = EWRK3_IO_BASE;
1302 maxSlots = 24;
1303 } else {
1304 iobase = ioaddr;
1305 maxSlots = i + 1;
1306 }
1307
1308 for (; (i<maxSlots) && (dev!=NULL);iobase+=EWRK3_IOP_INC, i++) {
1309 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1310 if (DevicePresent(iobase) == 0) {
1311 if ((dev = alloc_device(dev, iobase)) != NULL) {
1312 if (ewrk3_hw_init(dev, iobase) == 0) {
1313 num_ewrk3s++;
1314 }
1315 num_eth++;
1316 }
1317 }
1318 } else if (autoprobed) {
1319 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1320 }
1321 }
1322
1323 return;
1324 }
1325
1326
1327
1328
1329
1330 static void eisa_probe(struct device *dev, u_long ioaddr)
1331 {
1332 int i, maxSlots;
1333 u_long iobase;
1334 char name[EWRK3_STRLEN];
1335
1336 if (!ioaddr && autoprobed) return ;
1337 if (ioaddr < 0x1000) return;
1338
1339 if (ioaddr == 0) {
1340 iobase = EISA_SLOT_INC;
1341 i = 1;
1342 maxSlots = MAX_EISA_SLOTS;
1343 } else {
1344 iobase = ioaddr;
1345 i = (ioaddr >> 12);
1346 maxSlots = i + 1;
1347 }
1348
1349 for (i=1; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
1350 if (EISA_signature(name, EISA_ID) == 0) {
1351 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1352 if (DevicePresent(iobase) == 0) {
1353 if ((dev = alloc_device(dev, iobase)) != NULL) {
1354 if (ewrk3_hw_init(dev, iobase) == 0) {
1355 num_ewrk3s++;
1356 }
1357 num_eth++;
1358 }
1359 }
1360 } else if (autoprobed) {
1361 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1362 }
1363 }
1364 }
1365
1366 return;
1367 }
1368
1369
1370
1371
1372
1373 static struct device *alloc_device(struct device *dev, u_long iobase)
1374 {
1375 int addAutoProbe = 0;
1376 struct device *tmp = NULL, *ret;
1377 int (*init)(struct device *) = NULL;
1378
1379
1380
1381
1382 if (!loading_module) {
1383 while (dev->next != NULL) {
1384 if ((dev->base_addr == EWRK3_NDA) || (dev->base_addr == 0)) break;
1385 dev = dev->next;
1386 num_eth++;
1387 }
1388
1389
1390
1391
1392
1393 if ((dev->base_addr == 0) && (num_ewrk3s > 0)) {
1394 addAutoProbe++;
1395 tmp = dev->next;
1396 init = dev->init;
1397 }
1398
1399
1400
1401
1402
1403 if ((dev->next == NULL) &&
1404 !((dev->base_addr == EWRK3_NDA) || (dev->base_addr == 0))){
1405 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1406 GFP_KERNEL);
1407
1408 dev = dev->next;
1409 if (dev == NULL) {
1410 printk("eth%d: Device not initialised, insufficient memory\n",
1411 num_eth);
1412 } else {
1413
1414
1415
1416
1417
1418 dev->name = (char *)(dev + sizeof(struct device));
1419 if (num_eth > 9999) {
1420 sprintf(dev->name,"eth????");
1421 } else {
1422 sprintf(dev->name,"eth%d", num_eth);
1423 }
1424 dev->base_addr = iobase;
1425 dev->next = NULL;
1426 dev->init = &ewrk3_probe;
1427 num_ewrk3s++;
1428 }
1429 }
1430 ret = dev;
1431
1432
1433
1434
1435
1436 if (ret != NULL) {
1437 if (addAutoProbe) {
1438 for (;(tmp->next!=NULL) && (tmp->base_addr!=EWRK3_NDA); tmp=tmp->next);
1439
1440
1441
1442
1443
1444 if ((tmp->next == NULL) && !(tmp->base_addr == EWRK3_NDA)) {
1445 tmp->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1446 GFP_KERNEL);
1447 tmp = tmp->next;
1448 if (tmp == NULL) {
1449 printk("%s: Insufficient memory to extend the device list.\n",
1450 dev->name);
1451 } else {
1452
1453
1454
1455
1456
1457 tmp->name = (char *)(tmp + sizeof(struct device));
1458 if (num_eth > 9999) {
1459 sprintf(tmp->name,"eth????");
1460 } else {
1461 sprintf(tmp->name,"eth%d", num_eth);
1462 }
1463 tmp->base_addr = 0;
1464 tmp->next = NULL;
1465 tmp->init = init;
1466 }
1467 } else {
1468 tmp->base_addr = 0;
1469 }
1470 }
1471 }
1472 } else {
1473 ret = dev;
1474 }
1475
1476 return ret;
1477 }
1478
1479
1480
1481
1482 static int Read_EEPROM(u_long iobase, u_char eaddr)
1483 {
1484 int i;
1485
1486 outb((eaddr & 0x3f), EWRK3_PIR1);
1487 outb(EEPROM_RD, EWRK3_IOPR);
1488 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1489
1490 return inw(EWRK3_EPROM1);
1491 }
1492
1493
1494
1495
1496 static int Write_EEPROM(short data, u_long iobase, u_char eaddr)
1497 {
1498 int i;
1499
1500 outb(EEPROM_WR_EN, EWRK3_IOPR);
1501 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1502 outw(data, EWRK3_EPROM1);
1503 outb((eaddr & 0x3f), EWRK3_PIR1);
1504 outb(EEPROM_WR, EWRK3_IOPR);
1505 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1506 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1507 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1508
1509 return 0;
1510 }
1511
1512
1513
1514
1515 static void EthwrkSignature(char *name, char *eeprom_image)
1516 {
1517 u_long i,j,k;
1518 char *signatures[] = EWRK3_SIGNATURE;
1519
1520 strcpy(name, "");
1521 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1522 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1523 if (signatures[i][k] == eeprom_image[j]) {
1524 k++;
1525 } else {
1526 k=0;
1527 }
1528 }
1529 if (k == strlen(signatures[i])) {
1530 for (k=0; k<EWRK3_STRLEN; k++) {
1531 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1532 name[EWRK3_STRLEN] = '\0';
1533 }
1534 }
1535 }
1536
1537 return;
1538 }
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552 static int DevicePresent(u_long iobase)
1553 {
1554 union {
1555 struct {
1556 u32 a;
1557 u32 b;
1558 } llsig;
1559 char Sig[sizeof(u32) << 1];
1560 } dev;
1561 short sigLength;
1562 char data;
1563 int i, j, status = 0;
1564
1565 dev.llsig.a = ETH_PROM_SIG;
1566 dev.llsig.b = ETH_PROM_SIG;
1567 sigLength = sizeof(u32) << 1;
1568
1569 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1570 data = inb(EWRK3_APROM);
1571 if (dev.Sig[j] == data) {
1572 j++;
1573 } else {
1574 if (data == dev.Sig[0]) {
1575 j=1;
1576 } else {
1577 j=0;
1578 }
1579 }
1580 }
1581
1582 if (j!=sigLength) {
1583 status = -ENODEV;
1584 }
1585
1586 return status;
1587 }
1588
1589 static u_char get_hw_addr(struct device *dev, u_char *eeprom_image, char chipType)
1590 {
1591 int i, j, k;
1592 u_short chksum;
1593 u_char crc, lfsr, sd, status = 0;
1594 u_long iobase = dev->base_addr;
1595 u16 tmp;
1596
1597 if (chipType == LeMAC2) {
1598 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1599 sd = dev->dev_addr[j] = eeprom_image[EEPROM_PADDR0 + j];
1600 outb(dev->dev_addr[j], EWRK3_PAR0 + j);
1601 for (k=0; k<8; k++, sd >>= 1) {
1602 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1603 crc = (crc >> 1) + lfsr;
1604 }
1605 }
1606 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1607 } else {
1608 for (i=0,k=0;i<ETH_ALEN;) {
1609 k <<= 1 ;
1610 if (k > 0xffff) k-=0xffff;
1611
1612 k += (u_char) (tmp = inb(EWRK3_APROM));
1613 dev->dev_addr[i] = (u_char) tmp;
1614 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1615 i++;
1616 k += (u_short) ((tmp = inb(EWRK3_APROM)) << 8);
1617 dev->dev_addr[i] = (u_char) tmp;
1618 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1619 i++;
1620
1621 if (k > 0xffff) k-=0xffff;
1622 }
1623 if (k == 0xffff) k=0;
1624 chksum = inb(EWRK3_APROM);
1625 chksum |= (inb(EWRK3_APROM)<<8);
1626 if (k != chksum) status = -1;
1627 }
1628
1629 return status;
1630 }
1631
1632
1633
1634
1635 static int EISA_signature(char *name, s32 eisa_id)
1636 {
1637 u_long i;
1638 char *signatures[] = EWRK3_SIGNATURE;
1639 char ManCode[EWRK3_STRLEN];
1640 union {
1641 s32 ID;
1642 char Id[4];
1643 } Eisa;
1644 int status = 0;
1645
1646 *name = '\0';
1647 for (i=0; i<4; i++) {
1648 Eisa.Id[i] = inb(eisa_id + i);
1649 }
1650
1651 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
1652 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
1653 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
1654 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
1655 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
1656 ManCode[5]='\0';
1657
1658 for (i=0;(*signatures[i] != '\0') && (*name == '\0');i++) {
1659 if (strstr(ManCode, signatures[i]) != NULL) {
1660 strcpy(name,ManCode);
1661 status = 1;
1662 }
1663 }
1664
1665 return status;
1666 }
1667
1668
1669
1670
1671
1672 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1673 {
1674 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1675 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1676 u_long iobase = dev->base_addr;
1677 int i, j, status = 0;
1678 u_char csr;
1679 union {
1680 u_char addr[HASH_TABLE_LEN * ETH_ALEN];
1681 u_short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1682 } tmp;
1683
1684 switch(ioc->cmd) {
1685 case EWRK3_GET_HWADDR:
1686 for (i=0; i<ETH_ALEN; i++) {
1687 tmp.addr[i] = dev->dev_addr[i];
1688 }
1689 ioc->len = ETH_ALEN;
1690 if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
1691 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1692 }
1693
1694 break;
1695 case EWRK3_SET_HWADDR:
1696 if (suser()) {
1697 if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN))) {
1698 csr = inb(EWRK3_CSR);
1699 csr |= (CSR_TXD|CSR_RXD);
1700 outb(csr, EWRK3_CSR);
1701
1702 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1703 for (i=0; i<ETH_ALEN; i++) {
1704 dev->dev_addr[i] = tmp.addr[i];
1705 outb(tmp.addr[i], EWRK3_PAR0 + i);
1706 }
1707
1708 csr &= ~(CSR_TXD|CSR_RXD);
1709 outb(csr, EWRK3_CSR);
1710 }
1711 } else {
1712 status = -EPERM;
1713 }
1714
1715 break;
1716 case EWRK3_SET_PROM:
1717 if (suser()) {
1718 csr = inb(EWRK3_CSR);
1719 csr |= CSR_PME;
1720 csr &= ~CSR_MCE;
1721 outb(csr, EWRK3_CSR);
1722 } else {
1723 status = -EPERM;
1724 }
1725
1726 break;
1727 case EWRK3_CLR_PROM:
1728 if (suser()) {
1729 csr = inb(EWRK3_CSR);
1730 csr &= ~CSR_PME;
1731 outb(csr, EWRK3_CSR);
1732 } else {
1733 status = -EPERM;
1734 }
1735
1736 break;
1737 case EWRK3_SAY_BOO:
1738 printk("%s: Boo!\n", dev->name);
1739
1740 break;
1741 case EWRK3_GET_MCA:
1742 if (!(status = verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1743 while (set_bit(0, (void *)&lp->lock) != 0);
1744 if (lp->shmem_length == IO_ONLY) {
1745 outb(0, EWRK3_IOPR);
1746 outw(PAGE0_HTE, EWRK3_PIR1);
1747 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1748 tmp.addr[i] = inb(EWRK3_DATA);
1749 }
1750 } else {
1751 outb(0, EWRK3_MPR);
1752 memcpy_fromio(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1753 }
1754 ioc->len = (HASH_TABLE_LEN >> 3);
1755 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1756 }
1757 lp->lock = 0;
1758
1759 break;
1760 case EWRK3_SET_MCA:
1761 if (suser()) {
1762 if (!(status=verify_area(VERIFY_READ, ioc->data, ETH_ALEN*ioc->len))) {
1763 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1764 set_multicast_list(dev);
1765 }
1766 } else {
1767 status = -EPERM;
1768 }
1769
1770 break;
1771 case EWRK3_CLR_MCA:
1772 if (suser()) {
1773 set_multicast_list(dev);
1774 } else {
1775 status = -EPERM;
1776 }
1777
1778 break;
1779 case EWRK3_MCA_EN:
1780 if (suser()) {
1781 csr = inb(EWRK3_CSR);
1782 csr |= CSR_MCE;
1783 csr &= ~CSR_PME;
1784 outb(csr, EWRK3_CSR);
1785 } else {
1786 status = -EPERM;
1787 }
1788
1789 break;
1790 case EWRK3_GET_STATS:
1791 cli();
1792 ioc->len = sizeof(lp->pktStats);
1793 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1794 memcpy_tofs(ioc->data, &lp->pktStats, ioc->len);
1795 }
1796 sti();
1797
1798 break;
1799 case EWRK3_CLR_STATS:
1800 if (suser()) {
1801 cli();
1802 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1803 sti();
1804 } else {
1805 status = -EPERM;
1806 }
1807
1808 break;
1809 case EWRK3_GET_CSR:
1810 tmp.addr[0] = inb(EWRK3_CSR);
1811 ioc->len = 1;
1812 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1813 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1814 }
1815
1816 break;
1817 case EWRK3_SET_CSR:
1818 if (suser()) {
1819 if (!(status=verify_area(VERIFY_READ, ioc->data, 1))) {
1820 memcpy_fromfs(tmp.addr, ioc->data, 1);
1821 outb(tmp.addr[0], EWRK3_CSR);
1822 }
1823 } else {
1824 status = -EPERM;
1825 }
1826
1827 break;
1828 case EWRK3_GET_EEPROM:
1829 if (suser()) {
1830 for (i=0; i<(EEPROM_MAX>>1); i++) {
1831 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1832 }
1833 i = EEPROM_MAX;
1834 tmp.addr[i++] = inb(EWRK3_CMR);
1835 for (j=0;j<ETH_ALEN;j++) {
1836 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1837 }
1838 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1839 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1840 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1841 }
1842 } else {
1843 status = -EPERM;
1844 }
1845
1846 break;
1847 case EWRK3_SET_EEPROM:
1848 if (suser()) {
1849 if (!(status=verify_area(VERIFY_READ, ioc->data, EEPROM_MAX))) {
1850 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1851 for (i=0; i<(EEPROM_MAX>>1); i++) {
1852 Write_EEPROM(tmp.val[i], iobase, i);
1853 }
1854 }
1855 } else {
1856 status = -EPERM;
1857 }
1858
1859 break;
1860 case EWRK3_GET_CMR:
1861 tmp.addr[0] = inb(EWRK3_CMR);
1862 ioc->len = 1;
1863 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1864 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1865 }
1866
1867 break;
1868 case EWRK3_SET_TX_CUT_THRU:
1869 if (suser()) {
1870 lp->txc = 1;
1871 } else {
1872 status = -EPERM;
1873 }
1874
1875 break;
1876 case EWRK3_CLR_TX_CUT_THRU:
1877 if (suser()) {
1878 lp->txc = 0;
1879 } else {
1880 status = -EPERM;
1881 }
1882
1883 break;
1884 default:
1885 status = -EOPNOTSUPP;
1886 }
1887
1888 return status;
1889 }
1890
1891 #ifdef MODULE
1892 static char devicename[9] = { 0, };
1893 static struct device thisEthwrk = {
1894 devicename,
1895 0, 0, 0, 0,
1896 0x300, 5,
1897 0, 0, 0, NULL, ewrk3_probe };
1898
1899 static int io=0x300;
1900 static int irq=5;
1901
1902 int
1903 init_module(void)
1904 {
1905 thisEthwrk.base_addr=io;
1906 thisEthwrk.irq=irq;
1907 if (register_netdev(&thisEthwrk) != 0)
1908 return -EIO;
1909 return 0;
1910 }
1911
1912 void
1913 cleanup_module(void)
1914 {
1915 if (thisEthwrk.priv) {
1916 kfree(thisEthwrk.priv);
1917 thisEthwrk.priv = NULL;
1918 }
1919 thisEthwrk.irq = 0;
1920
1921 unregister_netdev(&thisEthwrk);
1922 release_region(thisEthwrk.base_addr, EWRK3_TOTAL_SIZE);
1923 }
1924 #endif
1925
1926
1927
1928
1929
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1934