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*/
1 /*
2 * bios32.c - PCI BIOS functions for Alpha systems not using BIOS
3 * emulation code.
4 *
5 * Written by Dave Rusling (david.rusling@reo.mts.dec.com)
6 *
7 * Adapted to 64-bit kernel and then rewritten by David Mosberger
8 * (davidm@cs.arizona.edu)
9 *
10 * For more information, please consult
11 *
12 * PCI BIOS Specification Revision
13 * PCI Local Bus Specification
14 * PCI System Design Guide
15 *
16 * PCI Special Interest Group
17 * M/S HF3-15A
18 * 5200 N.E. Elam Young Parkway
19 * Hillsboro, Oregon 97124-6497
20 * +1 (503) 696-2000
21 * +1 (800) 433-5177
22 *
23 * Manuals are $25 each or $50 for all three, plus $7 shipping
24 * within the United States, $35 abroad.
25 */
26 #include <linux/config.h>
27
28 #if 0
29 # define DBG_DEVS(args) printk args
30 #else
31 # define DBG_DEVS(args)
32 #endif
33
34 #ifndef CONFIG_PCI
35
36 int pcibios_present(void)
/* ![[next]](../icons/right.png)
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*/
37 {
38 return 0;
39 }
40
41 #else /* CONFIG_PCI */
42
43 #include <linux/kernel.h>
44 #include <linux/bios32.h>
45 #include <linux/pci.h>
46 #include <linux/malloc.h>
47 #include <linux/mm.h>
48
49 #include <asm/hwrpb.h>
50 #include <asm/io.h>
51
52
53 #define KB 1024
54 #define MB (1024*KB)
55 #define GB (1024*MB)
56
57 #define MAJOR_REV 0
58 #define MINOR_REV 3
59
60 /*
61 * Align VAL to ALIGN, which must be a power of two.
62 */
63 #define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
64
65
66 /*
67 * Temporary internal macro. If this 0, then do not write to any of
68 * the PCI registers, merely read them (i.e., use configuration as
69 * determined by SRM). The SRM seem do be doing a less than perfect
70 * job in configuring PCI devices, so for now we do it ourselves.
71 * Reconfiguring PCI devices breaks console (RPB) callbacks, but
72 * those don't work properly with 64 bit addresses anyways.
73 *
74 * The accepted convention seems to be that the console (POST
75 * software) should fully configure boot devices and configure the
76 * interrupt routing of *all* devices. In particular, the base
77 * addresses of non-boot devices need not be initialized. For
78 * example, on the AXPpci33 board, the base address a #9 GXE PCI
79 * graphics card reads as zero (this may, however, be due to a bug in
80 * the graphics card---there have been some rumor that the #9 BIOS
81 * incorrectly resets that address to 0...).
82 */
83 #define PCI_MODIFY 1
84
85 extern struct hwrpb_struct *hwrpb;
86
87
88 #if PCI_MODIFY
89
90 #if 0
91 static unsigned int io_base = 64*KB; /* <64KB are (E)ISA ports */
92 #else
93 static unsigned int io_base = 0xb000;
94 #endif
95
96 #if defined(CONFIG_ALPHA_XL)
97 /*
98 an AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
99 that get passed through the PCI<->ISA bridge chip. Because this causes
100 us to set the PCI->Mem window bases lower than normal, we've gotta allocate
101 PCI bus devices' memory addresses *above* the PCI<->memory mapping windows,
102 so that CPU memory DMA addresses issued by a bus device don't conflict
103 with bus memory addresses, like frame buffer memory for graphics cards.
104 */
105 static unsigned int mem_base = 1024*MB;
106 #else /* CONFIG_ALPHA_XL */
107 static unsigned int mem_base = 16*MB; /* <16MB is ISA memory */
108 #endif /* CONFIG_ALPHA_XL */
109
110 /*
111 * Disable PCI device DEV so that it does not respond to I/O or memory
112 * accesses.
113 */
114 static void disable_dev(struct pci_dev *dev)
/* ![[previous]](../icons/left.png)
*/
115 {
116 struct pci_bus *bus;
117 unsigned short cmd;
118
119 bus = dev->bus;
120 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
121
122 /* hack, turn it off first... */
123 cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
124 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND, cmd);
125 }
126
127
128 /*
129 * Layout memory and I/O for a device:
130 */
131 #define MAX(val1, val2) ( ((val1) > (val2)) ? val1 : val2)
132
133 static void layout_dev(struct pci_dev *dev)
/* */
134 {
135 struct pci_bus *bus;
136 unsigned short cmd;
137 unsigned int base, mask, size, reg;
138 unsigned int alignto;
139
140 bus = dev->bus;
141 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
142
143 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
144 /*
145 * Figure out how much space and of what type this
146 * device wants.
147 */
148 pcibios_write_config_dword(bus->number, dev->devfn, reg,
149 0xffffffff);
150 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
151 if (!base) {
152 /* this base-address register is unused */
153 continue;
154 }
155
156 /*
157 * We've read the base address register back after
158 * writing all ones and so now we must decode it.
159 */
160 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
161 /*
162 * I/O space base address register.
163 */
164 cmd |= PCI_COMMAND_IO;
165
166 base &= PCI_BASE_ADDRESS_IO_MASK;
167 mask = (~base << 1) | 0x1;
168 size = (mask & base) & 0xffffffff;
169 /* align to multiple of size of minimum base */
170 alignto = MAX(0x400, size) ;
171 base = ALIGN(io_base, alignto );
172 io_base = base + size;
173 pcibios_write_config_dword(bus->number, dev->devfn,
174 reg, base | 0x1);
175 } else {
176 unsigned int type;
177 /*
178 * Memory space base address register.
179 */
180 cmd |= PCI_COMMAND_MEMORY;
181 type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
182 base &= PCI_BASE_ADDRESS_MEM_MASK;
183 mask = (~base << 1) | 0x1;
184 size = (mask & base) & 0xffffffff;
185 switch (type) {
186 case PCI_BASE_ADDRESS_MEM_TYPE_32:
187 break;
188
189 case PCI_BASE_ADDRESS_MEM_TYPE_64:
190 printk("bios32 WARNING: "
191 "ignoring 64-bit device in "
192 "slot %d, function %d: \n",
193 PCI_SLOT(dev->devfn),
194 PCI_FUNC(dev->devfn));
195 reg += 4; /* skip extra 4 bytes */
196 continue;
197
198 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
199 /*
200 * Allocating memory below 1MB is *very*
201 * tricky, as there may be all kinds of
202 * ISA devices lurking that we don't know
203 * about. For now, we just cross fingers
204 * and hope nobody tries to do this on an
205 * Alpha (or that the console has set it
206 * up properly).
207 */
208 printk("bios32 WARNING: slot %d, function %d "
209 "requests memory below 1MB---don't "
210 "know how to do that.\n",
211 PCI_SLOT(dev->devfn),
212 PCI_FUNC(dev->devfn));
213 continue;
214 }
215 /*
216 * The following holds at least for the Low Cost
217 * Alpha implementation of the PCI interface:
218 *
219 * In sparse memory address space, the first
220 * octant (16MB) of every 128MB segment is
221 * aliased to the the very first 16MB of the
222 * address space (i.e., it aliases the ISA
223 * memory address space). Thus, we try to
224 * avoid allocating PCI devices in that range.
225 * Can be allocated in 2nd-7th octant only.
226 * Devices that need more than 112MB of
227 * address space must be accessed through
228 * dense memory space only!
229 */
230 /* align to multiple of size of minimum base */
231 alignto = MAX(0x1000, size) ;
232 base = ALIGN(mem_base, alignto);
233 if (size > 7 * 16*MB) {
234 printk("bios32 WARNING: slot %d, function %d "
235 "requests %dB of contiguous address "
236 " space---don't use sparse memory "
237 " accesses on this device!!\n",
238 PCI_SLOT(dev->devfn),
239 PCI_FUNC(dev->devfn), size);
240 } else {
241 if (((base / (16*MB)) & 0x7) == 0) {
242 base &= ~(128*MB - 1);
243 base += 16*MB;
244 base = ALIGN(base, alignto);
245 }
246 if (base / (128*MB) != (base + size) / (128*MB)) {
247 base &= ~(128*MB - 1);
248 base += (128 + 16)*MB;
249 base = ALIGN(base, alignto);
250 }
251 }
252 mem_base = base + size;
253 pcibios_write_config_dword(bus->number, dev->devfn,
254 reg, base);
255 }
256 }
257 /* enable device: */
258 if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
259 dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
260 dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
261 dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
262 {
263 /*
264 * All of these (may) have I/O scattered all around
265 * and may not use i/o-base address registers at all.
266 * So we just have to always enable I/O to these
267 * devices.
268 */
269 cmd |= PCI_COMMAND_IO;
270 }
271
272 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
273 cmd | PCI_COMMAND_MASTER);
274 DBG_DEVS(("layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n",
275 bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, dev->class));
276 }
277
278
279 static void layout_bus(struct pci_bus *bus)
/* */
280 {
281 unsigned int l, tio, bio, tmem, bmem;
282 struct pci_bus *child;
283 struct pci_dev *dev;
284
285 DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
286
287 if (!bus->devices && !bus->children)
288 return;
289
290 /*
291 * Align the current bases on appropriate boundaries (4K for
292 * IO and 1MB for memory).
293 */
294 bio = io_base = ALIGN(io_base, 4*KB);
295 bmem = mem_base = ALIGN(mem_base, 1*MB);
296
297 /*
298 * There are times when the PCI devices have already been
299 * setup (e.g., by MILO or SRM). In these cases there is a
300 * window during which two devices may have an overlapping
301 * address range. To avoid this causing trouble, we first
302 * turn off the I/O and memory address decoders for all PCI
303 * devices. They'll be re-enabled only once all address
304 * decoders are programmed consistently.
305 */
306 for (dev = bus->devices; dev; dev = dev->sibling) {
307 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
308 disable_dev(dev) ;
309 }
310 }
311
312 /*
313 * Allocate space to each device:
314 */
315 DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
316
317 for (dev = bus->devices; dev; dev = dev->sibling) {
318 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
319 layout_dev(dev);
320 }
321 }
322 /*
323 * Recursively allocate space for all of the sub-buses:
324 */
325 DBG_DEVS(("layout_bus: starting bus %d children\n", bus->number));
326
327 for (child = bus->children; child; child = child->next) {
328 layout_bus(child);
329 }
330 /*
331 * Align the current bases on 4K and 1MB boundaries:
332 */
333 tio = io_base = ALIGN(io_base, 4*KB);
334 tmem = mem_base = ALIGN(mem_base, 1*MB);
335
336 if (bus->self) {
337 struct pci_dev *bridge = bus->self;
338 /*
339 * Set up the top and bottom of the PCI I/O segment
340 * for this bus.
341 */
342 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
343 0x1c, &l);
344 l = (l & 0xffff0000) | (bio >> 8) | ((tio - 1) & 0xf000);
345 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
346 0x1c, l);
347 /*
348 * Set up the top and bottom of the PCI Memory segment
349 * for this bus.
350 */
351 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
352 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
353 0x20, l);
354 /*
355 * Turn off downstream PF memory address range:
356 */
357 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
358 0x24, 0x0000ffff);
359 /*
360 * Tell bridge that there is an ISA bus in the system:
361 */
362 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
363 0x3c, 0x00040000);
364 /*
365 * Clear status bits, enable I/O (for downstream I/O),
366 * turn on master enable (for upstream I/O), turn on
367 * memory enable (for downstream memory), turn on
368 * master enable (for upstream memory and I/O).
369 */
370 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
371 0x4, 0xffff0007);
372 }
373 }
374
375 #endif /* !PCI_MODIFY */
376
377
378 /*
379 * Given the vendor and device ids, find the n'th instance of that device
380 * in the system.
381 */
382 int pcibios_find_device (unsigned short vendor, unsigned short device_id,
/* */
383 unsigned short index, unsigned char *bus,
384 unsigned char *devfn)
385 {
386 unsigned int curr = 0;
387 struct pci_dev *dev;
388
389 for (dev = pci_devices; dev; dev = dev->next) {
390 if (dev->vendor == vendor && dev->device == device_id) {
391 if (curr == index) {
392 *devfn = dev->devfn;
393 *bus = dev->bus->number;
394 return PCIBIOS_SUCCESSFUL;
395 }
396 ++curr;
397 }
398 }
399 return PCIBIOS_DEVICE_NOT_FOUND;
400 }
401
402
403 /*
404 * Given the class, find the n'th instance of that device
405 * in the system.
406 */
407 int pcibios_find_class (unsigned int class_code, unsigned short index,
/* */
408 unsigned char *bus, unsigned char *devfn)
409 {
410 unsigned int curr = 0;
411 struct pci_dev *dev;
412
413 for (dev = pci_devices; dev; dev = dev->next) {
414 if (dev->class == class_code) {
415 if (curr == index) {
416 *devfn = dev->devfn;
417 *bus = dev->bus->number;
418 return PCIBIOS_SUCCESSFUL;
419 }
420 ++curr;
421 }
422 }
423 return PCIBIOS_DEVICE_NOT_FOUND;
424 }
425
426
427 int pcibios_present(void)
/* */
428 {
429 return 1;
430 }
431
432
433 unsigned long pcibios_init(unsigned long mem_start,
/* */
434 unsigned long mem_end)
435 {
436 printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
437
438 #if !PCI_MODIFY
439 printk("...NOT modifying existing (SRM) PCI configuration\n");
440 #endif
441 return mem_start;
442 }
443
444 /*
445 * The SRM console *disables* the IDE interface, this code ensures its
446 * enabled.
447 *
448 * This code bangs on a control register of the 87312 Super I/O chip
449 * that implements parallel port/serial ports/IDE/FDI. Depending on
450 * the motherboard, the Super I/O chip can be configured through a
451 * pair of registers that are located either at I/O ports 0x26e/0x26f
452 * or 0x398/0x399. Unfortunately, autodetecting which base address is
453 * in use works only once (right after a reset). The Super I/O chip
454 * has the additional quirk that configuration register data must be
455 * written twice (I believe this is a safety feature to prevent
456 * accidental modification---fun, isn't it?).
457 */
458 static inline void enable_ide(long ide_base)
/* */
459 {
460 int data;
461
462 outb(0, ide_base); /* set the index register for reg #0 */
463 data = inb(ide_base+1); /* read the current contents */
464 outb(0, ide_base); /* set the index register for reg #0 */
465 outb(data | 0x40, ide_base+1); /* turn on IDE */
466 outb(data | 0x40, ide_base+1); /* turn on IDE, really! */
467 }
468
469 /*
470 * A small note about bridges and interrupts. The DECchip 21050 (and later chips)
471 * adheres to the PCI-PCI bridge specification. This says that the interrupts on
472 * the other side of a bridge are swizzled in the following manner:
473 *
474 * Dev Interrupt Interrupt
475 * Pin on Pin on
476 * Device Connector
477 *
478 * 4 A A
479 * B B
480 * C C
481 * D D
482 *
483 * 5 A B
484 * B C
485 * C D
486 * D A
487 *
488 * 6 A C
489 * B D
490 * C A
491 * D B
492 *
493 * 7 A D
494 * B A
495 * C B
496 * D C
497 *
498 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
499 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
500 *
501 * The following code is somewhat simplistic as it assumes only one bridge.
502 * I will fix it later (david.rusling@reo.mts.dec.com).
503 */
504 static inline unsigned char bridge_swizzle(unsigned char pin, unsigned int slot)
/* */
505 {
506 /* swizzle */
507 return (((pin-1) + slot) % 4) + 1 ;
508 }
509
510 /*
511 * Most evaluation boards share most of the fixup code, which is isolated here.
512 * This function is declared "inline" as only one platform will ever be selected
513 * in any given kernel. If that platform doesn't need this code, we don't want
514 * it around as dead code.
515 */
516 static inline void common_fixup(long min_idsel, long max_idsel, long irqs_per_slot,
/* */
517 char irq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
518 long ide_base)
519 {
520 struct pci_dev *dev;
521 unsigned char pin;
522 unsigned char slot ;
523
524 /*
525 * Go through all devices, fixing up irqs as we see fit:
526 */
527 for (dev = pci_devices; dev; dev = dev->next) {
528 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
529 dev->irq = 0;
530 /*
531 * This device is not on the primary bus, we need to figure out which
532 * interrupt pin it will come in on. We know which slot it will come
533 * in on 'cos that slot is where the bridge is. Each time the interrupt
534 * line passes through a PCI-PCI bridge we must apply the swizzle function
535 * (see the inline static routine above).
536 */
537 if (dev->bus->number != 0) {
538 struct pci_dev *curr = dev ;
539 /* read the pin and do the PCI-PCI bridge interrupt pin swizzle */
540 pcibios_read_config_byte(dev->bus->number, dev->devfn,
541 PCI_INTERRUPT_PIN, &pin);
542 /* cope with 0 */
543 if (pin == 0) pin = 1 ;
544 /* follow the chain of bridges, swizzling as we go */
545 do {
546 /* swizzle */
547 pin = bridge_swizzle(pin, PCI_SLOT(curr->devfn)) ;
548 /* move up the chain of bridges */
549 curr = curr->bus->self ;
550 } while (curr->bus->self) ;
551 /* The slot is the slot of the last bridge. */
552 slot = PCI_SLOT(curr->devfn) ;
553 } else {
554 /* work out the slot */
555 slot = PCI_SLOT(dev->devfn) ;
556 /* read the pin */
557 pcibios_read_config_byte(dev->bus->number, dev->devfn,
558 PCI_INTERRUPT_PIN, &pin);
559 }
560 if (irq_tab[slot - min_idsel][pin] != -1)
561 dev->irq = irq_tab[slot - min_idsel][pin];
562 #if PCI_MODIFY
563 /* tell the device: */
564 pcibios_write_config_byte(dev->bus->number, dev->devfn,
565 PCI_INTERRUPT_LINE, dev->irq);
566 #endif
567 /*
568 * if its a VGA, enable its BIOS ROM at C0000
569 */
570 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
571 pcibios_write_config_dword(dev->bus->number, dev->devfn,
572 PCI_ROM_ADDRESS,
573 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
574 }
575 }
576
577 }
578 if (ide_base) {
579 enable_ide(ide_base);
580 }
581 }
582
583 /*
584 * The EB66+ is very similar to the EB66 except that it does not have
585 * the on-board NCR and Tulip chips. In the code below, I have used
586 * slot number to refer to the id select line and *not* the slot
587 * number used in the EB66+ documentation. However, in the table,
588 * I've given the slot number, the id select line and the Jxx number
589 * that's printed on the board. The interrupt pins from the PCI slots
590 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
591 * 0x806 ISA.
592 *
593 * In the table, -1 means don't assign an IRQ number. This is usually
594 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
595 */
596 static inline void eb66p_fixup(void)
/* */
597 {
598 char irq_tab[5][5] = {
599 {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
600 {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
601 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
602 {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
603 {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
604 };
605 common_fixup(6, 10, 5, irq_tab, 0x398);
606 }
607
608
609 /*
610 * The AlphaPC64 is very similar to the EB66+ except that its slots
611 * are numbered differently. In the code below, I have used slot
612 * number to refer to the id select line and *not* the slot number
613 * used in the AlphaPC64 documentation. However, in the table, I've
614 * given the slot number, the id select line and the Jxx number that's
615 * printed on the board. The interrupt pins from the PCI slots are
616 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
617 * ISA.
618 *
619 * In the table, -1 means don't assign an IRQ number. This is usually
620 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
621 */
622 static inline void cabriolet_fixup(void)
/* */
623 {
624 char irq_tab[5][5] = {
625 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
626 { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
627 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
628 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
629 { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
630 };
631
632 common_fixup(5, 9, 5, irq_tab, 0x398);
633 }
634
635
636 /*
637 * Fixup configuration for EB66/EB64+ boards.
638 *
639 * Both these boards use the same interrupt summary scheme. There are
640 * two 8 bit external summary registers as follows:
641 *
642 * Summary @ 0x26:
643 * Bit Meaning
644 * 0 Interrupt Line A from slot 0
645 * 1 Interrupt Line A from slot 1
646 * 2 Interrupt Line B from slot 0
647 * 3 Interrupt Line B from slot 1
648 * 4 Interrupt Line C from slot 0
649 * 5 Interrupt line from the two ISA PICs
650 * 6 Tulip (slot
651 * 7 NCR SCSI
652 *
653 * Summary @ 0x27
654 * Bit Meaning
655 * 0 Interrupt Line C from slot 1
656 * 1 Interrupt Line D from slot 0
657 * 2 Interrupt Line D from slot 1
658 * 3 RAZ
659 * 4 RAZ
660 * 5 RAZ
661 * 6 RAZ
662 * 7 RAZ
663 *
664 * The device to slot mapping looks like:
665 *
666 * Slot Device
667 * 5 NCR SCSI controller
668 * 6 PCI on board slot 0
669 * 7 PCI on board slot 1
670 * 8 Intel SIO PCI-ISA bridge chip
671 * 9 Tulip - DECchip 21040 ethernet controller
672 *
673 *
674 * This two layered interrupt approach means that we allocate IRQ 16 and
675 * above for PCI interrupts. The IRQ relates to which bit the interrupt
676 * comes in on. This makes interrupt processing much easier.
677 */
678 static inline void eb66_and_eb64p_fixup(void)
/* */
679 {
680 char irq_tab[5][5] = {
681 {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */
682 {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */
683 {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */
684 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
685 {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */
686 };
687 common_fixup(5, 9, 5, irq_tab, 0);
688 }
689
690
691 /*
692 * Fixup configuration for all boards that route the PCI interrupts
693 * through the SIO PCI/ISA bridge. This includes Noname (AXPpci33),
694 * Avanti (AlphaStation) and Kenetics's Platform 2000.
695 */
696 static inline void sio_fixup(void)
/* */
697 {
698 struct pci_dev *dev;
699 /*
700 * The Noname board has 5 PCI slots with each of the 4
701 * interrupt pins routed to different pins on the PCI/ISA
702 * bridge (PIRQ0-PIRQ3). The table below is based on
703 * information available at:
704 *
705 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
706 *
707 * I have no information on the Avanti interrupt routing, but
708 * the routing seems to be identical to the Noname except
709 * that the Avanti has an additional slot whose routing I'm
710 * unsure of.
711 *
712 * pirq_tab[0] is a fake entry to deal with old PCI boards
713 * that have the interrupt pin number hardwired to 0 (meaning
714 * that they use the default INTA line, if they are interrupt
715 * driven at all).
716 */
717 static const char pirq_tab[][5] = {
718 #ifdef CONFIG_ALPHA_P2K
719 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
720 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
721 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
722 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
723 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
724 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
725 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
726 #else
727 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
728 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
729 { 2, 2, -1, -1, -1}, /* idsel 8 (Noname hack: slot closest to ISA) */
730 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
731 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
732 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
733 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
734 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
735 #endif
736 };
737 /*
738 * route_tab selects irq routing in PCI/ISA bridge so that:
739 * PIRQ0 -> irq 15
740 * PIRQ1 -> irq 9
741 * PIRQ2 -> irq 10
742 * PIRQ3 -> irq 11
743 *
744 * This probably ought to be configurable via MILO. For
745 * example, sound boards seem to like using IRQ 9.
746 */
747 const unsigned int route_tab = 0x0b0a090f;
748 unsigned int level_bits;
749 unsigned char pin, slot;
750 int pirq;
751
752 pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
753
754 /*
755 * Go through all devices, fixing up irqs as we see fit:
756 */
757 level_bits = 0;
758 for (dev = pci_devices; dev; dev = dev->next) {
759 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE)
760 continue;
761 dev->irq = 0;
762 if (dev->bus->number != 0) {
763 struct pci_dev *curr = dev ;
764 /*
765 * read the pin and do the PCI-PCI bridge
766 * interrupt pin swizzle
767 */
768 pcibios_read_config_byte(dev->bus->number, dev->devfn,
769 PCI_INTERRUPT_PIN, &pin);
770 /* cope with 0 */
771 if (pin == 0) pin = 1 ;
772 /* follow the chain of bridges, swizzling as we go */
773 do {
774 /* swizzle */
775 pin = bridge_swizzle(pin, PCI_SLOT(curr->devfn)) ;
776 /* move up the chain of bridges */
777 curr = curr->bus->self ;
778 } while (curr->bus->self) ;
779 /* The slot is the slot of the last bridge. */
780 slot = PCI_SLOT(curr->devfn) ;
781 } else {
782 /* work out the slot */
783 slot = PCI_SLOT(dev->devfn) ;
784 /* read the pin */
785 pcibios_read_config_byte(dev->bus->number, dev->devfn,
786 PCI_INTERRUPT_PIN, &pin);
787 }
788
789 if (slot < 6 || slot >= 6 + sizeof(pirq_tab)/sizeof(pirq_tab[0])) {
790 printk("bios32.sio_fixup: "
791 "weird, found device %04x:%04x in non-existent slot %d!!\n",
792 dev->vendor, dev->device, slot);
793 continue;
794 }
795 pirq = pirq_tab[slot - 6][pin];
796
797 DBG_DEVS(("sio_fixup: bus %d slot 0x%x VID 0x%x DID 0x%x\n"
798 " int_slot 0x%x int_pin 0x%x, pirq 0x%x\n",
799 dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device,
800 slot, pin, pirq));
801 /*
802 * if its a VGA, enable its BIOS ROM at C0000
803 */
804 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
805 pcibios_write_config_dword(dev->bus->number, dev->devfn,
806 PCI_ROM_ADDRESS,
807 0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
808 }
809 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
810 continue; /* for now, displays get no IRQ */
811 }
812
813 if (pirq < 0) {
814 printk("bios32.sio_fixup: "
815 "weird, device %04x:%04x coming in on slot %d has no irq line!!\n",
816 dev->vendor, dev->device, slot);
817 continue;
818 }
819
820 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
821
822 /* must set the PCI IRQs to level triggered */
823 level_bits |= (1 << dev->irq);
824
825 #if PCI_MODIFY
826 /* tell the device: */
827 pcibios_write_config_byte(dev->bus->number, dev->devfn,
828 PCI_INTERRUPT_LINE, dev->irq);
829 #endif
830 }
831 /*
832 * Now, make all PCI interrupts level sensitive. Notice:
833 * these registers must be accessed byte-wise. inw()/outw()
834 * don't work.
835 */
836 level_bits |= (inb(0x4d0) | (inb(0x4d1) << 8));
837 outb((level_bits >> 0) & 0xff, 0x4d0);
838 outb((level_bits >> 8) & 0xff, 0x4d1);
839 enable_ide(0x26e);
840 }
841
842
843 #ifdef CONFIG_TGA_CONSOLE
844 extern void tga_console_init(void);
845 #endif /* CONFIG_TGA_CONSOLE */
846
847 unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
/* */
848 {
849 #if PCI_MODIFY
850 /*
851 * Scan the tree, allocating PCI memory and I/O space.
852 */
853 layout_bus(&pci_root);
854 #endif
855
856 /*
857 * Now is the time to do all those dirty little deeds...
858 */
859 #if defined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI) || defined(CONFIG_ALPHA_P2K)
860 sio_fixup();
861 #elif defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB164)
862 cabriolet_fixup();
863 #elif defined(CONFIG_ALPHA_EB66P)
864 eb66p_fixup();
865 #elif defined(CONFIG_ALPHA_EB66)
866 eb66_and_eb64p_fixup();
867 #elif defined(CONFIG_ALPHA_EB64P)
868 eb66_and_eb64p_fixup();
869 #else
870 # error You must tell me what kind of platform you want.
871 #endif
872
873 #ifdef CONFIG_TGA_CONSOLE
874 tga_console_init();
875 #endif /* CONFIG_TGA_CONSOLE */
876
877 return mem_start;
878 }
879
880
881 const char *pcibios_strerror (int error)
/* ![[last]](../icons/n_last.png)
*/
882 {
883 static char buf[80];
884
885 switch (error) {
886 case PCIBIOS_SUCCESSFUL:
887 return "SUCCESSFUL";
888
889 case PCIBIOS_FUNC_NOT_SUPPORTED:
890 return "FUNC_NOT_SUPPORTED";
891
892 case PCIBIOS_BAD_VENDOR_ID:
893 return "SUCCESSFUL";
894
895 case PCIBIOS_DEVICE_NOT_FOUND:
896 return "DEVICE_NOT_FOUND";
897
898 case PCIBIOS_BAD_REGISTER_NUMBER:
899 return "BAD_REGISTER_NUMBER";
900
901 default:
902 sprintf (buf, "UNKNOWN RETURN 0x%x", error);
903 return buf;
904 }
905 }
906
907 #endif /* CONFIG_PCI */
![[bottom]](../icons/n_bottom.png){kind=icon}
*/