include/asm-i386/smp.h

/* */
This source file includes following definitions.
apic_write
apic_read
smp_processor_id
   1 #ifndef __ASM_SMP_H
   2 #define __ASM_SMP_H
   3 
   4 #ifdef __SMP__
   5 #ifndef ASSEMBLY
   6 
   7 #include <asm/i82489.h>
   8 #include <asm/bitops.h>
   9 #include <linux/tasks.h>
  10 #include <linux/ptrace.h>
  11 
  12 /*
  13  *      Support definitions for SMP machines following the intel multiprocessing
  14  *      specification
  15  */
  16 
  17 /*
  18  *      This tag identifies where the SMP configuration
  19  *      information is. 
  20  */
  21  
  22 #define SMP_MAGIC_IDENT ('_'<<24)|('P'<<16)|('M'<<8)|'_'
  23 
  24 struct intel_mp_floating
  25 {
  26         char mpf_signature[4];          /* "_MP_"                       */
  27         unsigned long mpf_physptr;      /* Configuration table address  */
  28         unsigned char mpf_length;       /* Our length (paragraphs)      */
  29         unsigned char mpf_specification;/* Specification version        */
  30         unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
  31         unsigned char mpf_feature1;     /* Standard or configuration ?  */
  32         unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
  33         unsigned char mpf_feature3;     /* Unused (0)                   */
  34         unsigned char mpf_feature4;     /* Unused (0)                   */
  35         unsigned char mpf_feature5;     /* Unused (0)                   */
  36 };
  37 
  38 struct mp_config_table
  39 {
  40         char mpc_signature[4];
  41 #define MPC_SIGNATURE "PCMP"
  42         unsigned short mpc_length;      /* Size of table */
  43         char  mpc_spec;                 /* 0x01 */
  44         char  mpc_checksum;
  45         char  mpc_oem[8];
  46         char  mpc_productid[12];
  47         unsigned long mpc_oemptr;       /* 0 if not present */
  48         unsigned short mpc_oemsize;     /* 0 if not present */
  49         unsigned short mpc_oemcount;
  50         unsigned long mpc_lapic;        /* APIC address */
  51         unsigned long reserved;
  52 };
  53 
  54 /* Followed by entries */
  55 
  56 #define MP_PROCESSOR    0
  57 #define MP_BUS          1
  58 #define MP_IOAPIC       2
  59 #define MP_INTSRC       3
  60 #define MP_LINTSRC      4
  61 
  62 struct mpc_config_processor
  63 {
  64         unsigned char mpc_type;
  65         unsigned char mpc_apicid;       /* Local APIC number */
  66         unsigned char mpc_apicver;      /* Its versions */
  67         unsigned char mpc_cpuflag;
  68 #define CPU_ENABLED             1       /* Processor is available */
  69 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
  70         unsigned long mpc_cpufeature;           
  71 #define CPU_STEPPING_MASK 0x0F
  72 #define CPU_MODEL_MASK  0xF0
  73 #define CPU_FAMILY_MASK 0xF00
  74         unsigned long mpc_featureflag;  /* CPUID feature value */
  75         unsigned long mpc_reserved[2];
  76 };
  77 
  78 struct mpc_config_bus
  79 {
  80         unsigned char mpc_type;
  81         unsigned char mpc_busid;
  82         unsigned char mpc_bustype[6] __attribute((packed));
  83 };
  84 
  85 #define BUSTYPE_EISA    "EISA"
  86 #define BUSTYPE_ISA     "ISA"
  87 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
  88 #define BUSTYPE_MCA     "MCA"
  89 #define BUSTYPE_VL      "VL"            /* Local bus */
  90 #define BUSTYPE_PCI     "PCI"
  91 #define BUSTYPE_PCMCIA  "PCMCIA"
  92 
  93 /* We don't understand the others */
  94 
  95 struct mpc_config_ioapic
  96 {
  97         unsigned char mpc_type;
  98         unsigned char mpc_apicid;
  99         unsigned char mpc_apicver;
 100         unsigned char mpc_flags;
 101 #define MPC_APIC_USABLE         0x01
 102         unsigned long mpc_apicaddr;
 103 };
 104 
 105 struct mpc_config_intsrc
 106 {
 107         unsigned char mpc_type;
 108         unsigned char mpc_irqtype;
 109         unsigned short mpc_irqflag;
 110         unsigned char mpc_srcbus;
 111         unsigned char mpc_srcbusirq;
 112         unsigned char mpc_dstapic;
 113         unsigned char mpc_dstirq;
 114 };
 115 
 116 #define MP_INT_VECTORED         0
 117 #define MP_INT_NMI              1
 118 #define MP_INT_SMI              2
 119 #define MP_INT_EXTINT           3
 120 
 121 #define MP_IRQDIR_DEFAULT       0
 122 #define MP_IRQDIR_HIGH          1
 123 #define MP_IRQDIR_LOW           3
 124 
 125 
 126 struct mpc_config_intlocal
 127 {
 128         unsigned char mpc_type;
 129         unsigned char mpc_irqtype;
 130         unsigned short mpc_irqflag;
 131         unsigned char mpc_srcbusid;
 132         unsigned char mpc_srcbusirq;
 133         unsigned char mpc_destapic;     
 134 #define MP_APIC_ALL     0xFF
 135         unsigned char mpc_destapiclint;
 136 };
 137 
 138 
 139 /*
 140  *      Default configurations
 141  *
 142  *      1       2 CPU ISA 82489DX
 143  *      2       2 CPU EISA 82489DX no IRQ 8 or timer chaining
 144  *      3       2 CPU EISA 82489DX
 145  *      4       2 CPU MCA 82489DX
 146  *      5       2 CPU ISA+PCI
 147  *      6       2 CPU EISA+PCI
 148  *      7       2 CPU MCA+PCI
 149  */
 150 
 151 /*
 152  *      Per process x86 parameters
 153  */
 154  
 155 struct cpuinfo_x86
 156 {
 157         char hard_math;
 158         char x86;
 159         char x86_model;
 160         char x86_mask;
 161         char x86_vendor_id[16];
 162         int  x86_capability;
 163         int  fdiv_bug;
 164         int  have_cpuid;
 165         char wp_works_ok;
 166         char hlt_works_ok;
 167         unsigned long udelay_val;
 168 };
 169 
 170 
 171 extern struct cpuinfo_x86 cpu_data[NR_CPUS];
 172 
 173 /*
 174  *      Private routines/data
 175  */
 176  
 177 extern int smp_found_config;
 178 extern int smp_scan_config(unsigned long, unsigned long);
 179 extern unsigned long smp_alloc_memory(unsigned long mem_base);
 180 extern unsigned char *apic_reg;
 181 extern unsigned char *kernel_stacks[NR_CPUS];
 182 extern unsigned char boot_cpu_id;
 183 extern unsigned long cpu_present_map;
 184 extern volatile int cpu_number_map[NR_CPUS];
 185 extern volatile int cpu_logical_map[NR_CPUS];
 186 extern volatile unsigned long smp_invalidate_needed;
 187 extern void smp_flush_tlb(void);
 188 extern volatile unsigned long kernel_flag, kernel_counter;
 189 extern volatile unsigned long cpu_callin_map[NR_CPUS];
 190 extern volatile unsigned char active_kernel_processor;
 191 extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
 192 extern void smp_reschedule_irq(int cpl, struct pt_regs *regs);
 193 extern unsigned long ipi_count;
 194 extern void smp_invalidate_rcv(void);           /* Process an NMI */
 195 extern volatile unsigned long kernel_counter;
 196 extern volatile unsigned long syscall_count;
 197 
 198 /*
 199  *      General functions that each host system must provide.
 200  */
 201  
 202 extern void smp_callin(void);
 203 extern void smp_boot_cpus(void);
 204 extern void smp_store_cpu_info(int id);         /* Store per cpu info (like the initial udelay numbers */
 205 
 206 extern volatile unsigned long smp_proc_in_lock[NR_CPUS]; /* for computing process time */
 207 extern volatile unsigned long smp_process_available;
 208 
 209 /*
 210  *      APIC handlers: Note according to the Intel specification update
 211  *      you should put reads between APIC writes.
 212  *      Intel Pentium processor specification update [11AP, pg 64]
 213  *              "Back to Back Assertions of HOLD May Cause Lost APIC Write Cycle"
 214  */
 215 
 216 extern __inline void apic_write(unsigned long reg, unsigned long v)
     /*  */
 217 {
 218         *((volatile unsigned long *)(apic_reg+reg))=v;
 219 }
 220 
 221 extern __inline unsigned long apic_read(unsigned long reg)
     /*  */
 222 {
 223         return *((volatile unsigned long *)(apic_reg+reg));
 224 }
 225 
 226 /*
 227  *      This function is needed by all SMP systems. It must _always_ be valid from the initial
 228  *      startup. This may require magic on some systems (in the i86 case we dig out the boot 
 229  *      cpu id from the config and set up a fake apic_reg pointer so that before we activate
 230  *      the apic we get the right answer). Hopefully other processors are more sensible 8)
 231  */
 232  
 233 extern __inline int smp_processor_id(void)
     /*  */
 234 {
 235         return GET_APIC_ID(apic_read(APIC_ID));
 236 }
 237 
 238 #endif /* !ASSEMBLY */
 239 
 240 #define NO_PROC_ID              0xFF            /* No processor magic marker */
 241 
 242 /*
 243  *      This magic constant controls our willingness to transfer
 244  *      a process across CPUs. Such a transfer incurs misses on the L1
 245  *      cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
 246  *      gut feeling is this will vary by board in value. For a board
 247  *      with separate L2 cache it probably depends also on the RSS, and
 248  *      for a board with shared L2 cache it ought to decay fast as other
 249  *      processes are run.
 250  */
 251  
 252 #define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
 253 
 254 #define SMP_FROM_INT            1
 255 #define SMP_FROM_SYSCALL        2
 256 
 257 #endif
 258 #endif
/* */
root/include/asm-i386/smp.h

INCLUDED FROM

DEFINITIONS
