This source file includes following definitions.
- readisac_0
- readisac_3
- writeisac_0
- writeisac_3
- readisac_s
- writeisac_s
- readhscx_0
- readhscx_3
- writehscx_0
- writehscx_3
- readhscx_s
- writehscx_s
- waitforCEC_0
- waitforCEC_3
- waitforXFW_0
- waitforXFW_3
- writehscxCMDR_0
- writehscxCMDR_3
- teles_hscxreport
- teles_report
- hscx_sched_event
- hscx_empty_fifo
- hscx_fill_fifo
- hscx_interrupt
- isac_sched_event
- empty_fifo
- fill_fifo
- act_wanted
- ph_command
- isac_new_ph
- teles_interrupt
- act_ivated
- process_new_ph
- process_xmt
- process_rcv
- isac_bh
- hscx_process_xmt
- hscx_process_rcv
- hscx_bh
- restart_ph
- initisac
- checkcard
- modehscx
- teles_addlist
- teles_rmlist
- teles_l2l1
- check_ph_act
- teles_manl1
- teles_l2l1discardq
- setstack_teles
- init_hscxstate
- initcard
- get_irq
- release_irq
- close_hscxstate
- closecard
- teles_shiftcards
- teles_inithardware
- teles_closehardware
- hscx_l2l1
- hscx_l2l1discardq
- open_hscxstate
- hscx_manl1
- setstack_hscx
- teles_reportcard
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16 #define __NO_VERSION__
17 #include "teles.h"
18
19 #define INCLUDE_INLINE_FUNCS
20 #include <linux/tqueue.h>
21 #include <linux/interrupt.h>
22
23 #undef DCHAN_VERBOSE
24
25 extern void tei_handler(struct PStack *st, byte pr,
26 struct BufHeader *ibh);
27 extern struct IsdnCard cards[];
28 extern int nrcards;
29
30 #define byteout(addr,val) outb_p(val,addr)
31 #define bytein(addr) inb_p(addr)
32
33 static inline byte
34 readisac_0(byte * cardm, byte offset)
35 {
36 return *(byte *) (cardm + 0x100 + ((offset & 1) ? 0x1ff : 0) + offset);
37 }
38
39 static inline byte
40 readisac_3(int iobase, byte offset)
41 {
42 return (bytein(iobase - 0x420 + offset));
43 }
44
45 #define READISAC(mbase,ibase,ofs) \
46 ((mbase)?readisac_0(mbase,ofs):readisac_3(ibase,ofs))
47
48 static inline void
49 writeisac_0(byte * cardm, byte offset, byte value)
50 {
51 *(byte *) (cardm + 0x100 + ((offset & 1) ? 0x1ff : 0) + offset) = value;
52 }
53
54 static inline void
55 writeisac_3(int iobase, byte offset, byte value)
56 {
57 byteout(iobase - 0x420 + offset, value);
58 }
59
60 #define WRITEISAC(mbase,ibase,ofs,val) \
61 ((mbase)?writeisac_0(mbase,ofs,val):writeisac_3(ibase,ofs,val))
62
63 static inline void
64 readisac_s(int iobase, byte offset, byte * dest, int count)
65 {
66 insb(iobase - 0x420 + offset, dest, count);
67 }
68
69 static inline void
70 writeisac_s(int iobase, byte offset, byte * src, int count)
71 {
72 outsb(iobase - 0x420 + offset, src, count);
73 }
74
75 static inline byte
76 readhscx_0(byte * base, byte hscx, byte offset)
77 {
78 return *(byte *) (base + 0x180 + ((offset & 1) ? 0x1FF : 0) +
79 ((hscx & 1) ? 0x40 : 0) + offset);
80 }
81
82 static inline byte
83 readhscx_3(int iobase, byte hscx, byte offset)
84 {
85 return (bytein(iobase - (hscx ? 0x820 : 0xc20) + offset));
86 }
87
88 #define READHSCX(mbase,ibase,hscx,ofs) \
89 ((mbase)?readhscx_0(mbase,hscx,ofs):readhscx_3(ibase,hscx,ofs))
90
91 static inline void
92 writehscx_0(byte * base, byte hscx, byte offset, byte data)
93 {
94 *(byte *) (base + 0x180 + ((offset & 1) ? 0x1FF : 0) +
95 ((hscx & 1) ? 0x40 : 0) + offset) = data;
96 }
97
98 static inline void
99 writehscx_3(int iobase, byte hscx, byte offset, byte data)
100 {
101 byteout(iobase - (hscx ? 0x820 : 0xc20) + offset, data);
102 }
103
104 static inline void
105 readhscx_s(int iobase, byte hscx, byte offset, byte * dest, int count)
106 {
107 insb(iobase - (hscx ? 0x820 : 0xc20) + offset, dest, count);
108 }
109
110 static inline void
111 writehscx_s(int iobase, byte hscx, byte offset, byte * src, int count)
112 {
113 outsb(iobase - (hscx ? 0x820 : 0xc20) + offset, src, count);
114 }
115
116 #define ISAC_MASK 0x20
117 #define ISAC_ISTA 0x20
118 #define ISAC_STAR 0x21
119 #define ISAC_CMDR 0x21
120 #define ISAC_EXIR 0x24
121
122 #define ISAC_RBCH 0x2a
123
124 #define ISAC_ADF2 0x39
125 #define ISAC_SPCR 0x30
126 #define ISAC_ADF1 0x38
127 #define ISAC_CIX0 0x31
128 #define ISAC_STCR 0x37
129 #define ISAC_MODE 0x22
130 #define ISAC_RSTA 0x27
131 #define ISAC_RBCL 0x25
132 #define ISAC_TIMR 0x23
133 #define ISAC_SQXR 0x3b
134
135 #define HSCX_ISTA 0x20
136 #define HSCX_CCR1 0x2f
137 #define HSCX_CCR2 0x2c
138 #define HSCX_TSAR 0x31
139 #define HSCX_TSAX 0x30
140 #define HSCX_XCCR 0x32
141 #define HSCX_RCCR 0x33
142 #define HSCX_MODE 0x22
143 #define HSCX_CMDR 0x21
144 #define HSCX_EXIR 0x24
145 #define HSCX_XAD1 0x24
146 #define HSCX_XAD2 0x25
147 #define HSCX_RAH2 0x27
148 #define HSCX_RSTA 0x27
149 #define HSCX_TIMR 0x23
150 #define HSCX_STAR 0x21
151 #define HSCX_RBCL 0x25
152 #define HSCX_XBCH 0x2d
153 #define HSCX_VSTR 0x2e
154 #define HSCX_RLCR 0x2e
155 #define HSCX_MASK 0x20
156
157 static inline void
158 waitforCEC_0(byte * base, byte hscx)
159 {
160 long to = 10;
161
162 while ((readhscx_0(base, hscx, HSCX_STAR) & 0x04) && to) {
163 udelay(5);
164 to--;
165 }
166 if (!to)
167 printk(KERN_WARNING "waitforCEC timeout\n");
168 }
169
170 static inline void
171 waitforCEC_3(int iobase, byte hscx)
172 {
173 long to = 10;
174
175 while ((readhscx_3(iobase, hscx, HSCX_STAR) & 0x04) && to) {
176 udelay(5);
177 to--;
178 }
179 if (!to)
180 printk(KERN_WARNING "waitforCEC timeout\n");
181 }
182
183 static inline void
184 waitforXFW_0(byte * base, byte hscx)
185 {
186 long to = 10;
187
188 waitforCEC_0(base, hscx);
189
190 while ((!(readhscx_0(base, hscx, HSCX_STAR) & 0x40)) && to) {
191 udelay(5);
192 to--;
193 }
194 if (!to)
195 printk(KERN_WARNING "waitforXFW timeout\n");
196 }
197
198 static inline void
199 waitforXFW_3(int iobase, byte hscx)
200 {
201 long to = 10;
202
203 waitforCEC_3(iobase, hscx);
204
205 while ((!(readhscx_3(iobase, hscx, HSCX_STAR) & 0x40)) && to) {
206 udelay(5);
207 to--;
208 }
209 if (!to)
210 printk(KERN_WARNING "waitforXFW timeout\n");
211 }
212
213 static inline void
214 writehscxCMDR_0(byte * base, byte hscx, byte data)
215 {
216 long flags;
217
218 save_flags(flags);
219 cli();
220 waitforCEC_0(base, hscx);
221 writehscx_0(base, hscx, HSCX_CMDR, data);
222 restore_flags(flags);
223 }
224
225 static inline void
226 writehscxCMDR_3(int iobase, byte hscx, byte data)
227 {
228 long flags;
229
230 save_flags(flags);
231 cli();
232 waitforCEC_3(iobase, hscx);
233 writehscx_3(iobase, hscx, HSCX_CMDR, data);
234 restore_flags(flags);
235 }
236
237 #define WRITEHSCX_CMDR(mbase,ibase,hscx,data) \
238 ((mbase)?writehscxCMDR_0(mbase,hscx,data):writehscxCMDR_3(ibase,hscx,data))
239
240
241
242
243
244 #define ISAC_RCVBUFREADY 0
245 #define ISAC_XMTBUFREADY 1
246 #define ISAC_PHCHANGE 2
247
248 #define HSCX_RCVBUFREADY 0
249 #define HSCX_XMTBUFREADY 1
250
251 void
252 teles_hscxreport(struct IsdnCardState *sp, int hscx)
253 {
254 printk(KERN_DEBUG "HSCX %d\n", hscx);
255 if (sp->membase) {
256 printk(KERN_DEBUG " ISTA %x\n", readhscx_0(sp->membase,
257 hscx, HSCX_ISTA));
258 printk(KERN_DEBUG " STAR %x\n", readhscx_0(sp->membase,
259 hscx, HSCX_STAR));
260 printk(KERN_DEBUG " EXIR %x\n", readhscx_0(sp->membase,
261 hscx, HSCX_EXIR));
262 } else {
263 printk(KERN_DEBUG " ISTA %x\n", readhscx_3(sp->iobase,
264 hscx, HSCX_ISTA));
265 printk(KERN_DEBUG " STAR %x\n", readhscx_3(sp->iobase,
266 hscx, HSCX_STAR));
267 printk(KERN_DEBUG " EXIR %x\n", readhscx_3(sp->iobase,
268 hscx, HSCX_EXIR));
269 }
270 }
271
272 void
273 teles_report(struct IsdnCardState *sp)
274 {
275 printk(KERN_DEBUG "ISAC\n");
276 if (sp->membase) {
277 printk(KERN_DEBUG " ISTA %x\n", readisac_0(sp->membase,
278 ISAC_ISTA));
279 printk(KERN_DEBUG " STAR %x\n", readisac_0(sp->membase,
280 ISAC_STAR));
281 printk(KERN_DEBUG " EXIR %x\n", readisac_0(sp->membase,
282 ISAC_EXIR));
283 } else {
284 printk(KERN_DEBUG " ISTA %x\n", readisac_3(sp->iobase,
285 ISAC_ISTA));
286 printk(KERN_DEBUG " STAR %x\n", readisac_3(sp->iobase,
287 ISAC_STAR));
288 printk(KERN_DEBUG " EXIR %x\n", readisac_3(sp->iobase,
289 ISAC_EXIR));
290 }
291 teles_hscxreport(sp, 0);
292 teles_hscxreport(sp, 1);
293 }
294
295
296
297
298
299 static void
300 hscx_sched_event(struct HscxState *hsp, int event)
301 {
302 hsp->event |= 1 << event;
303 queue_task_irq_off(&hsp->tqueue, &tq_immediate);
304 mark_bh(IMMEDIATE_BH);
305 }
306
307 static void
308 hscx_empty_fifo(struct HscxState *hsp, int count)
309 {
310 byte *ptr;
311 struct BufHeader *ibh = hsp->rcvibh;
312
313 if (hsp->sp->debug)
314 printk(KERN_DEBUG "hscx_empty_fifo\n");
315
316 if (hsp->rcvptr + count > BUFFER_SIZE(HSCX_RBUF_ORDER,
317 HSCX_RBUF_BPPS)) {
318 printk(KERN_WARNING
319 "hscx_empty_fifo: incoming packet too large\n");
320 WRITEHSCX_CMDR(hsp->membase, hsp->iobase, hsp->hscx, 0x80);
321 return;
322 }
323 ptr = DATAPTR(ibh);
324 ptr += hsp->rcvptr;
325
326 hsp->rcvptr += count;
327 if (hsp->membase) {
328 while (count--)
329 *ptr++ = readhscx_0(hsp->membase, hsp->hscx, 0x0);
330 writehscxCMDR_0(hsp->membase, hsp->hscx, 0x80);
331 } else {
332 readhscx_s(hsp->iobase, hsp->hscx, 0x3e, ptr, count);
333 writehscxCMDR_3(hsp->iobase, hsp->hscx, 0x80);
334 }
335 #ifdef BCHAN_VERBOSE
336 {
337 int i;
338 printk(KERN_DEBUG "hscx_empty_fifo");
339 for (i = 0; i < count; i++)
340 printk(" %2x", ptr[i]);
341 printk("\n");
342 }
343 #endif
344 }
345
346 static void
347 hscx_fill_fifo(struct HscxState *hsp)
348 {
349 struct BufHeader *ibh;
350 int more, count;
351 byte *ptr;
352
353 if (hsp->sp->debug)
354 printk(KERN_DEBUG "hscx_fill_fifo\n");
355
356 ibh = hsp->xmtibh;
357 if (!ibh)
358 return;
359
360 count = ibh->datasize - hsp->sendptr;
361 if (count <= 0)
362 return;
363
364 #if 0
365 if (!hsp->sendptr) {
366 ptr = DATAPTR(ibh);
367 printk(KERN_DEBUG "snd bytes %2x %2x %2x %2x %2x\n", ptr[0], ptr[1], ptr[2],
368 ptr[3], ptr[4]);
369 }
370 #endif
371
372 more = 0;
373 if (count > 32) {
374 more = !0;
375 count = 32;
376 }
377 ptr = DATAPTR(ibh);
378 ptr += hsp->sendptr;
379 hsp->sendptr += count;
380
381 #ifdef BCHAN_VERBOSE
382 {
383 int i;
384 printk(KERN_DEBUG "hscx_fill_fifo ");
385 for (i = 0; i < count; i++)
386 printk(" %2x", ptr[i]);
387 printk("\n");
388 }
389 #endif
390 if (hsp->membase) {
391 waitforXFW_0(hsp->membase, hsp->hscx);
392 while (count--)
393 writehscx_0(hsp->membase, hsp->hscx, 0x0, *ptr++);
394 writehscxCMDR_0(hsp->membase, hsp->hscx, more ? 0x8 : 0xa);
395 } else {
396 waitforXFW_3(hsp->iobase, hsp->hscx);
397 writehscx_s(hsp->iobase, hsp->hscx, 0x3e, ptr, count);
398 writehscxCMDR_3(hsp->iobase, hsp->hscx, more ? 0x8 : 0xa);
399 }
400 }
401
402 static inline void
403 hscx_interrupt(struct IsdnCardState *sp, byte val, byte hscx)
404 {
405 byte r;
406 struct HscxState *hsp = sp->hs + hscx;
407 int count;
408
409 if (!hsp->init)
410 return;
411
412 if (val & 0x80) {
413
414 r = READHSCX(hsp->membase, sp->iobase, hsp->hscx, HSCX_RSTA);
415 if ((r & 0xf0) != 0xa0) {
416 if (!r & 0x80)
417 printk(KERN_WARNING
418 "Teles: HSCX invalid frame\n");
419 if (r & 0x40)
420 printk(KERN_WARNING "Teles: HSCX RDO\n");
421 if (!r & 0x20)
422 printk(KERN_WARNING "Teles: HSCX CRC error\n");
423 if (hsp->rcvibh)
424 BufPoolRelease(hsp->rcvibh);
425 hsp->rcvibh = NULL;
426 WRITEHSCX_CMDR(hsp->membase, hsp->iobase, hsp->hscx,
427 0x80);
428 goto afterRME;
429 }
430 if (!hsp->rcvibh)
431 if (BufPoolGet(&hsp->rcvibh, &hsp->rbufpool,
432 GFP_ATOMIC, (void *) 1, 1)) {
433 printk(KERN_WARNING
434 "HSCX RME out of buffers at %ld\n",
435 jiffies);
436 WRITEHSCX_CMDR(hsp->membase, hsp->iobase,
437 hsp->hscx, 0x80);
438 goto afterRME;
439 } else
440 hsp->rcvptr = 0;
441
442 count = READHSCX(hsp->membase, sp->iobase, hsp->hscx,
443 HSCX_RBCL) & 0x1f;
444 if (count == 0)
445 count = 32;
446 hscx_empty_fifo(hsp, count);
447 hsp->rcvibh->datasize = hsp->rcvptr - 1;
448 BufQueueLink(&hsp->rq, hsp->rcvibh);
449 hsp->rcvibh = NULL;
450 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
451 }
452 afterRME:
453 if (val & 0x40) {
454 if (!hsp->rcvibh)
455 if (BufPoolGet(&hsp->rcvibh, &hsp->rbufpool,
456 GFP_ATOMIC, (void *) 1, 2)) {
457 printk(KERN_WARNING
458 "HSCX RME out of buffers at %ld\n",
459 jiffies);
460 WRITEHSCX_CMDR(hsp->membase, hsp->iobase,
461 hsp->hscx, 0x80);
462 goto afterRPF;
463 } else
464 hsp->rcvptr = 0;
465
466 hscx_empty_fifo(hsp, 32);
467 #ifdef VOICE
468 hsp->rcvibh->datasize = hsp->rcvptr - 1;
469 BufQueueLink(&hsp->rq, hsp->rcvibh);
470 hsp->rcvibh = NULL;
471 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
472 #endif
473 }
474 afterRPF:
475 if (val & 0x10) {
476 if (hsp->xmtibh)
477 if (hsp->xmtibh->datasize > hsp->sendptr) {
478 hscx_fill_fifo(hsp);
479 goto afterXPR;
480 } else {
481 if (hsp->releasebuf)
482 BufPoolRelease(hsp->xmtibh);
483 hsp->xmtibh = NULL;
484 hsp->sendptr = 0;
485 if (hsp->st->l4.l1writewakeup)
486 hsp->st->l4.l1writewakeup(hsp->st);
487 }
488 if (!BufQueueUnlink(&hsp->xmtibh, &hsp->sq)) {
489 hsp->releasebuf = !0;
490 hscx_fill_fifo(hsp);
491 } else
492 hscx_sched_event(hsp, HSCX_XMTBUFREADY);
493 }
494 afterXPR:
495 }
496
497
498
499
500
501 static void
502 isac_sched_event(struct IsdnCardState *sp, int event)
503 {
504 sp->event |= 1 << event;
505 queue_task_irq_off(&sp->tqueue, &tq_immediate);
506 mark_bh(IMMEDIATE_BH);
507 }
508
509 static void
510 empty_fifo(struct IsdnCardState *sp, int count)
511 {
512 byte *ptr;
513 struct BufHeader *ibh = sp->rcvibh;
514
515 if (sp->debug)
516 printk(KERN_DEBUG "empty_fifo\n");
517
518 if (sp->rcvptr >= 3072) {
519 printk(KERN_WARNING "empty_fifo rcvptr %d\n", sp->rcvptr);
520 return;
521 }
522 ptr = DATAPTR(ibh);
523 ptr += sp->rcvptr;
524 sp->rcvptr += count;
525
526 if (sp->membase) {
527 #ifdef DCHAN_VERBOSE
528 printk(KERN_DEBUG "empty_fifo ");
529 while (count--) {
530 *ptr = readisac_0(sp->membase, 0x0);
531 printk("%2x ", *ptr);
532 ptr++;
533 }
534 printk("\n");
535 #else
536 while (count--)
537 *ptr++ = readisac_0(sp->membase, 0x0);
538 #endif
539 writeisac_0(sp->membase, ISAC_CMDR, 0x80);
540 } else {
541 #ifdef DCHAN_VERBOSE
542 int i;
543 printk(KERN_DEBUG "empty_fifo ");
544 readisac_s(sp->iobase, 0x3e, ptr, count);
545 for (i = 0; i < count; i++)
546 printk("%2x ", ptr[i]);
547 printk("\n");
548 #else
549 readisac_s(sp->iobase, 0x3e, ptr, count);
550 #endif
551 writeisac_3(sp->iobase, ISAC_CMDR, 0x80);
552 }
553 }
554
555 static void
556 fill_fifo(struct IsdnCardState *sp)
557 {
558 struct BufHeader *ibh;
559 int count, more;
560 byte *ptr;
561
562 if (sp->debug)
563 printk(KERN_DEBUG "fill_fifo\n");
564
565 ibh = sp->xmtibh;
566 if (!ibh)
567 return;
568
569 count = ibh->datasize - sp->sendptr;
570 if (count <= 0)
571 return;
572 if (count >= 3072)
573 return;
574
575 more = 0;
576 if (count > 32) {
577 more = !0;
578 count = 32;
579 }
580 ptr = DATAPTR(ibh);
581 ptr += sp->sendptr;
582 sp->sendptr += count;
583
584 if (sp->membase) {
585 #ifdef DCHAN_VERBOSE
586 printk(KERN_DEBUG "fill_fifo ");
587 while (count--) {
588 writeisac_0(sp->membase, 0x0, *ptr);
589 printk("%2x ", *ptr);
590 ptr++;
591 }
592 printk("\n");
593 #else
594 while (count--)
595 writeisac_0(sp->membase, 0x0, *ptr++);
596 #endif
597 writeisac_0(sp->membase, ISAC_CMDR, more ? 0x8 : 0xa);
598 } else {
599 #ifdef DCHAN_VERBOSE
600 int i;
601 writeisac_s(sp->iobase, 0x3e, ptr, count);
602 printk(KERN_DEBUG "fill_fifo ");
603 for (i = 0; i < count; i++)
604 printk("%2x ", ptr[i]);
605 printk("\n");
606 #else
607 writeisac_s(sp->iobase, 0x3e, ptr, count);
608 #endif
609 writeisac_3(sp->iobase, ISAC_CMDR, more ? 0x8 : 0xa);
610 }
611 }
612
613 static int
614 act_wanted(struct IsdnCardState *sp)
615 {
616 struct PStack *st;
617
618 st = sp->stlist;
619 while (st)
620 if (st->l1.act_state)
621 return (!0);
622 else
623 st = st->next;
624 return (0);
625 }
626
627 static void
628 ph_command(struct IsdnCardState *sp, unsigned int command)
629 {
630 printk(KERN_DEBUG "ph_command %d\n", command);
631 WRITEISAC(sp->membase, sp->iobase, ISAC_CIX0, (command << 2) | 3);
632 }
633
634 static void
635 isac_new_ph(struct IsdnCardState *sp)
636 {
637 int enq;
638
639 enq = act_wanted(sp);
640
641 switch (sp->ph_state) {
642 case (0):
643 case (6):
644 if (enq)
645 ph_command(sp, 0);
646 else
647 ph_command(sp, 15);
648 break;
649 case (7):
650 if (enq)
651 ph_command(sp, 9);
652 break;
653 case (12):
654 case (13):
655 sp->ph_active = 5;
656 isac_sched_event(sp, ISAC_PHCHANGE);
657 if (!sp->xmtibh)
658 if (!BufQueueUnlink(&sp->xmtibh, &sp->sq))
659 sp->sendptr = 0;
660 if (sp->xmtibh)
661 fill_fifo(sp);
662 break;
663 case (4):
664 case (8):
665 break;
666 default:
667 sp->ph_active = 0;
668 break;
669 }
670 }
671
672 static void
673 teles_interrupt(int intno, void *dev_id, struct pt_regs *regs)
674 {
675 byte val, val2, r;
676 struct IsdnCardState *sp;
677 unsigned int count;
678 struct HscxState *hsp;
679
680 sp = (struct IsdnCardState *) irq2dev_map[intno];
681
682 if (!sp) {
683 printk(KERN_WARNING "Teles: Spurious interrupt!\n");
684 return;
685 }
686 val = READHSCX(sp->membase, sp->iobase, 1, HSCX_ISTA);
687
688 if (val & 0x01) {
689 hsp = sp->hs + 1;
690 printk(KERN_WARNING "HSCX B EXIR %x xmitbh %lx rcvibh %lx\n",
691 READHSCX(sp->membase, sp->iobase, 1, HSCX_EXIR),
692 (long) hsp->xmtibh,
693 (long) hsp->rcvibh);
694 }
695 if (val & 0xf8) {
696 if (sp->debug)
697 printk(KERN_DEBUG "HSCX B interrupt %x\n", val);
698 hscx_interrupt(sp, val, 1);
699 }
700 if (val & 0x02) {
701 printk(KERN_WARNING "HSCX A EXIR %x\n",
702 READHSCX(sp->membase, sp->iobase, 0, HSCX_EXIR));
703 }
704
705
706 if (sp->membase) {
707 if (val & 0x04) {
708 val = readhscx_0(sp->membase, 0, HSCX_ISTA);
709 if (sp->debug)
710 printk(KERN_DEBUG "HSCX A interrupt %x\n",
711 val);
712 hscx_interrupt(sp, val, 0);
713 }
714 } else {
715 val2 = readhscx_3(sp->iobase, 0, HSCX_ISTA);
716 if (sp->debug)
717 printk(KERN_DEBUG "HSCX A ISTA %x\n", val2);
718 if (val & 0x04) {
719 if (sp->debug)
720 printk(KERN_DEBUG "HSCX A interrupt %x\n",
721 val2);
722 hscx_interrupt(sp, val2, 0);
723 }
724 }
725
726
727 val = READISAC(sp->membase, sp->iobase, ISAC_ISTA);
728
729 if (sp->debug)
730 printk(KERN_DEBUG "ISAC interrupt %x\n", val);
731
732 if (val & 0x80) {
733
734 r = READISAC(sp->membase, sp->iobase, ISAC_RSTA);
735 if ((r & 0x70) != 0x20) {
736 if (r & 0x40)
737 printk(KERN_WARNING "Teles: ISAC RDO\n");
738 if (!r & 0x20)
739 printk(KERN_WARNING "Teles: ISAC CRC error\n");
740 if (sp->rcvibh)
741 BufPoolRelease(sp->rcvibh);
742 sp->rcvibh = NULL;
743 WRITEISAC(sp->membase, sp->iobase, ISAC_CMDR, 0x80);
744 goto afterRME;
745 }
746 if (!sp->rcvibh)
747 if (BufPoolGet(&(sp->rcvibh), &(sp->rbufpool),
748 GFP_ATOMIC,
749 (void *) 1, 3)) {
750 printk(KERN_WARNING
751 "ISAC RME out of buffers!\n");
752 WRITEISAC(sp->membase, sp->iobase,
753 ISAC_CMDR, 0x80);
754 goto afterRME;
755 } else
756 sp->rcvptr = 0;
757
758 count = READISAC(sp->membase, sp->iobase, ISAC_RBCL) & 0x1f;
759 if (count == 0)
760 count = 32;
761 empty_fifo(sp, count);
762 sp->rcvibh->datasize = sp->rcvptr;
763 BufQueueLink(&(sp->rq), sp->rcvibh);
764 sp->rcvibh = NULL;
765 isac_sched_event(sp, ISAC_RCVBUFREADY);
766 }
767 afterRME:
768 if (val & 0x40) {
769 if (!sp->rcvibh)
770 if (BufPoolGet(&(sp->rcvibh), &(sp->rbufpool),
771 GFP_ATOMIC,
772 (void *) 1, 4)) {
773 printk(KERN_WARNING
774 "ISAC RME out of buffers!\n");
775 WRITEISAC(sp->membase, sp->iobase,
776 ISAC_CMDR, 0x80);
777 goto afterRPF;
778 } else
779 sp->rcvptr = 0;
780 empty_fifo(sp, 32);
781 }
782 afterRPF:
783 if (val & 0x20) {
784 }
785 if (val & 0x10) {
786 if (sp->xmtibh)
787 if (sp->xmtibh->datasize > sp->sendptr) {
788 fill_fifo(sp);
789 goto afterXPR;
790 } else {
791 if (sp->releasebuf)
792 BufPoolRelease(sp->xmtibh);
793 sp->xmtibh = NULL;
794 sp->sendptr = 0;
795 }
796 if (!BufQueueUnlink(&sp->xmtibh, &sp->sq)) {
797 sp->releasebuf = !0;
798 fill_fifo(sp);
799 } else
800 isac_sched_event(sp, ISAC_XMTBUFREADY);
801 }
802 afterXPR:
803 if (val & 0x04) {
804 sp->ph_state = (READISAC(sp->membase, sp->iobase, ISAC_CIX0)
805 >> 2) & 0xf;
806 printk(KERN_DEBUG "l1state %d\n", sp->ph_state);
807 isac_new_ph(sp);
808 }
809 if (sp->membase) {
810 writeisac_0(sp->membase, ISAC_MASK, 0xFF);
811 writehscx_0(sp->membase, 0, HSCX_MASK, 0xFF);
812 writehscx_0(sp->membase, 1, HSCX_MASK, 0xFF);
813 writeisac_0(sp->membase, ISAC_MASK, 0x0);
814 writehscx_0(sp->membase, 0, HSCX_MASK, 0x0);
815 writehscx_0(sp->membase, 1, HSCX_MASK, 0x0);
816 } else {
817 writeisac_3(sp->iobase, ISAC_MASK, 0xFF);
818 writehscx_3(sp->iobase, 0, HSCX_MASK, 0xFF);
819 writehscx_3(sp->iobase, 1, HSCX_MASK, 0xFF);
820 writeisac_3(sp->iobase, ISAC_MASK, 0x0);
821 writehscx_3(sp->iobase, 0, HSCX_MASK, 0x0);
822 writehscx_3(sp->iobase, 1, HSCX_MASK, 0x0);
823 }
824 }
825
826
827
828
829
830 static void
831 act_ivated(struct IsdnCardState *sp)
832 {
833 struct PStack *st;
834
835 st = sp->stlist;
836 while (st) {
837 if (st->l1.act_state == 1) {
838 st->l1.act_state = 2;
839 st->l1.l1man(st, PH_ACTIVATE, NULL);
840 }
841 st = st->next;
842 }
843 }
844
845 static void
846 process_new_ph(struct IsdnCardState *sp)
847 {
848 if (sp->ph_active == 5)
849 act_ivated(sp);
850 }
851
852 static void
853 process_xmt(struct IsdnCardState *sp)
854 {
855 struct PStack *stptr;
856
857 if (sp->xmtibh)
858 return;
859
860 stptr = sp->stlist;
861 while (stptr != NULL)
862 if (stptr->l1.requestpull) {
863 stptr->l1.requestpull = 0;
864 stptr->l1.l1l2(stptr, PH_PULL_ACK, NULL);
865 break;
866 } else
867 stptr = stptr->next;
868 }
869
870 static void
871 process_rcv(struct IsdnCardState *sp)
872 {
873 struct BufHeader *ibh, *cibh;
874 struct PStack *stptr;
875 byte *ptr;
876 int found, broadc;
877 char tmp[64];
878
879 while (!BufQueueUnlink(&ibh, &sp->rq)) {
880 stptr = sp->stlist;
881 ptr = DATAPTR(ibh);
882 broadc = (ptr[1] >> 1) == 127;
883
884 if (broadc && sp->dlogflag && (!(ptr[0] >> 2)))
885 dlogframe(sp, ptr + 3, ibh->datasize - 3,
886 "Q.931 frame network->user broadcast");
887
888 if (broadc) {
889 while (stptr != NULL) {
890 if ((ptr[0] >> 2) == stptr->l2.sap)
891 if (!BufPoolGet(&cibh, &sp->rbufpool, GFP_ATOMIC,
892 (void *) 1, 5)) {
893 memcpy(DATAPTR(cibh), DATAPTR(ibh), ibh->datasize);
894 cibh->datasize = ibh->datasize;
895 stptr->l1.l1l2(stptr, PH_DATA, cibh);
896 } else
897 printk(KERN_WARNING "isdn broadcast buffer shortage\n");
898 stptr = stptr->next;
899 }
900 BufPoolRelease(ibh);
901 } else {
902 found = 0;
903 while (stptr != NULL)
904 if (((ptr[0] >> 2) == stptr->l2.sap) &&
905 ((ptr[1] >> 1) == stptr->l2.tei)) {
906 stptr->l1.l1l2(stptr, PH_DATA, ibh);
907 found = !0;
908 break;
909 } else
910 stptr = stptr->next;
911 if (!found) {
912
913
914
915
916
917 if ((!(ptr[0] >> 2)) && (!(ptr[2] & 0x01))) {
918 sprintf(tmp, "Q.931 frame network->user with tei %d (not for us)", ptr[1] >> 1);
919 dlogframe(sp, ptr + 4, ibh->datasize - 4, tmp);
920 }
921 BufPoolRelease(ibh);
922 }
923 }
924
925 }
926
927 }
928
929 static void
930 isac_bh(struct IsdnCardState *sp)
931 {
932 if (!sp)
933 return;
934
935 if (clear_bit(ISAC_PHCHANGE, &sp->event))
936 process_new_ph(sp);
937 if (clear_bit(ISAC_RCVBUFREADY, &sp->event))
938 process_rcv(sp);
939 if (clear_bit(ISAC_XMTBUFREADY, &sp->event))
940 process_xmt(sp);
941 }
942
943
944 static void
945 hscx_process_xmt(struct HscxState *hsp)
946 {
947 struct PStack *st = hsp->st;
948
949 if (hsp->xmtibh)
950 return;
951
952 if (st->l1.requestpull) {
953 st->l1.requestpull = 0;
954 st->l1.l1l2(st, PH_PULL_ACK, NULL);
955 }
956 if (!hsp->active)
957 if ((!hsp->xmtibh) && (!hsp->sq.head))
958 modehscx(hsp, 0, 0);
959 }
960
961 static void
962 hscx_process_rcv(struct HscxState *hsp)
963 {
964 struct BufHeader *ibh;
965
966 #ifdef DEBUG_MAGIC
967 if (hsp->magic != 301270) {
968 printk(KERN_DEBUG "hscx_process_rcv magic not 301270\n");
969 return;
970 }
971 #endif
972 while (!BufQueueUnlink(&ibh, &hsp->rq)) {
973 hsp->st->l1.l1l2(hsp->st, PH_DATA, ibh);
974 }
975 }
976
977 static void
978 hscx_bh(struct HscxState *hsp)
979 {
980
981 if (!hsp)
982 return;
983
984 if (clear_bit(HSCX_RCVBUFREADY, &hsp->event))
985 hscx_process_rcv(hsp);
986 if (clear_bit(HSCX_XMTBUFREADY, &hsp->event))
987 hscx_process_xmt(hsp);
988
989 }
990
991
992
993
994
995 static void
996 restart_ph(struct IsdnCardState *sp)
997 {
998 switch (sp->ph_active) {
999 case (0):
1000 if (sp->ph_state == 6)
1001 ph_command(sp, 0);
1002 else
1003 ph_command(sp, 1);
1004 sp->ph_active = 1;
1005 break;
1006 }
1007 }
1008
1009 static void
1010 initisac(byte * cardmem, int iobase)
1011 {
1012 if (cardmem) {
1013 writeisac_0(cardmem, ISAC_MASK, 0xff);
1014 writeisac_0(cardmem, ISAC_ADF2, 0x0);
1015 writeisac_0(cardmem, ISAC_SPCR, 0xa);
1016 writeisac_0(cardmem, ISAC_ADF1, 0x2);
1017 writeisac_0(cardmem, ISAC_STCR, 0x70);
1018 writeisac_0(cardmem, ISAC_MODE, 0xc9);
1019 writeisac_0(cardmem, ISAC_CMDR, 0x41);
1020 writeisac_0(cardmem, ISAC_CIX0, (1 << 2) | 3);
1021 } else {
1022 writeisac_3(iobase, ISAC_MASK, 0xff);
1023 writeisac_3(iobase, ISAC_ADF2, 0x80);
1024 writeisac_3(iobase, ISAC_SQXR, 0x2f);
1025 writeisac_3(iobase, ISAC_SPCR, 0x00);
1026 writeisac_3(iobase, ISAC_ADF1, 0x02);
1027 writeisac_3(iobase, ISAC_STCR, 0x70);
1028 writeisac_3(iobase, ISAC_MODE, 0xc9);
1029 writeisac_3(iobase, ISAC_TIMR, 0x00);
1030 writeisac_3(iobase, ISAC_ADF1, 0x00);
1031 writeisac_3(iobase, ISAC_CMDR, 0x41);
1032 writeisac_3(iobase, ISAC_CIX0, (1 << 2) | 3);
1033 }
1034 }
1035
1036 static int
1037 checkcard(int cardnr)
1038 {
1039 int timout;
1040 byte cfval, val;
1041 struct IsdnCard *card = cards + cardnr;
1042
1043 if (!card->iobase) {
1044 if (card->membase) {
1045 printk(KERN_NOTICE
1046 "Teles 8 assumed, mem: %lx irq: %d proto: %s\n",
1047 (long) card->membase, card->interrupt,
1048 (card->protocol == ISDN_PTYPE_1TR6) ?
1049 "1TR6" : "EDSS1");
1050 printk(KERN_INFO "HSCX version A: %x B:%x\n",
1051 readhscx_0(card->membase, 0, HSCX_VSTR) & 0xf,
1052 readhscx_0(card->membase, 1, HSCX_VSTR) & 0xf);
1053 }
1054 } else {
1055 switch (card->iobase) {
1056 case 0x180:
1057 case 0x280:
1058 case 0x380:
1059 printk(KERN_INFO "teles: port 0x%x specified, assuming 0x%x\n",
1060 card->iobase, (card->iobase | 0xc00));
1061 card->iobase |= 0xc00;
1062 break;
1063 }
1064 if (check_region(card->iobase, 8)) {
1065 printk(KERN_WARNING
1066 "teles: ports %x-%x already in use\n",
1067 card->iobase,
1068 card->iobase + 8 );
1069 return -1;
1070 }
1071 switch (card->interrupt) {
1072 case 2:
1073 cfval = 0x00;
1074 break;
1075 case 3:
1076 cfval = 0x02;
1077 break;
1078 case 4:
1079 cfval = 0x04;
1080 break;
1081 case 5:
1082 cfval = 0x06;
1083 break;
1084 case 10:
1085 cfval = 0x08;
1086 break;
1087 case 11:
1088 cfval = 0x0A;
1089 break;
1090 case 12:
1091 cfval = 0x0C;
1092 break;
1093 case 15:
1094 cfval = 0x0E;
1095 break;
1096 default:
1097 cfval = 0x00;
1098 break;
1099 }
1100 if (card->membase) {
1101 cfval |= (((unsigned int) card->membase >> 9) & 0xF0);
1102
1103 if (bytein(card->iobase + 0) != 0x51) {
1104 printk(KERN_INFO "XXX Byte at %x is %x\n",
1105 card->iobase + 0,
1106 bytein(card->iobase + 0));
1107 return -2;
1108 }
1109 if (bytein(card->iobase + 1) != 0x93) {
1110 printk(KERN_INFO "XXX Byte at %x is %x\n",
1111 card->iobase + 1,
1112 bytein(card->iobase + 1));
1113 return -2;
1114 }
1115 val = bytein(card->iobase + 2);
1116
1117
1118 if (val != 0x1e && val != 0x1f) {
1119 printk(KERN_INFO "XXX Byte at %x is %x\n",
1120 card->iobase + 2,
1121 bytein(card->iobase + 2));
1122 return -2;
1123 }
1124 }
1125 request_region(card->iobase, 8, "teles");
1126 cli();
1127 timout = jiffies + (HZ / 10) + 1;
1128 byteout(card->iobase + 4, cfval);
1129 sti();
1130 while (jiffies <= timout);
1131
1132 cli();
1133 timout = jiffies + (HZ / 10) + 1;
1134 byteout(card->iobase + 4, cfval | 1);
1135 sti();
1136 while (jiffies <= timout);
1137
1138 if (card->membase)
1139 printk(KERN_NOTICE
1140 "Teles 16.0 found, io: %x mem: %lx irq: %d proto: %s\n",
1141 card->iobase, (long) card->membase,
1142 card->interrupt,
1143 (card->protocol == ISDN_PTYPE_1TR6) ?
1144 "1TR6" : "EDSS1");
1145 else
1146 printk(KERN_NOTICE
1147 "Teles 16.3 found, io: %x irq: %d proto: %s\n",
1148 card->iobase, card->interrupt,
1149 (card->protocol == ISDN_PTYPE_1TR6) ?
1150 "1TR6" : "EDSS1");
1151 printk(KERN_INFO "HSCX version A:%x B:%x\n",
1152 READHSCX(card->membase, card->iobase, 0,
1153 HSCX_VSTR) & 0xf,
1154 READHSCX(card->membase, card->iobase, 1,
1155 HSCX_VSTR) & 0xf);
1156
1157 }
1158 if (card->membase) {
1159 cli();
1160 timout = jiffies + (HZ / 5) + 1;
1161 *(byte *) (card->membase + 0x80) = 0;
1162 sti();
1163 while (jiffies <= timout);
1164
1165 cli();
1166 *(byte *) (card->membase + 0x80) = 1;
1167 timout = jiffies + (HZ / 5) + 1;
1168 sti();
1169 while (jiffies <= timout);
1170 }
1171 return (0);
1172 }
1173
1174 void
1175 modehscx(struct HscxState *hs, int mode,
1176 int ichan)
1177 {
1178 struct IsdnCardState *sp = hs->sp;
1179 int hscx = hs->hscx;
1180
1181 printk(KERN_DEBUG "modehscx hscx %d mode %d ichan %d\n",
1182 hscx, mode, ichan);
1183
1184 if (hscx == 0)
1185 ichan = 1 - ichan;
1186
1187 if (sp->membase) {
1188 writehscx_0(sp->membase, hscx, HSCX_CCR1, 0x85);
1189 writehscx_0(sp->membase, hscx, HSCX_XAD1, 0xFF);
1190 writehscx_0(sp->membase, hscx, HSCX_XAD2, 0xFF);
1191 writehscx_0(sp->membase, hscx, HSCX_RAH2, 0xFF);
1192 writehscx_0(sp->membase, hscx, HSCX_XBCH, 0x0);
1193
1194 switch (mode) {
1195 case (0):
1196 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1197 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0xff);
1198 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0xff);
1199 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1200 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1201 writehscx_0(sp->membase, hscx, HSCX_MODE, 0x84);
1202 break;
1203 case (1):
1204 if (ichan == 0) {
1205 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1206 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x7);
1207 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x7);
1208 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1209 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1210 } else {
1211 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1212 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x3);
1213 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x3);
1214 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1215 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1216 }
1217 writehscx_0(sp->membase, hscx, HSCX_MODE, 0xe4);
1218 writehscx_0(sp->membase, hscx, HSCX_CMDR, 0x41);
1219 break;
1220 case (2):
1221 if (ichan == 0) {
1222 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1223 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x7);
1224 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x7);
1225 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1226 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1227 } else {
1228 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1229 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x3);
1230 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x3);
1231 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1232 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1233 }
1234 writehscx_0(sp->membase, hscx, HSCX_MODE, 0x8c);
1235 writehscx_0(sp->membase, hscx, HSCX_CMDR, 0x41);
1236 break;
1237 }
1238 writehscx_0(sp->membase, hscx, HSCX_ISTA, 0x00);
1239 } else {
1240 writehscx_3(sp->iobase, hscx, HSCX_CCR1, 0x85);
1241 writehscx_3(sp->iobase, hscx, HSCX_XAD1, 0xFF);
1242 writehscx_3(sp->iobase, hscx, HSCX_XAD2, 0xFF);
1243 writehscx_3(sp->iobase, hscx, HSCX_RAH2, 0xFF);
1244 writehscx_3(sp->iobase, hscx, HSCX_XBCH, 0x00);
1245 writehscx_3(sp->iobase, hscx, HSCX_RLCR, 0x00);
1246
1247 switch (mode) {
1248 case (0):
1249 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1250 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0xff);
1251 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0xff);
1252 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1253 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1254 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0x84);
1255 break;
1256 case (1):
1257 if (ichan == 0) {
1258 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1259 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x2f);
1260 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x2f);
1261 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1262 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1263 } else {
1264 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1265 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x3);
1266 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x3);
1267 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1268 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1269 }
1270 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0xe4);
1271 writehscx_3(sp->iobase, hscx, HSCX_CMDR, 0x41);
1272 break;
1273 case (2):
1274 if (ichan == 0) {
1275 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1276 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x2f);
1277 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x2f);
1278 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1279 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1280 } else {
1281 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1282 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x3);
1283 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x3);
1284 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1285 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1286 }
1287 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0x8c);
1288 writehscx_3(sp->iobase, hscx, HSCX_CMDR, 0x41);
1289 break;
1290 }
1291 writehscx_3(sp->iobase, hscx, HSCX_ISTA, 0x00);
1292 }
1293 }
1294
1295 void
1296 teles_addlist(struct IsdnCardState *sp,
1297 struct PStack *st)
1298 {
1299 st->next = sp->stlist;
1300 sp->stlist = st;
1301 }
1302
1303 void
1304 teles_rmlist(struct IsdnCardState *sp,
1305 struct PStack *st)
1306 {
1307 struct PStack *p;
1308
1309 if (sp->stlist == st)
1310 sp->stlist = st->next;
1311 else {
1312 p = sp->stlist;
1313 while (p)
1314 if (p->next == st) {
1315 p->next = st->next;
1316 return;
1317 } else
1318 p = p->next;
1319 }
1320 }
1321
1322
1323 static void
1324 teles_l2l1(struct PStack *st, int pr,
1325 struct BufHeader *ibh)
1326 {
1327 struct IsdnCardState *sp = (struct IsdnCardState *)
1328 st->l1.hardware;
1329
1330
1331 switch (pr) {
1332 case (PH_DATA):
1333 if (sp->xmtibh)
1334 BufQueueLink(&sp->sq, ibh);
1335 else {
1336 sp->xmtibh = ibh;
1337 sp->sendptr = 0;
1338 sp->releasebuf = !0;
1339 fill_fifo(sp);
1340 }
1341 break;
1342 case (PH_DATA_PULLED):
1343 if (sp->xmtibh) {
1344 printk(KERN_DEBUG "teles_l2l1: this shouldn't happen\n");
1345 break;
1346 }
1347 sp->xmtibh = ibh;
1348 sp->sendptr = 0;
1349 sp->releasebuf = 0;
1350 fill_fifo(sp);
1351 break;
1352 case (PH_REQUEST_PULL):
1353 if (!sp->xmtibh) {
1354 st->l1.requestpull = 0;
1355 st->l1.l1l2(st, PH_PULL_ACK, NULL);
1356 } else
1357 st->l1.requestpull = !0;
1358 break;
1359 }
1360 }
1361
1362 static void
1363 check_ph_act(struct IsdnCardState *sp)
1364 {
1365 struct PStack *st = sp->stlist;
1366
1367 while (st) {
1368 if (st->l1.act_state)
1369 return;
1370 st = st->next;
1371 }
1372 sp->ph_active = 0;
1373 }
1374
1375 static void
1376 teles_manl1(struct PStack *st, int pr,
1377 void *arg)
1378 {
1379 struct IsdnCardState *sp = (struct IsdnCardState *)
1380 st->l1.hardware;
1381 long flags;
1382
1383 switch (pr) {
1384 case (PH_ACTIVATE):
1385 save_flags(flags);
1386 cli();
1387 if (sp->ph_active == 5) {
1388 st->l1.act_state = 2;
1389 restore_flags(flags);
1390 st->l1.l1man(st, PH_ACTIVATE, NULL);
1391 } else {
1392 st->l1.act_state = 1;
1393 if (sp->ph_active == 0)
1394 restart_ph(sp);
1395 restore_flags(flags);
1396 }
1397 break;
1398 case (PH_DEACTIVATE):
1399 st->l1.act_state = 0;
1400 check_ph_act(sp);
1401 break;
1402 }
1403 }
1404
1405 static void
1406 teles_l2l1discardq(struct PStack *st, int pr,
1407 void *heldby, int releasetoo)
1408 {
1409 struct IsdnCardState *sp = (struct IsdnCardState *) st->l1.hardware;
1410
1411 #ifdef DEBUG_MAGIC
1412 if (sp->magic != 301271) {
1413 printk(KERN_DEBUG "isac_discardq magic not 301271\n");
1414 return;
1415 }
1416 #endif
1417
1418 BufQueueDiscard(&sp->sq, pr, heldby, releasetoo);
1419 }
1420
1421 void
1422 setstack_teles(struct PStack *st, struct IsdnCardState *sp)
1423 {
1424 st->l1.hardware = sp;
1425 st->l1.sbufpool = &(sp->sbufpool);
1426 st->l1.rbufpool = &(sp->rbufpool);
1427 st->l1.smallpool = &(sp->smallpool);
1428 st->protocol = sp->teistack->protocol;
1429
1430 setstack_tei(st);
1431
1432 st->l1.stlistp = &(sp->stlist);
1433 st->l1.act_state = 0;
1434 st->l2.l2l1 = teles_l2l1;
1435 st->l2.l2l1discardq = teles_l2l1discardq;
1436 st->ma.manl1 = teles_manl1;
1437 st->l1.requestpull = 0;
1438 }
1439
1440 void
1441 init_hscxstate(struct IsdnCardState *sp,
1442 int hscx)
1443 {
1444 struct HscxState *hsp = sp->hs + hscx;
1445
1446 hsp->sp = sp;
1447 hsp->hscx = hscx;
1448 hsp->membase = sp->membase;
1449 hsp->iobase = sp->iobase;
1450
1451 hsp->tqueue.next = 0;
1452 hsp->tqueue.sync = 0;
1453 hsp->tqueue.routine = (void *) (void *) hscx_bh;
1454 hsp->tqueue.data = hsp;
1455
1456 hsp->inuse = 0;
1457 hsp->init = 0;
1458 hsp->active = 0;
1459
1460 #ifdef DEBUG_MAGIC
1461 hsp->magic = 301270;
1462 #endif
1463 }
1464
1465 void
1466 initcard(int cardnr)
1467 {
1468 struct IsdnCardState *sp;
1469 struct IsdnCard *card = cards + cardnr;
1470
1471 sp = (struct IsdnCardState *)
1472 Smalloc(sizeof(struct IsdnCardState), GFP_KERNEL,
1473 "struct IsdnCardState");
1474
1475 sp->membase = card->membase;
1476 sp->iobase = card->iobase;
1477 sp->cardnr = cardnr;
1478
1479 BufPoolInit(&sp->sbufpool, ISAC_SBUF_ORDER, ISAC_SBUF_BPPS,
1480 ISAC_SBUF_MAXPAGES);
1481 BufPoolInit(&sp->rbufpool, ISAC_RBUF_ORDER, ISAC_RBUF_BPPS,
1482 ISAC_RBUF_MAXPAGES);
1483 BufPoolInit(&sp->smallpool, ISAC_SMALLBUF_ORDER, ISAC_SMALLBUF_BPPS,
1484 ISAC_SMALLBUF_MAXPAGES);
1485
1486 sp->dlogspace = Smalloc(4096, GFP_KERNEL, "dlogspace");
1487
1488 initisac(card->membase, card->iobase);
1489
1490 sp->rcvibh = NULL;
1491 sp->rcvptr = 0;
1492 sp->xmtibh = NULL;
1493 sp->sendptr = 0;
1494 sp->event = 0;
1495 sp->tqueue.next = 0;
1496 sp->tqueue.sync = 0;
1497 sp->tqueue.routine = (void *) (void *) isac_bh;
1498 sp->tqueue.data = sp;
1499
1500 BufQueueInit(&sp->rq);
1501 BufQueueInit(&sp->sq);
1502
1503 sp->stlist = NULL;
1504
1505 sp->ph_active = 0;
1506
1507 sp->dlogflag = 0;
1508 sp->debug = 0;
1509
1510 sp->releasebuf = 0;
1511 #ifdef DEBUG_MAGIC
1512 sp->magic = 301271;
1513 #endif
1514
1515 cards[sp->cardnr].sp = sp;
1516
1517 init_hscxstate(sp, 0);
1518 init_hscxstate(sp, 1);
1519
1520 modehscx(sp->hs, 0, 0);
1521 modehscx(sp->hs + 1, 0, 0);
1522
1523 WRITEISAC(sp->membase, sp->iobase, ISAC_MASK, 0x0);
1524 }
1525
1526 static int
1527 get_irq(int cardnr)
1528 {
1529 struct IsdnCard *card = cards + cardnr;
1530 long flags;
1531
1532 save_flags(flags);
1533 cli();
1534 if (request_irq(card->interrupt, &teles_interrupt,
1535 SA_INTERRUPT, "teles", NULL)) {
1536 printk(KERN_WARNING "Teles couldn't get interrupt %d\n",
1537 card->interrupt);
1538 restore_flags(flags);
1539 return (!0);
1540 }
1541 irq2dev_map[card->interrupt] = (void *) card->sp;
1542 restore_flags(flags);
1543 return (0);
1544 }
1545
1546 static void
1547 release_irq(int cardnr)
1548 {
1549 struct IsdnCard *card = cards + cardnr;
1550
1551 irq2dev_map[card->interrupt] = NULL;
1552 free_irq(card->interrupt, NULL);
1553 }
1554
1555 void
1556 close_hscxstate(struct HscxState *hs)
1557 {
1558 modehscx(hs, 0, 0);
1559 hs->inuse = 0;
1560
1561 if (hs->init) {
1562 BufPoolFree(&hs->smallpool);
1563 BufPoolFree(&hs->rbufpool);
1564 BufPoolFree(&hs->sbufpool);
1565 }
1566 hs->init = 0;
1567 }
1568
1569 void
1570 closecard(int cardnr)
1571 {
1572 struct IsdnCardState *sp = cards[cardnr].sp;
1573
1574 cards[cardnr].sp = NULL;
1575
1576 Sfree(sp->dlogspace);
1577
1578 BufPoolFree(&sp->smallpool);
1579 BufPoolFree(&sp->rbufpool);
1580 BufPoolFree(&sp->sbufpool);
1581
1582 close_hscxstate(sp->hs + 1);
1583 close_hscxstate(sp->hs);
1584
1585 if (cards[cardnr].iobase)
1586 release_region(cards[cardnr].iobase, 8);
1587
1588 Sfree((void *) sp);
1589 }
1590
1591 void
1592 teles_shiftcards(int idx)
1593 {
1594 int i;
1595
1596 for (i = idx; i < 15; i++)
1597 memcpy(&cards[i],&cards[i+1],sizeof(cards[i]));
1598 }
1599
1600 int
1601 teles_inithardware(void)
1602 {
1603 int foundcards = 0;
1604 int i = 0;
1605
1606 while (i < nrcards) {
1607 if (!cards[i].protocol)
1608 break;
1609 switch (checkcard(i)) {
1610 case (0):
1611 initcard(i);
1612 if (get_irq(i)) {
1613 closecard(i);
1614 teles_shiftcards(i);
1615 } else {
1616 foundcards++;
1617 i++;
1618 }
1619 break;
1620 case (-1):
1621 teles_shiftcards(i);
1622 break;
1623 case (-2):
1624 release_region(cards[i].iobase, 8);
1625 teles_shiftcards(i);
1626 printk(KERN_WARNING "NO Teles card found at 0x%x!\n", cards[i].iobase);
1627 break;
1628 }
1629 }
1630 return foundcards;
1631 }
1632
1633 void
1634 teles_closehardware(void)
1635 {
1636 int i;
1637
1638 for (i = 0; i < nrcards; i++)
1639 if (cards[i].sp) {
1640 release_irq(i);
1641 closecard(i);
1642 }
1643 }
1644
1645 static void
1646 hscx_l2l1(struct PStack *st, int pr,
1647 struct BufHeader *ibh)
1648 {
1649 struct IsdnCardState *sp = (struct IsdnCardState *)
1650 st->l1.hardware;
1651 struct HscxState *hsp = sp->hs + st->l1.hscx;
1652
1653 switch (pr) {
1654 case (PH_DATA):
1655 if (hsp->xmtibh)
1656 BufQueueLink(&hsp->sq, ibh);
1657 else {
1658 hsp->xmtibh = ibh;
1659 hsp->sendptr = 0;
1660 hsp->releasebuf = !0;
1661 hscx_fill_fifo(hsp);
1662 }
1663 break;
1664 case (PH_DATA_PULLED):
1665 if (hsp->xmtibh) {
1666 printk(KERN_DEBUG "hscx_l2l1: this shouldn't happen\n");
1667 break;
1668 }
1669 hsp->xmtibh = ibh;
1670 hsp->sendptr = 0;
1671 hsp->releasebuf = 0;
1672 hscx_fill_fifo(hsp);
1673 break;
1674 case (PH_REQUEST_PULL):
1675 if (!hsp->xmtibh) {
1676 st->l1.requestpull = 0;
1677 st->l1.l1l2(st, PH_PULL_ACK, NULL);
1678 } else
1679 st->l1.requestpull = !0;
1680 break;
1681 }
1682
1683 }
1684
1685 extern struct IsdnBuffers *tracebuf;
1686
1687 static void
1688 hscx_l2l1discardq(struct PStack *st, int pr, void *heldby,
1689 int releasetoo)
1690 {
1691 struct IsdnCardState *sp = (struct IsdnCardState *)
1692 st->l1.hardware;
1693 struct HscxState *hsp = sp->hs + st->l1.hscx;
1694
1695 #ifdef DEBUG_MAGIC
1696 if (hsp->magic != 301270) {
1697 printk(KERN_DEBUG "hscx_discardq magic not 301270\n");
1698 return;
1699 }
1700 #endif
1701
1702 BufQueueDiscard(&hsp->sq, pr, heldby, releasetoo);
1703 }
1704
1705 static int
1706 open_hscxstate(struct IsdnCardState *sp,
1707 int hscx)
1708 {
1709 struct HscxState *hsp = sp->hs + hscx;
1710
1711 if (!hsp->init) {
1712 BufPoolInit(&hsp->sbufpool, HSCX_SBUF_ORDER, HSCX_SBUF_BPPS,
1713 HSCX_SBUF_MAXPAGES);
1714 BufPoolInit(&hsp->rbufpool, HSCX_RBUF_ORDER, HSCX_RBUF_BPPS,
1715 HSCX_RBUF_MAXPAGES);
1716 BufPoolInit(&hsp->smallpool, HSCX_SMALLBUF_ORDER, HSCX_SMALLBUF_BPPS,
1717 HSCX_SMALLBUF_MAXPAGES);
1718 }
1719 hsp->init = !0;
1720
1721 BufQueueInit(&hsp->rq);
1722 BufQueueInit(&hsp->sq);
1723
1724 hsp->releasebuf = 0;
1725 hsp->rcvibh = NULL;
1726 hsp->xmtibh = NULL;
1727 hsp->rcvptr = 0;
1728 hsp->sendptr = 0;
1729 hsp->event = 0;
1730 return (0);
1731 }
1732
1733 static void
1734 hscx_manl1(struct PStack *st, int pr,
1735 void *arg)
1736 {
1737 struct IsdnCardState *sp = (struct IsdnCardState *)
1738 st->l1.hardware;
1739 struct HscxState *hsp = sp->hs + st->l1.hscx;
1740
1741 switch (pr) {
1742 case (PH_ACTIVATE):
1743 hsp->active = !0;
1744 modehscx(hsp, st->l1.hscxmode, st->l1.hscxchannel);
1745 st->l1.l1man(st, PH_ACTIVATE, NULL);
1746 break;
1747 case (PH_DEACTIVATE):
1748 if (!hsp->xmtibh)
1749 modehscx(hsp, 0, 0);
1750
1751 hsp->active = 0;
1752 break;
1753 }
1754 }
1755
1756 int
1757 setstack_hscx(struct PStack *st, struct HscxState *hs)
1758 {
1759 if (open_hscxstate(st->l1.hardware, hs->hscx))
1760 return (-1);
1761
1762 st->l1.hscx = hs->hscx;
1763 st->l2.l2l1 = hscx_l2l1;
1764 st->ma.manl1 = hscx_manl1;
1765 st->l2.l2l1discardq = hscx_l2l1discardq;
1766
1767 st->l1.sbufpool = &hs->sbufpool;
1768 st->l1.rbufpool = &hs->rbufpool;
1769 st->l1.smallpool = &hs->smallpool;
1770 st->l1.act_state = 0;
1771 st->l1.requestpull = 0;
1772
1773 hs->st = st;
1774 return (0);
1775 }
1776
1777 void
1778 teles_reportcard(int cardnr)
1779 {
1780
1781 printk(KERN_DEBUG "teles_reportcard\n");
1782
1783 }
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