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1 /* esp.h: Defines and structures for the Sparc ESP (Enhanced SCSI
2 * Processor) driver under Linux.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7 #ifndef _SPARC_ESP_H
8 #define _SPARC_ESP_H
9
10 /* For dvma controller register definitions. */
11 #include <asm/dma.h>
12
13 /* The ESP SCSI controllers have their register sets in three
14 * "classes":
15 *
16 * 1) Registers which are both read and write.
17 * 2) Registers which are read only.
18 * 3) Registers which are write only.
19 *
20 * Yet, they all live within the same IO space.
21 */
22
23 /* All the ESP registers are one byte each and are accessed longwords
24 * apart with a big-endian ordering to the bytes.
25 */
26
27 struct Sparc_ESP_regs {
28 /* Access Description Offset */
29 volatile unchar esp_tclow; /* rw Low bits of the transfer count 0x00 */
30 unchar tlpad1[3];
31 volatile unchar esp_tcmed; /* rw Mid bits of the transfer count 0x04 */
32 unchar fdpad[3];
33 volatile unchar esp_fdata; /* rw FIFO data bits 0x08 */
34 unchar cbpad[3];
35 volatile unchar esp_cmd; /* rw SCSI command bits 0x0c */
36 unchar stpad[3];
37 volatile unchar esp_status; /* ro ESP status register 0x10 */
38 #define esp_busid esp_status /* wo Bus ID for select/reselect 0x10 */
39 unchar irqpd[3];
40 volatile unchar esp_intrpt; /* ro Kind of interrupt 0x14 */
41 #define esp_timeo esp_intrpt /* wo Timeout value for select/resel 0x14 */
42 unchar sspad[3];
43 volatile unchar esp_sstep; /* ro Sequence step register 0x18 */
44 #define esp_stp esp_sstep /* wo Transfer period per sync 0x18 */
45 unchar ffpad[3];
46 volatile unchar esp_fflags; /* ro Bits of current FIFO info 0x1c */
47 #define esp_soff esp_fflags /* wo Sync offset 0x1c */
48 unchar cf1pd[3];
49 volatile unchar esp_cfg1; /* rw First configuration register 0x20 */
50 unchar cfpad[3];
51 volatile unchar esp_cfact; /* wo Clock conversion factor 0x24 */
52 unchar ctpad[3];
53 volatile unchar esp_ctest; /* wo Chip test register 0x28 */
54 unchar cf2pd[3];
55 volatile unchar esp_cfg2; /* rw Second configuration register 0x2c */
56 unchar cf3pd[3];
57
58 /* The following is only found on the 53C9X series SCSI chips */
59 volatile unchar esp_cfg3; /* rw Third configuration register 0x30 */
60 unchar thpd[7];
61
62 /* The following is found on all chips except the NCR53C90 (ESP100) */
63 volatile unchar esp_tchi; /* rw High bits of transfer count 0x38 */
64 #define esp_uid esp_tchi /* ro Unique ID code 0x38 */
65 unchar fgpad[3];
66 volatile unchar esp_fgrnd; /* rw Data base for fifo 0x3c */
67 };
68
69 /* Various revisions of the ESP board. */
70 enum esp_rev {
71 esp100 = 0x00, /* NCR53C90 */
72 esp100a = 0x01, /* NCR53C90A */
73 esp236 = 0x02,
74 fas236 = 0x03,
75 fas100a = 0x04,
76 fast = 0x05,
77 espunknown = 0x06
78 };
79
80 /* We get one of these for each ESP probed. */
81 struct Sparc_ESP {
82 struct Sparc_ESP *next; /* Next ESP on probed or NULL */
83 struct Sparc_ESP_regs *eregs; /* All esp registers */
84 struct Linux_SBus_DMA *dma; /* Who I do transfers with. */
85 struct sparc_dma_registers *dregs; /* And his registers. */
86 struct Scsi_Host *ehost; /* Backpointer to SCSI Host */
87
88 struct linux_sbus_device *edev; /* Pointer to SBus entry */
89 char prom_name[64]; /* Name of ESP device from prom */
90 int prom_node; /* Prom node where ESP found */
91 int esp_id; /* Same as esphost->host_id */
92
93 /* ESP Configuration Registers */
94 unsigned char config1; /* Copy of the 1st config register */
95 unsigned char config2; /* Copy of the 2nd config register */
96 unsigned char config3[8]; /* Copy of the 3rd config register */
97
98 /* The current command we are sending to the ESP chip. This esp_command
99 * ptr needs to be mapped in DVMA area so we can send commands and read
100 * from the ESP fifo without burning precious CPU cycles. Programmed I/O
101 * sucks when we have the DVMA to do it for us.
102 */
103 volatile unchar *esp_command; /* Location of command */
104 int esp_clen; /* Length of this command */
105
106 /* To hold onto the dvma buffer ptr. */
107 char *dvma_hold;
108
109 /* The following are used to determine the cause of an IRQ. Upon every
110 * IRQ entry we synchronize these with the hardware registers.
111 */
112 unchar ireg; /* Copy of ESP interrupt register */
113 unchar sreg; /* Same for ESP status register */
114 unchar seqreg; /* The ESP sequence register */
115
116 /* Clock periods, frequencies, synchronization, etc. */
117 unsigned int cfreq; /* Clock frequency in HZ */
118 unsigned int cfact; /* Clock conversion factor */
119 unsigned int ccycle; /* One ESP clock cycle */
120 unsigned int ctick; /* One ESP clock time */
121 unsigned int sync_defp; /* Default negotiation period */
122
123 /* Misc. info about this ESP */
124 enum esp_rev erev; /* ESP revision */
125 int irq; /* SBus IRQ for this ESP */
126 int scsi_id; /* Who am I as initiator? */
127 int scsi_id_mask; /* Bitmask of 'me'. */
128 int diff; /* Differential SCSI? */
129 int bursts; /* Burst sizes our DVMA supports */
130
131 /* Our command queues, only one cmd lives in the current_SC queue. */
132 Scsi_Cmnd *issue_SC; /* Commands to be issued */
133 Scsi_Cmnd *current_SC; /* Who is currently working the bus */
134 Scsi_Cmnd *disconnected_SC; /* Commands disconnected from the bus */
135
136 #ifdef THREADED_ESP_DRIVER
137 Scsi_Cmnd *eatme_SC; /* Cmds waiting for esp thread to process. */
138 #endif
139
140 /* Abortion status */
141 int aborting, abortion_complete, abort_result;
142 };
143
144 /* Bitfield meanings for the above registers. */
145
146 /* ESP config reg 1, read-write, found on all ESP chips */
147 #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
148 #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
149 #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
150 #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
151 #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
152 #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
153
154 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
155 #define ESP_CONFIG2_DMAPARITY 0x01 /* Parity DMA err (200,236) */
156 #define ESP_CONFIG2_REGPARITY 0x02 /* Parity reg err (200,236) */
157 #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
158 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features */
159 #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
160 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
161 #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,esp216) */
162 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (esp236) */
163 #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
164
165 /* ESP config register 3 read-write, found only esp236+fas236+fas100a chips */
166 #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a) */
167 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
168 #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a) */
169 #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
170 #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a) */
171 #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
172 #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a) */
173 #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
174 #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a) */
175 #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
176 #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
177 #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
178 #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
179
180 /* ESP command register read-write */
181 /* Group 1 commands: These may be sent at any point in time to the ESP
182 * chip. None of them can generate interrupts 'cept
183 * the "SCSI bus reset" command if you have not disabled
184 * SCSI reset interrupts in the config1 ESP register.
185 */
186 #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
187 #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
188 #define ESP_CMD_RC 0x02 /* Chip reset */
189 #define ESP_CMD_RS 0x03 /* SCSI bus reset */
190
191 /* Group 2 commands: ESP must be an initiator and connected to a target
192 * for these commands to work.
193 */
194 #define ESP_CMD_TI 0x10 /* Transfer Information */
195 #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
196 #define ESP_CMD_MOK 0x12 /* Message okie-dokie */
197 #define ESP_CMD_TPAD 0x18 /* Transfer Pad */
198 #define ESP_CMD_SATN 0x1a /* Set ATN */
199 #define ESP_CMD_RATN 0x1b /* De-assert ATN */
200
201 /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
202 * to a target as the initiator for these commands to work.
203 */
204 #define ESP_CMD_SMSG 0x20 /* Send message */
205 #define ESP_CMD_SSTAT 0x21 /* Send status */
206 #define ESP_CMD_SDATA 0x22 /* Send data */
207 #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
208 #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
209 #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
210 #define ESP_CMD_DCNCT 0x27 /* Disconnect */
211 #define ESP_CMD_RMSG 0x28 /* Receive Message */
212 #define ESP_CMD_RCMD 0x29 /* Receive Command */
213 #define ESP_CMD_RDATA 0x2a /* Receive Data */
214 #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
215
216 /* Group 4 commands: The ESP must be in the disconnected state and must
217 * not be connected to any targets as initiator for
218 * these commands to work.
219 */
220 #define ESP_CMD_RSEL 0x40 /* Reselect */
221 #define ESP_CMD_SEL 0x41 /* Select w/o ATN */
222 #define ESP_CMD_SELA 0x42 /* Select w/ATN */
223 #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
224 #define ESP_CMD_ESEL 0x44 /* Enable selection */
225 #define ESP_CMD_DSEL 0x45 /* Disable selections */
226 #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
227 #define ESP_CMD_RSEL3 0x47 /* Reselect3 */
228
229 /* This bit enables the ESP's DMA on the SBus */
230 #define ESP_CMD_DMA 0x80 /* Do DMA? */
231
232
233 /* ESP status register read-only */
234 #define ESP_STAT_PIO 0x01 /* IO phase bit */
235 #define ESP_STAT_PCD 0x02 /* CD phase bit */
236 #define ESP_STAT_PMSG 0x04 /* MSG phase bit */
237 #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
238 #define ESP_STAT_TDONE 0x08 /* Transfer Completed */
239 #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
240 #define ESP_STAT_PERR 0x20 /* Parity error */
241 #define ESP_STAT_SPAM 0x40 /* Real bad error */
242 /* This indicates the 'interrupt pending' condition on esp236, it is a reserved
243 * bit on other revs of the ESP.
244 */
245 #define ESP_STAT_INTR 0x80 /* Interrupt */
246
247 /* The status register can be masked with ESP_STAT_PMASK and compared
248 * with the following values to determine the current phase the ESP
249 * (at least thinks it) is in. For our purposes we also add our own
250 * software 'done' bit for our phase management engine.
251 */
252 #define ESP_DOP (0) /* Data Out */
253 #define ESP_DIP (ESP_STAT_PIO) /* Data In */
254 #define ESP_CMDP (ESP_STAT_PCD) /* Command */
255 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
256 #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
257 #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
258
259 /* ESP interrupt register read-only */
260 #define ESP_INTR_S 0x01 /* Select w/o ATN */
261 #define ESP_INTR_SATN 0x02 /* Select w/ATN */
262 #define ESP_INTR_RSEL 0x04 /* Reselected */
263 #define ESP_INTR_FDONE 0x08 /* Function done */
264 #define ESP_INTR_BSERV 0x10 /* Bus service */
265 #define ESP_INTR_DC 0x20 /* Disconnect */
266 #define ESP_INTR_IC 0x40 /* Illegal command given */
267 #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
268
269 /* Interrupt status macros */
270 #define ESP_SRESET_IRQ(esp) ((esp)->intreg & (ESP_INTR_SR))
271 #define ESP_ILLCMD_IRQ(esp) ((esp)->intreg & (ESP_INTR_IC))
272 #define ESP_SELECT_WITH_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_SATN))
273 #define ESP_SELECT_WITHOUT_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_S))
274 #define ESP_SELECTION_IRQ(esp) ((ESP_SELECT_WITH_ATN_IRQ(esp)) || \
275 (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
276 #define ESP_RESELECTION_IRQ(esp) ((esp)->intreg & (ESP_INTR_RSEL))
277
278 /* ESP sequence step register read-only */
279 #define ESP_STEP_VBITS 0x07 /* Valid bits */
280 #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
281 #define ESP_STEP_SID 0x01 /* One msg byte sent */
282 #define ESP_STEP_NCMD 0x02 /* Was not in command phase */
283 #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
284 * bytes to be lost
285 */
286 #define ESP_STEP_FINI 0x04 /* Command was sent ok */
287
288 /* ESP chip-test register read-write */
289 #define ESP_TEST_TARG 0x01 /* Target test mode */
290 #define ESP_TEST_INI 0x02 /* Initiator test mode */
291 #define ESP_TEST_TS 0x04 /* Tristate test mode */
292
293 /* ESP unique ID register read-only, found on fas236+fas100a only */
294 #define ESP_UID_F100A 0x00 /* ESP FAS100A */
295 #define ESP_UID_F236 0x02 /* ESP FAS236 */
296 #define ESP_UID_REV 0x07 /* ESP revision */
297 #define ESP_UID_FAM 0xf8 /* ESP family */
298
299 /* ESP fifo flags register read-only */
300 /* Note that the following implies a 16 byte FIFO on the ESP. */
301 #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
302 #define ESP_FF_SSTEP 0xe0 /* Sequence step */
303
304 /* ESP clock conversion factor register write-only */
305 #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
306 #define ESP_CCF_NEVER 0x01 /* Set it to this and die */
307 #define ESP_CCF_F2 0x02 /* 10MHz */
308 #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
309 #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
310 #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
311 #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
312 #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
313
314 extern int esp_detect(struct SHT *);
315 extern const char *esp_info(struct Scsi_Host *);
316 extern int esp_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
317 extern int esp_command(Scsi_Cmnd *);
318 extern int esp_abort(Scsi_Cmnd *);
319 extern int esp_reset(Scsi_Cmnd *, unsigned int);
320
321 extern struct proc_dir_entry proc_scsi_esp;
322
323 #define SCSI_SPARC_ESP { \
324 /* struct SHT *next */ NULL, \
325 /* long *usage_count */ NULL, \
326 /* struct proc_dir_entry *proc_dir */ &proc_scsi_esp, \
327 /* int (*proc_info)(char *, char **, off_t, int, int, int) */ NULL, \
328 /* const char *name */ "Sun ESP 100/100a/200", \
329 /* int detect(struct SHT *) */ esp_detect, \
330 /* int release(struct Scsi_Host *) */ NULL, \
331 /* const char *info(struct Scsi_Host *) */ esp_info, \
332 /* int command(Scsi_Cmnd *) */ esp_command, \
333 /* int queuecommand(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *)) */ esp_queue, \
334 /* int abort(Scsi_Cmnd *) */ esp_abort, \
335 /* int reset(Scsi_Cmnd *, int) */ esp_reset, \
336 /* int slave_attach(int, int) */ NULL, \
337 /* int bios_param(Disk *, kdev_t, int[]) */ NULL, \
338 /* int can_queue */ 10, \
339 /* int this_id */ 7, \
340 /* short unsigned int sg_tablesize */ SG_ALL, \
341 /* short cmd_per_lun */ 1, \
342 /* unsigned char present */ 0, \
343 /* unsigned unchecked_isa_dma:1 */ 0, \
344 /* unsigned use_clustering:1 */ DISABLE_CLUSTERING, }
345
346 /* For our interrupt engine. */
347 #define for_each_esp(esp) \
348 for((esp) = espchain; (esp); (esp) = (esp)->next)
349
350 #endif /* !(_SPARC_ESP_H) */
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