include/asm-m68k/atarihw.h

/* */
This source file includes following definitions.
dma_cache_maintenance
   1 /*
   2 ** linux/atarihw.h -- This header defines some macros and pointers for
   3 **                    the various Atari custom hardware registers.
   4 **
   5 ** Copyright 1994 by Bj”rn Brauel
   6 **
   7 ** 5/1/94 Roman Hodek:
   8 **   Added definitions for TT specific chips.
   9 **
  10 ** This file is subject to the terms and conditions of the GNU General Public
  11 ** License.  See the file README.legal in the main directory of this archive
  12 ** for more details.
  13 **
  14 */
  15 
  16 #ifndef _LINUX_ATARIHW_H_
  17 #define _LINUX_ATARIHW_H_
  18 
  19 #include <linux/types.h>
  20 
  21 /* Reading the MFP port register gives a machine independent delay, since the
  22  * MFP always has a 8 MHz clock. This avoids problems with the varying length
  23  * of nops on various machines. Somebody claimed that the tstb takes 600 ns.
  24  */
  25 #define MFPDELAY() \
  26         __asm__ __volatile__ ( "tstb %0" : : "m" (mfp.par_dt_reg) : "cc" );
  27 
  28 /* Memory used for screen ram and stdma buffers */
  29 void atari_stram_init (void);
  30 void *atari_stram_alloc (long size, unsigned long *start_mem );
  31 void atari_stram_free (void *);
  32 
  33 extern int is_medusa;
  34 
  35 /* Do cache push/invalidate for DMA read/write. This function obeys the
  36  * snooping on some machines (Medusa) and processors: The Medusa itself can
  37  * snoop, but only the '040 can source data from its cache to DMA writes i.e.,
  38  * reads from memory). Both '040 and '060 invalidate cache entries on snooped
  39  * DMA reads (i.e., writes to memory).
  40  */
  41 
  42 #include <linux/mm.h>
  43 #include <asm/pgtable.h>
  44 
  45 static inline void dma_cache_maintenance( unsigned long paddr,
     /*  */
  46                                           unsigned long len,
  47                                           int writeflag )
  48 
  49 {
  50         if (writeflag) {
  51                 if (!is_medusa || m68k_is040or060 == 6)
  52                         cache_push( paddr, len );
  53         }
  54         else {
  55                 if (!is_medusa)
  56                         cache_clear( paddr, len );
  57         }
  58 }
  59 
  60 
  61 /* 
  62 ** Shifter  
  63  */
  64 #define ST_LOW  0
  65 #define ST_MID  1
  66 #define ST_HIGH 2
  67 #define TT_LOW  7
  68 #define TT_MID  4
  69 #define TT_HIGH 6
  70 
  71 #define SHF_BAS (0xffff8200)    
  72 struct SHIFTER 
  73  {
  74         u_char pad1;
  75         u_char bas_hi;
  76         u_char pad2;
  77         u_char bas_md;
  78         u_char pad3;
  79         u_char volatile vcounthi;
  80         u_char pad4;
  81         u_char volatile vcountmid;
  82         u_char pad5;
  83         u_char volatile vcountlow;
  84         u_char volatile syncmode;
  85         u_char pad6;
  86         u_char pad7; 
  87         u_char bas_lo;
  88  };
  89 # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
  90 
  91 #define SHF_FBAS (0xffff820e)
  92 struct SHIFTER_F030
  93  {
  94   u_short off_next;
  95   u_short scn_width;
  96  };                             
  97 # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
  98 
  99 
 100 #define SHF_TBAS (0xffff8200)
 101 struct SHIFTER_TT {
 102         u_char  char_dummy0;
 103         u_char  bas_hi;                 /* video mem base addr, high and mid byte */
 104         u_char  char_dummy1;
 105         u_char  bas_md;
 106         u_char  char_dummy2;
 107         u_char  vcount_hi;              /* pointer to currently displayed byte */
 108         u_char  char_dummy3;
 109         u_char  vcount_md;
 110         u_char  char_dummy4;
 111         u_char  vcount_lo;
 112         u_short st_sync;                /* ST compatible sync mode register, unused */
 113         u_char  char_dummy5;
 114         u_char  bas_lo;                 /* video mem addr, low byte */
 115         u_char  char_dummy6[2+3*16];
 116         /* $ffff8240: */
 117         u_short color_reg[16];  /* 16 color registers */
 118         u_char  st_shiftmode;   /* ST compatible shift mode register, unused */
 119         u_char  char_dummy7;
 120         u_short tt_shiftmode;   /* TT shift mode register */
 121 
 122 
 123 };
 124 #define shifter_tt      ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
 125 
 126 /* values for shifter_tt->tt_shiftmode */
 127 #define TT_SHIFTER_STLOW                0x0000
 128 #define TT_SHIFTER_STMID                0x0100
 129 #define TT_SHIFTER_STHIGH               0x0200
 130 #define TT_SHIFTER_TTLOW                0x0700
 131 #define TT_SHIFTER_TTMID                0x0400
 132 #define TT_SHIFTER_TTHIGH               0x0600
 133 #define TT_SHIFTER_MODEMASK     0x0700
 134 #define TT_SHIFTER_NUMMODE      0x0008
 135 #define TT_SHIFTER_PALETTE_MASK 0x000f
 136 #define TT_SHIFTER_GRAYMODE             0x1000
 137 
 138 /* 256 TT palette registers */
 139 #define TT_PALETTE_BASE (0xffff8400)
 140 #define tt_palette      ((volatile u_short *)TT_PALETTE_BASE)
 141 
 142 #define TT_PALETTE_RED_MASK             0x0f00
 143 #define TT_PALETTE_GREEN_MASK   0x00f0
 144 #define TT_PALETTE_BLUE_MASK    0x000f
 145 
 146 /*
 147 ** Falcon030 VIDEL Video Controller
 148 ** for description see File 'linux\tools\atari\hardware.txt
 149  */
 150 #define f030_col ((u_long *)            0xffff9800)
 151 #define f030_xreg ((u_short*)           0xffff8282)
 152 #define f030_yreg ((u_short*)           0xffff82a2)
 153 #define f030_creg ((u_short*)           0xffff82c0)
 154 #define f030_sreg ((u_short*)           0xffff8260)
 155 #define f030_mreg ((u_short*)           0xffff820a)
 156 #define f030_linewidth ((u_short*)      0xffff820e)
 157 #define f030_hscroll ((u_char*)         0xffff8265)
 158 
 159 #define VIDEL_BAS (0xffff8260)
 160 struct VIDEL {
 161         u_short st_shift;
 162         u_short pad1;
 163         u_char  xoffset_s;
 164         u_char  xoffset;
 165         u_short f_shift;
 166         u_char  pad2[0x1a];
 167         u_short hht;
 168         u_short hbb;
 169         u_short hbe;
 170         u_short hdb;
 171         u_short hde;
 172         u_short hss;
 173         u_char  pad3[0x14];
 174         u_short vft;
 175         u_short vbb;
 176         u_short vbe;
 177         u_short vdb;
 178         u_short vde;
 179         u_short vss;
 180         u_char  pad4[0x12];
 181         u_short control;
 182         u_short mode;
 183 };
 184 #define videl   ((*(volatile struct VIDEL *)VIDEL_BAS))
 185 
 186 /*
 187 ** DMA/WD1772 Disk Controller
 188  */                          
 189  
 190 #define FWD_BAS (0xffff8604)  
 191 struct DMA_WD
 192  {
 193   u_short fdc_acces_seccount;
 194   u_short dma_mode_status;
 195   u_char dma_vhi;       /* Some extended ST-DMAs can handle 32 bit addresses */
 196   u_char dma_hi;
 197   u_char char_dummy2;
 198   u_char dma_md;
 199   u_char char_dummy3;
 200   u_char dma_lo;
 201   u_short fdc_speed;
 202  };
 203 # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
 204 /* alias */
 205 #define st_dma dma_wd
 206 /* The two highest bytes of an extended DMA as a short; this is a must
 207  * for the Medusa.
 208  */
 209 #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
 210 
 211 /*
 212 ** YM2149 Sound Chip
 213 ** access in bytes
 214  */
 215 
 216 #define YM_BAS (0xffff8800)
 217 struct SOUND_YM
 218  {
 219   u_char rd_data_reg_sel;
 220   u_char char_dummy1;
 221   u_char wd_data;
 222  };
 223 #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
 224 
 225 /* TT SCSI DMA */
 226 
 227 #define TT_SCSI_DMA_BAS (0xffff8700)
 228 struct TT_DMA {
 229         u_char  char_dummy0;
 230         u_char  dma_addr_hi;
 231         u_char  char_dummy1;
 232         u_char  dma_addr_hmd;
 233         u_char  char_dummy2;
 234         u_char  dma_addr_lmd;
 235         u_char  char_dummy3;
 236         u_char  dma_addr_lo;
 237         u_char  char_dummy4;
 238         u_char  dma_cnt_hi;
 239         u_char  char_dummy5;
 240         u_char  dma_cnt_hmd;
 241         u_char  char_dummy6;
 242         u_char  dma_cnt_lmd;
 243         u_char  char_dummy7;
 244         u_char  dma_cnt_lo;
 245         u_long  dma_restdata;
 246         u_short dma_ctrl;
 247 };
 248 #define tt_scsi_dma     ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
 249 
 250 /* TT SCSI Controller 5380 */
 251 
 252 #define TT_5380_BAS     (0xffff8781)
 253 struct TT_5380 {
 254         u_char  scsi_data;
 255         u_char  char_dummy1;
 256         u_char  scsi_icr;
 257         u_char  char_dummy2;
 258         u_char  scsi_mode;
 259         u_char  char_dummy3;
 260         u_char  scsi_tcr;
 261         u_char  char_dummy4;
 262         u_char  scsi_idstat;
 263         u_char  char_dummy5;
 264         u_char  scsi_dmastat;
 265         u_char  char_dummy6;
 266         u_char  scsi_targrcv;
 267         u_char  char_dummy7;
 268         u_char  scsi_inircv;
 269 };
 270 #define tt_scsi                 ((*(volatile struct TT_5380 *)TT_5380_BAS))
 271 #define tt_scsi_regp    ((volatile char *)TT_5380_BAS)
 272 
 273 
 274 /* 
 275 ** Falcon DMA Sound Subsystem
 276 ** not implemented yet
 277  */     
 278 
 279 /*
 280 ** Falcon Blitter
 281 */
 282 
 283 #define BLT_BAS (0xffff8a00)
 284 
 285 struct BLITTER
 286  {
 287   u_short halftone[16];
 288   u_short src_x_inc;
 289   u_short src_y_inc;
 290   u_long src_address;
 291   u_short endmask1;  
 292   u_short endmask2;  
 293   u_short endmask3;
 294   u_short dst_x_inc;
 295   u_short dst_y_inc;
 296   u_long dst_address;
 297   u_short wd_per_line;
 298   u_short ln_per_bb;
 299   u_short hlf_op_reg;
 300   u_short log_op_reg;
 301   u_short lin_nm_reg;
 302   u_short skew_reg;  
 303  };
 304 # define blitter ((*(volatile struct BLITTER *)BLT_BAS))
 305 
 306 
 307 /*
 308 ** SCC Z8530
 309  */
 310  
 311 #define SCC_BAS (0xffff8c81)
 312 struct SCC
 313  {
 314   u_char cha_a_ctrl;
 315   u_char char_dummy1;
 316   u_char cha_a_data;
 317   u_char char_dummy2;
 318   u_char cha_b_ctrl;
 319   u_char char_dummy3;
 320   u_char cha_b_data;
 321  };
 322 # define scc ((*(volatile struct SCC*)SCC_BAS))
 323 
 324 /* The ESCC (Z85230) in an Atari ST. The channels are revered! */
 325 # define st_escc ((*(volatile struct SCC*)0xfffffa31))
 326 # define st_escc_dsr ((*(volatile char *)0xfffffa39))
 327 
 328 /* TT SCC DMA Controller (same chip as SCSI DMA) */
 329 
 330 #define TT_SCC_DMA_BAS  (0xffff8c01)
 331 #define tt_scc_dma      ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
 332 
 333 /*
 334 ** VIDEL Palette Register 
 335  */
 336 
 337 #define FPL_BAS (0xffff9800)
 338 struct VIDEL_PALETTE
 339  {
 340   u_long reg[256];
 341  };
 342 # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
 343 
 344 
 345 /*
 346 ** Falcon DSP Host Interface
 347 ** not implemented yet
 348  */
 349  
 350 /*
 351 ** MFP 68901
 352  */
 353  
 354 #define MFP_BAS (0xfffffa01)
 355 struct MFP
 356  {
 357   u_char par_dt_reg;
 358   u_char char_dummy1;
 359   u_char active_edge;
 360   u_char char_dummy2;
 361   u_char data_dir;
 362   u_char char_dummy3;
 363   u_char int_en_a;
 364   u_char char_dummy4;
 365   u_char int_en_b;
 366   u_char char_dummy5;
 367   u_char int_pn_a;
 368   u_char char_dummy6;
 369   u_char int_pn_b;
 370   u_char char_dummy7;
 371   u_char int_sv_a;
 372   u_char char_dummy8;
 373   u_char int_sv_b;
 374   u_char char_dummy9;
 375   u_char int_mk_a;
 376   u_char char_dummy10;
 377   u_char int_mk_b;
 378   u_char char_dummy11;
 379   u_char vec_adr;
 380   u_char char_dummy12;
 381   u_char tim_ct_a;
 382   u_char char_dummy13;
 383   u_char tim_ct_b;
 384   u_char char_dummy14;
 385   u_char tim_ct_cd;
 386   u_char char_dummy15;
 387   u_char tim_dt_a;
 388   u_char char_dummy16;
 389   u_char tim_dt_b;
 390   u_char char_dummy17;
 391   u_char tim_dt_c;
 392   u_char char_dummy18;
 393   u_char tim_dt_d;
 394   u_char char_dummy19;
 395   u_char sync_char;
 396   u_char char_dummy20;
 397   u_char usart_ctr;
 398   u_char char_dummy21;
 399   u_char rcv_stat;
 400   u_char char_dummy22;
 401   u_char trn_stat;
 402   u_char char_dummy23;
 403   u_char usart_dta;
 404  };
 405 # define mfp ((*(volatile struct MFP*)MFP_BAS))
 406 
 407 /* TT's second MFP */
 408 
 409 #define TT_MFP_BAS      (0xfffffa81)
 410 # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
 411 
 412 
 413 /* TT System Control Unit */
 414 
 415 #define TT_SCU_BAS      (0xffff8e01)
 416 struct TT_SCU {
 417         u_char  sys_mask;
 418         u_char  char_dummy1;
 419         u_char  sys_stat;
 420         u_char  char_dummy2;
 421         u_char  softint;
 422         u_char  char_dummy3;
 423         u_char  vmeint;
 424         u_char  char_dummy4;
 425         u_char  gp_reg1;
 426         u_char  char_dummy5;
 427         u_char  gp_reg2;
 428         u_char  char_dummy6;
 429         u_char  vme_mask;
 430         u_char  char_dummy7;
 431         u_char  vme_stat;
 432 };
 433 #define tt_scu  ((*(volatile struct TT_SCU *)TT_SCU_BAS))
 434 
 435 /* TT real time clock */
 436 
 437 #define TT_RTC_BAS      (0xffff8961)
 438 struct TT_RTC {
 439         u_char  regsel;
 440         u_char  dummy;
 441         u_char  data;
 442 };
 443 #define tt_rtc  ((*(volatile struct TT_RTC *)TT_RTC_BAS))
 444 
 445 
 446 /*
 447 ** ACIA 6850
 448  */
 449 /* constants for the ACIA registers */
 450 
 451 /* baudrate selection and reset (Baudrate = clock/factor) */
 452 #define ACIA_DIV1  0
 453 #define ACIA_DIV16 1
 454 #define ACIA_DIV64 2
 455 #define ACIA_RESET 3
 456 
 457 /* character format */
 458 #define ACIA_D7E2S (0<<2)       /* 7 data, even parity, 2 stop */
 459 #define ACIA_D7O2S (1<<2)       /* 7 data, odd parity, 2 stop */
 460 #define ACIA_D7E1S (2<<2)       /* 7 data, even parity, 1 stop */
 461 #define ACIA_D7O1S (3<<2)       /* 7 data, odd parity, 1 stop */
 462 #define ACIA_D8N2S (4<<2)       /* 8 data, no parity, 2 stop */
 463 #define ACIA_D8N1S (5<<2)       /* 8 data, no parity, 1 stop */
 464 #define ACIA_D8E1S (6<<2)       /* 8 data, even parity, 1 stop */
 465 #define ACIA_D8O1S (7<<2)       /* 8 data, odd parity, 1 stop */
 466 
 467 /* transmit control */
 468 #define ACIA_RLTID (0<<5)       /* RTS low, TxINT disabled */
 469 #define ACIA_RLTIE (1<<5)       /* RTS low, TxINT enabled */
 470 #define ACIA_RHTID (2<<5)       /* RTS high, TxINT disabled */
 471 #define ACIA_RLTIDSB (3<<5)     /* RTS low, TxINT disabled, send break */
 472 
 473 /* receive control */
 474 #define ACIA_RID (0<<7)         /* RxINT disabled */
 475 #define ACIA_RIE (1<<7)         /* RxINT enabled */
 476 
 477 /* status fields of the ACIA */
 478 #define ACIA_RDRF 1             /* Receive Data Register Full */
 479 #define ACIA_TDRE (1<<1)        /* Transmit Data Register Empty */
 480 #define ACIA_DCD  (1<<2)        /* Data Carrier Detect */
 481 #define ACIA_CTS  (1<<3)        /* Clear To Send */
 482 #define ACIA_FE   (1<<4)        /* Framing Error */
 483 #define ACIA_OVRN (1<<5)        /* Receiver Overrun */
 484 #define ACIA_PE   (1<<6)        /* Parity Error */
 485 #define ACIA_IRQ  (1<<7)        /* Interrupt Request */
 486 
 487 #define ACIA_BAS (0xfffffc00)
 488 struct ACIA 
 489  {
 490   u_char key_ctrl;
 491   u_char char_dummy1;
 492   u_char key_data;
 493   u_char char_dummy2;
 494   u_char mid_ctrl;
 495   u_char char_dummy3;
 496   u_char mid_data;
 497  };
 498 # define acia ((*(volatile struct ACIA*)ACIA_BAS))
 499 
 500 #define TT_DMASND_BAS (0xffff8900)
 501 struct TT_DMASND {
 502         u_char  int_ctrl;       /* Falcon: Interrupt control */
 503         u_char  ctrl;
 504         u_char  pad2;
 505         u_char  bas_hi;
 506         u_char  pad3;
 507         u_char  bas_mid;
 508         u_char  pad4;
 509         u_char  bas_low;
 510         u_char  pad5;
 511         u_char  addr_hi;
 512         u_char  pad6;
 513         u_char  addr_mid;
 514         u_char  pad7;
 515         u_char  addr_low;
 516         u_char  pad8;
 517         u_char  end_hi;
 518         u_char  pad9;
 519         u_char  end_mid;
 520         u_char  pad10;
 521         u_char  end_low;
 522         u_char  pad11[12];
 523         u_char  track_select;   /* Falcon */
 524         u_char  mode;
 525         u_char  pad12[14];
 526         /* Falcon only: */
 527         u_short cbar_src;
 528         u_short cbar_dst;
 529         u_char  ext_div;
 530         u_char  int_div;
 531         u_char  rec_track_select;
 532         u_char  dac_src;
 533         u_char  adc_src;
 534         u_char  input_gain;
 535         u_short output_atten;
 536 };
 537 # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
 538 
 539 #define DMASND_CTRL_OFF         0x00
 540 #define DMASND_CTRL_ON          0x01
 541 #define DMASND_CTRL_REPEAT      0x02
 542 #define DMASND_MODE_MONO        0x80
 543 #define DMASND_MODE_STEREO      0x00
 544 #define DMASND_MODE_8BIT        0x00
 545 #define DMASND_MODE_16BIT       0x40    /* Falcon only */
 546 #define DMASND_MODE_6KHZ        0x00    /* Falcon: mute */
 547 #define DMASND_MODE_12KHZ       0x01
 548 #define DMASND_MODE_25KHZ       0x02
 549 #define DMASND_MODE_50KHZ       0x03
 550 
 551 #define DMASNDSetBase(bufstart)                                         \
 552     do {                                                                \
 553         tt_dmasnd.bas_hi  = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
 554         tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
 555         tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
 556     } while( 0 )
 557 
 558 #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) +     \
 559                         (tt_dmasnd.addr_mid << 8) +     \
 560                         (tt_dmasnd.addr_low))
 561 
 562 #define DMASNDSetEnd(bufend)                            \
 563     do {                                                \
 564         tt_dmasnd.end_hi  = (unsigned char)(((bufend) & 0xff0000) >> 16); \
 565         tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
 566         tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
 567     } while( 0 )
 568 
 569 
 570 #define TT_MICROWIRE_BAS        (0xffff8922)
 571 struct TT_MICROWIRE {
 572         u_short data;
 573         u_short mask;
 574 };
 575 # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
 576 
 577 #define MW_LM1992_ADDR          0x0400
 578 
 579 #define MW_LM1992_VOLUME(dB)    \
 580     (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
 581 #define MW_LM1992_BALLEFT(dB)   \
 582     (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
 583 #define MW_LM1992_BALRIGHT(dB)  \
 584     (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
 585 #define MW_LM1992_TREBLE(dB)    \
 586     (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
 587 #define MW_LM1992_BASS(dB)      \
 588     (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
 589 
 590 #define MW_LM1992_PSG_LOW       0x000
 591 #define MW_LM1992_PSG_HIGH      0x001
 592 #define MW_LM1992_PSG_OFF       0x002
 593 
 594 #define MSTE_RTC_BAS    (0xfffffc21)
 595 
 596 struct MSTE_RTC {
 597         u_char sec_ones;
 598         u_char dummy1;
 599         u_char sec_tens;
 600         u_char dummy2;
 601         u_char min_ones;
 602         u_char dummy3;
 603         u_char min_tens;
 604         u_char dummy4;
 605         u_char hr_ones;
 606         u_char dummy5;
 607         u_char hr_tens;
 608         u_char dummy6;
 609         u_char weekday;
 610         u_char dummy7;
 611         u_char day_ones;
 612         u_char dummy8;
 613         u_char day_tens;
 614         u_char dummy9;
 615         u_char mon_ones;
 616         u_char dummy10;
 617         u_char mon_tens;
 618         u_char dummy11;
 619         u_char year_ones;
 620         u_char dummy12;
 621         u_char year_tens;
 622         u_char dummy13;
 623         u_char mode;
 624         u_char dummy14;
 625         u_char test;
 626         u_char dummy15;
 627         u_char reset;
 628 };
 629 
 630 #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
 631 
 632 #endif /* linux/atarihw.h */
 633
/* */
root/include/asm-m68k/atarihw.h

INCLUDED FROM

DEFINITIONS
