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15
16 #define DE4X5_BMR iobase+(0x000 << lp->bus)
17 #define DE4X5_TPD iobase+(0x008 << lp->bus)
18 #define DE4X5_RPD iobase+(0x010 << lp->bus)
19 #define DE4X5_RRBA iobase+(0x018 << lp->bus)
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus)
21 #define DE4X5_STS iobase+(0x028 << lp->bus)
22 #define DE4X5_OMR iobase+(0x030 << lp->bus)
23 #define DE4X5_IMR iobase+(0x038 << lp->bus)
24 #define DE4X5_MFC iobase+(0x040 << lp->bus)
25 #define DE4X5_APROM iobase+(0x048 << lp->bus)
26 #define DE4X5_BROM iobase+(0x048 << lp->bus)
27 #define DE4X5_SROM iobase+(0x048 << lp->bus)
28 #define DE4X5_MII iobase+(0x048 << lp->bus)
29 #define DE4X5_DDR iobase+(0x050 << lp->bus)
30 #define DE4X5_FDR iobase+(0x058 << lp->bus)
31 #define DE4X5_GPT iobase+(0x058 << lp->bus)
32 #define DE4X5_GEP iobase+(0x060 << lp->bus)
33 #define DE4X5_SISR iobase+(0x060 << lp->bus)
34 #define DE4X5_SICR iobase+(0x068 << lp->bus)
35 #define DE4X5_STRR iobase+(0x070 << lp->bus)
36 #define DE4X5_SIGR iobase+(0x078 << lp->bus)
37
38
39
40
41 #define EISA_ID iobase+0x0c80
42 #define EISA_ID0 iobase+0x0c80
43 #define EISA_ID1 iobase+0x0c81
44 #define EISA_ID2 iobase+0x0c82
45 #define EISA_ID3 iobase+0x0c83
46 #define EISA_CR iobase+0x0c84
47 #define EISA_REG0 iobase+0x0c88
48 #define EISA_REG1 iobase+0x0c89
49 #define EISA_REG2 iobase+0x0c8a
50 #define EISA_REG3 iobase+0x0c8f
51 #define EISA_APROM iobase+0x0c90
52
53
54
55
56 #define PCI_CFID iobase+0x0008
57 #define PCI_CFCS iobase+0x000c
58 #define PCI_CFRV iobase+0x0018
59 #define PCI_CFLT iobase+0x001c
60 #define PCI_CBIO iobase+0x0028
61 #define PCI_CBMA iobase+0x002c
62 #define PCI_CBER iobase+0x0030
63 #define PCI_CFIT iobase+0x003c
64 #define PCI_CFDA iobase+0x0040
65
66
67
68
69 #define ER0_BSW 0x80
70 #define ER0_BMW 0x40
71 #define ER0_EPT 0x20
72 #define ER0_ISTS 0x10
73 #define ER0_LI 0x08
74 #define ER0_INTL 0x06
75 #define ER0_INTT 0x01
76
77
78
79
80 #define ER1_IAM 0xe0
81 #define ER1_IAE 0x10
82 #define ER1_UPIN 0x0f
83
84
85
86
87 #define ER2_BRS 0xc0
88 #define ER2_BRA 0x3c
89
90
91
92
93 #define ER3_BWE 0x40
94 #define ER3_BRE 0x04
95 #define ER3_LSR 0x02
96
97
98
99
100 #define CFID_DID 0xff00
101 #define CFID_VID 0x00ff
102 #define DC21040_DID 0x0002
103 #define DC21040_VID 0x1011
104 #define DC21041_DID 0x0014
105 #define DC21041_VID 0x1011
106 #define DC21140_DID 0x0009
107 #define DC21140_VID 0x1011
108
109
110
111
112 #define DC21040 DC21040_DID
113 #define DC21041 DC21041_DID
114 #define DC21140 DC21140_DID
115
116 #define is_DC21040 ((vendor == DC21040_VID) && (device == DC21040_DID))
117 #define is_DC21041 ((vendor == DC21041_VID) && (device == DC21041_DID))
118 #define is_DC21140 ((vendor == DC21140_VID) && (device == DC21140_DID))
119
120
121
122
123 #define CFCS_DPE 0x80000000
124 #define CFCS_SSE 0x40000000
125 #define CFCS_RMA 0x20000000
126 #define CFCS_RTA 0x10000000
127 #define CFCS_DST 0x06000000
128 #define CFCS_DPR 0x01000000
129 #define CFCS_FBB 0x00800000
130 #define CFCS_SLE 0x00000100
131 #define CFCS_PER 0x00000040
132 #define CFCS_MO 0x00000004
133 #define CFCS_MSA 0x00000002
134 #define CFCS_IOSA 0x00000001
135
136
137
138
139 #define CFRV_BC 0xff000000
140 #define CFRV_SC 0x00ff0000
141 #define CFRV_SN 0x000000f0
142 #define CFRV_RN 0x0000000f
143 #define BASE_CLASS 0x02000000
144 #define SUB_CLASS 0x00000000
145 #define STEP_NUMBER 0x00000020
146 #define REV_NUMBER 0x00000003
147 #define CFRV_MASK 0xffff0000
148
149
150
151
152 #define CFLT_BC 0x0000ff00
153
154
155
156
157 #define CBIO_MASK 0xffffff80
158 #define CBIO_IOSI 0x00000001
159
160
161
162
163 #define CBER_MASK 0xfffffc00
164 #define CBER_ROME 0x00000001
165
166
167
168
169 #define CFDA_PSM 0x80000000
170
171
172
173
174 #define BMR_DBO 0x00100000
175 #define BMR_TAP 0x000e0000
176 #define BMR_DAS 0x00010000
177 #define BMR_CAL 0x0000c000
178 #define BMR_PBL 0x00003f00
179 #define BMR_BLE 0x00000080
180 #define BMR_DSL 0x0000007c
181 #define BMR_BAR 0x00000002
182 #define BMR_SWR 0x00000001
183
184 #define TAP_NOPOLL 0x00000000
185 #define TAP_200US 0x00020000
186 #define TAP_800US 0x00040000
187 #define TAP_1_6MS 0x00060000
188 #define TAP_12_8US 0x00080000
189 #define TAP_25_6US 0x000a0000
190 #define TAP_51_2US 0x000c0000
191 #define TAP_102_4US 0x000e0000
192
193 #define CAL_NOUSE 0x00000000
194 #define CAL_8LONG 0x00004000
195 #define CAL_16LONG 0x00008000
196 #define CAL_32LONG 0x0000c000
197
198 #define PBL_0 0x00000000
199 #define PBL_1 0x00000100
200 #define PBL_2 0x00000200
201 #define PBL_4 0x00000400
202 #define PBL_8 0x00000800
203 #define PBL_16 0x00001000
204 #define PBL_32 0x00002000
205
206 #define DSL_0 0x00000000
207 #define DSL_1 0x00000004
208 #define DSL_2 0x00000008
209 #define DSL_4 0x00000010
210 #define DSL_8 0x00000020
211 #define DSL_16 0x00000040
212 #define DSL_32 0x00000080
213
214
215
216
217 #define TPD 0x00000001
218
219
220
221
222 #define RPD 0x00000001
223
224
225
226
227 #define RRBA 0xfffffffc
228
229
230
231
232 #define TRBA 0xfffffffc
233
234
235
236
237 #define STS_BE 0x03800000
238 #define STS_TS 0x00700000
239 #define STS_RS 0x000e0000
240 #define STS_NIS 0x00010000
241 #define STS_AIS 0x00008000
242 #define STS_ER 0x00004000
243 #define STS_SE 0x00002000
244 #define STS_LNF 0x00001000
245 #define STS_FD 0x00000800
246 #define STS_TM 0x00000800
247 #define STS_AT 0x00000400
248 #define STS_RWT 0x00000200
249 #define STS_RPS 0x00000100
250 #define STS_RU 0x00000080
251 #define STS_RI 0x00000040
252 #define STS_UNF 0x00000020
253 #define STS_LNP 0x00000010
254 #define STS_TJT 0x00000008
255 #define STS_TU 0x00000004
256 #define STS_TPS 0x00000002
257 #define STS_TI 0x00000001
258
259 #define EB_PAR 0x00000000
260 #define EB_MA 0x00800000
261 #define EB_TA 0x01000000
262 #define EB_RES0 0x01800000
263 #define EB_RES1 0x02000000
264
265 #define TS_STOP 0x00000000
266 #define TS_FTD 0x00100000
267 #define TS_WEOT 0x00200000
268 #define TS_QDAT 0x00300000
269 #define TS_RES 0x00400000
270 #define TS_SPKT 0x00500000
271 #define TS_SUSP 0x00600000
272 #define TS_CLTD 0x00700000
273
274 #define RS_STOP 0x00000000
275 #define RS_FRD 0x00020000
276 #define RS_CEOR 0x00040000
277 #define RS_WFRP 0x00060000
278 #define RS_SUSP 0x00080000
279 #define RS_CLRD 0x000a0000
280 #define RS_FLUSH 0x000c0000
281 #define RS_QRFS 0x000e0000
282
283 #define INT_CANCEL 0x0001ffff
284
285
286
287
288 #define OMR_SDP 0x02000000
289 #define OMR_SCR 0x01000000
290 #define OMR_PCS 0x00800000
291 #define OMR_TTM 0x00400000
292 #define OMR_SF 0x00200000
293 #define OMR_HBD 0x00080000
294 #define OMR_PS 0x00040000
295 #define OMR_CA 0x00020000
296 #define OMR_BP 0x00010000
297 #define OMR_TR 0x0000c000
298 #define OMR_ST 0x00002000
299 #define OMR_FC 0x00001000
300 #define OMR_OM 0x00000c00
301 #define OMR_FD 0x00000200
302 #define OMR_FKD 0x00000100
303 #define OMR_PM 0x00000080
304 #define OMR_PR 0x00000040
305 #define OMR_SB 0x00000020
306 #define OMR_IF 0x00000010
307 #define OMR_PB 0x00000008
308 #define OMR_HO 0x00000004
309 #define OMR_SR 0x00000002
310 #define OMR_HP 0x00000001
311
312 #define TR_72 0x00000000
313 #define TR_96 0x00004000
314 #define TR_128 0x00008000
315 #define TR_160 0x0000c000
316
317
318
319
320 #define IMR_NIM 0x00010000
321 #define IMR_AIM 0x00008000
322 #define IMR_ERM 0x00004000
323 #define IMR_SEM 0x00002000
324 #define IMR_LFM 0x00001000
325 #define IMR_FDM 0x00000800
326 #define IMR_TMM 0x00000800
327 #define IMR_ATM 0x00000400
328 #define IMR_RWM 0x00000200
329 #define IMR_RSM 0x00000100
330 #define IMR_RUM 0x00000080
331 #define IMR_RIM 0x00000040
332 #define IMR_UNM 0x00000020
333 #define IMR_LPM 0x00000010
334 #define IMR_TJM 0x00000008
335 #define IMR_TUM 0x00000004
336 #define IMR_TSM 0x00000002
337 #define IMR_TIM 0x00000001
338
339
340
341
342 #define MFC_OVFL 0x00010000
343 #define MFC_CNTR 0x0000ffff
344
345
346
347
348 #define APROM_DN 0x80000000
349 #define APROM_DT 0x000000ff
350
351
352
353
354 #define BROM_MODE 0x00008000
355 #define BROM_RD 0x00004000
356 #define BROM_WR 0x00002000
357 #define BROM_BR 0x00001000
358 #define BROM_SR 0x00000800
359 #define BROM_REG 0x00000400
360 #define BROM_DT 0x000000ff
361
362
363
364
365 #define MII_MDI 0x00080000
366 #define MII_MDO 0x00060000
367 #define MII_MRD 0x00040000
368 #define MII_MWR 0x00000000
369 #define MII_MDT 0x00020000
370 #define MII_MDC 0x00010000
371 #define MII_RD 0x00004000
372 #define MII_WR 0x00002000
373 #define MII_SEL 0x00000800
374
375 #define SROM_MODE 0x00008000
376 #define SROM_RD 0x00004000
377 #define SROM_WR 0x00002000
378 #define SROM_BR 0x00001000
379 #define SROM_SR 0x00000800
380 #define SROM_REG 0x00000400
381 #define SROM_DT 0x000000ff
382
383 #define DT_OUT 0x00000008
384 #define DT_IN 0x00000004
385 #define DT_CLK 0x00000002
386 #define DT_CS 0x00000001
387
388 #define MII_PREAMBLE 0xffffffff
389 #define MII_TEST 0xaaaaaaaa
390 #define MII_STRD 0x06
391 #define MII_STWR 0x0a
392
393 #define MII_CR 0x00
394 #define MII_SR 0x01
395 #define MII_ID0 0x02
396 #define MII_ID1 0x03
397 #define MII_ANA 0x04
398 #define MII_ANLPA 0x05
399 #define MII_ANE 0x06
400 #define MII_ANP 0x07
401
402 #define DE4X5_MAX_MII 32
403
404
405
406
407 #define MII_CR_RST 0x8000
408 #define MII_CR_LPBK 0x4000
409 #define MII_CR_SPD 0x2000
410 #define MII_CR_10 0x0000
411 #define MII_CR_100 0x2000
412 #define MII_CR_ASSE 0x1000
413 #define MII_CR_PD 0x0800
414 #define MII_CR_ISOL 0x0400
415 #define MII_CR_RAN 0x0200
416 #define MII_CR_FDM 0x0100
417 #define MII_CR_CTE 0x0080
418
419
420
421
422 #define MII_SR_T4C 0x8000
423 #define MII_SR_TXFD 0x4000
424 #define MII_SR_TXHD 0x2000
425 #define MII_SR_TFD 0x1000
426 #define MII_SR_THD 0x0800
427 #define MII_SR_ASSC 0x0020
428 #define MII_SR_RFD 0x0010
429 #define MII_SR_ANC 0x0008
430 #define MII_SR_LKS 0x0004
431 #define MII_SR_JABD 0x0002
432 #define MII_SR_XC 0x0001
433
434
435
436
437 #define MII_ANA_TAF 0x03e0
438 #define MII_ANA_T4AM 0x0400
439 #define MII_ANA_TXAM 0x0180
440 #define MII_ANA_FDAM 0x0140
441 #define MII_ANA_HDAM 0x02a0
442 #define MII_ANA_100M 0x0380
443 #define MII_ANA_10M 0x0060
444 #define MII_ANA_CSMA 0x0001
445
446
447
448
449 #define MII_ANLPA_NP 0x8000
450 #define MII_ANLPA_ACK 0x4000
451 #define MII_ANLPA_RF 0x2000
452 #define MII_ANLPA_TAF 0x03e0
453 #define MII_ANLPA_T4AM 0x0400
454 #define MII_ANLPA_TXAM 0x0180
455 #define MII_ANLPA_FDAM 0x0140
456 #define MII_ANLPA_HDAM 0x02a0
457 #define MII_ANLPA_100M 0x0380
458 #define MII_ANLPA_10M 0x0060
459 #define MII_ANLPA_CSMA 0x0001
460
461
462
463
464 #define MEDIA_NWAY 0x0080
465 #define MEDIA_MII 0x0040
466 #define MEDIA_FIBRE 0x0008
467 #define MEDIA_AUI 0x0004
468 #define MEDIA_TP 0x0002
469 #define MEDIA_BNC 0x0001
470
471
472
473
474 #define FDR_FDACV 0x0000ffff
475
476
477
478
479 #define GPT_CON 0x00010000
480 #define GPT_VAL 0x0000ffff
481
482
483
484
485
486 #define GEP_LNP 0x00000080
487 #define GEP_SLNK 0x00000040
488 #define GEP_SDET 0x00000020
489 #define GEP_HRST 0x00000010
490 #define GEP_FDXD 0x00000008
491 #define GEP_PHYL 0x00000004
492 #define GEP_FLED 0x00000002
493 #define GEP_MODE 0x00000001
494 #define GEP_INIT 0x0000011f
495
496
497
498
499
500 #define SISR_LPC 0xffff0000
501 #define SISR_LPN 0x00008000
502 #define SISR_ANS 0x00007000
503 #define SISR_NSN 0x00000800
504 #define SISR_ANR_FDS 0x00000400
505 #define SISR_NRA 0x00000200
506 #define SISR_SRA 0x00000100
507 #define SISR_DAO 0x00000080
508 #define SISR_DAZ 0x00000040
509 #define SISR_DSP 0x00000020
510 #define SISR_DSD 0x00000010
511 #define SISR_APS 0x00000008
512 #define SISR_LKF 0x00000004
513 #define SISR_NCR 0x00000002
514 #define SISR_PAUI 0x00000001
515 #define SIA_RESET 0x00000000
516
517 #define ANS_NDIS 0x00000000
518 #define ANS_TDIS 0x00001000
519 #define ANS_ADET 0x00002000
520 #define ANS_ACK 0x00003000
521 #define ANS_CACK 0x00004000
522 #define ANS_NWOK 0x00005000
523 #define ANS_LCHK 0x00006000
524
525
526
527
528 #define SICR_SDM 0xffff0000
529 #define SICR_OE57 0x00008000
530 #define SICR_OE24 0x00004000
531 #define SICR_OE13 0x00002000
532 #define SICR_IE 0x00001000
533 #define SICR_EXT 0x00000000
534 #define SICR_D_SIA 0x00000400
535 #define SICR_DPLL 0x00000800
536 #define SICR_APLL 0x00000a00
537 #define SICR_D_RxM 0x00000c00
538 #define SICR_M_RxM 0x00000d00
539 #define SICR_LNKT 0x00000e00
540 #define SICR_SEL 0x00000f00
541 #define SICR_ASE 0x00000080
542 #define SICR_SIM 0x00000040
543 #define SICR_ENI 0x00000020
544 #define SICR_EDP 0x00000010
545 #define SICR_AUI 0x00000008
546 #define SICR_CAC 0x00000004
547 #define SICR_PS 0x00000002
548 #define SICR_SRL 0x00000001
549 #define SICR_RESET 0xffff0000
550
551
552
553
554 #define STRR_TAS 0x00008000
555 #define STRR_SPP 0x00004000
556 #define STRR_APE 0x00002000
557 #define STRR_LTE 0x00001000
558 #define STRR_SQE 0x00000800
559 #define STRR_CLD 0x00000400
560 #define STRR_CSQ 0x00000200
561 #define STRR_RSQ 0x00000100
562 #define STRR_ANE 0x00000080
563 #define STRR_HDE 0x00000040
564 #define STRR_CPEN 0x00000030
565 #define STRR_LSE 0x00000008
566 #define STRR_DREN 0x00000004
567 #define STRR_LBK 0x00000002
568 #define STRR_ECEN 0x00000001
569 #define STRR_RESET 0xffffffff
570
571
572
573
574 #define SIGR_LV2 0x00008000
575 #define SIGR_LE2 0x00004000
576 #define SIGR_FRL 0x00002000
577 #define SIGR_DPST 0x00001000
578 #define SIGR_LSD 0x00000800
579 #define SIGR_FLF 0x00000400
580 #define SIGR_FUSQ 0x00000200
581 #define SIGR_TSCK 0x00000100
582 #define SIGR_LV1 0x00000080
583 #define SIGR_LE1 0x00000040
584 #define SIGR_RWR 0x00000020
585 #define SIGR_RWD 0x00000010
586 #define SIGR_ABM 0x00000008
587 #define SIGR_JCK 0x00000004
588 #define SIGR_HUJ 0x00000002
589 #define SIGR_JBD 0x00000001
590 #define SIGR_RESET 0xffff0000
591
592
593
594
595 #define R_OWN 0x80000000
596 #define RD_FL 0x7fff0000
597 #define RD_ES 0x00008000
598 #define RD_LE 0x00004000
599 #define RD_DT 0x00003000
600 #define RD_RF 0x00000800
601 #define RD_MF 0x00000400
602 #define RD_FS 0x00000200
603 #define RD_LS 0x00000100
604 #define RD_TL 0x00000080
605 #define RD_CS 0x00000040
606 #define RD_FT 0x00000020
607 #define RD_RJ 0x00000010
608 #define RD_DB 0x00000004
609 #define RD_CE 0x00000002
610 #define RD_OF 0x00000001
611
612 #define RD_RER 0x02000000
613 #define RD_RCH 0x01000000
614 #define RD_RBS2 0x003ff800
615 #define RD_RBS1 0x000007ff
616
617
618
619
620 #define T_OWN 0x80000000
621 #define TD_ES 0x00008000
622 #define TD_TO 0x00004000
623 #define TD_LO 0x00000800
624 #define TD_NC 0x00000400
625 #define TD_LC 0x00000200
626 #define TD_EC 0x00000100
627 #define TD_HF 0x00000080
628 #define TD_CC 0x00000078
629 #define TD_LF 0x00000004
630 #define TD_UF 0x00000002
631 #define TD_DE 0x00000001
632
633 #define TD_IC 0x80000000
634 #define TD_LS 0x40000000
635 #define TD_FS 0x20000000
636 #define TD_FT1 0x10000000
637 #define TD_SET 0x08000000
638 #define TD_AC 0x04000000
639 #define TD_TER 0x02000000
640 #define TD_TCH 0x01000000
641 #define TD_DPD 0x00800000
642 #define TD_FT0 0x00400000
643 #define TD_RBS2 0x003ff800
644 #define TD_RBS1 0x000007ff
645
646 #define PERFECT_F 0x00000000
647 #define HASH_F TD_FT0
648 #define INVERSE_F TD_FT1
649 #define HASH_O_F TD_FT1| TD_F0
650
651
652
653
654 #define NC 0x0000
655 #define TP 0x0001
656 #define TP_NW 0x0002
657 #define BNC 0x0004
658 #define AUI 0x0008
659 #define BNC_AUI 0x0010
660 #define ANS 0x0020
661 #define ANS_1 0x0021
662
663 #define _10Mb 0x0040
664 #define _100Mb 0x0080
665 #define SPD_DET 0x0100
666 #define INIT 0x0200
667 #define EXT_SIA 0x0400
668 #define ANS_SUSPECT 0x0802
669 #define TP_SUSPECT 0x0803
670 #define BNC_AUI_SUSPECT 0x0804
671 #define EXT_SIA_SUSPECT 0x0805
672 #define BNC_SUSPECT 0x0806
673 #define AUI_SUSPECT 0x0807
674
675 #define AUTO 0x4000
676 #define TIMER_CB 0x80000000
677
678
679
680
681 #define PCI 0
682 #define EISA 1
683
684 #define HASH_TABLE_LEN 512
685 #define HASH_BITS 0x01ff
686
687 #define SETUP_FRAME_LEN 192
688 #define IMPERF_PA_OFFSET 156
689
690 #define POLL_DEMAND 1
691
692 #define LOST_MEDIA_THRESHOLD 3
693 #define LOST_MEDIA (lp->lostMedia > LOST_MEDIA_THRESHOLD)
694
695 #define MASK_INTERRUPTS 1
696 #define UNMASK_INTERRUPTS 0
697
698 #define DE4X5_STRLEN 8
699
700 #define DE4X5_INIT 0
701 #define DE4X5_RUN 1
702
703 #define DE4X5_SAVE_STATE 0
704 #define DE4X5_RESTORE_STATE 1
705
706
707
708
709 #define PERFECT 0
710 #define HASH_PERF 1
711 #define PERFECT_REJ 2
712 #define ALL_HASH 3
713
714 #define ALL 0
715 #define PHYS_ADDR_ONLY 1
716
717
718
719
720 #define NO 0
721 #define FALSE 0
722 #define CLOSED 0
723
724 #define YES ~0
725 #define TRUE ~0
726 #define OPEN ~0
727
728
729
730
731
732
733 #define NATIONAL_TX 0x2000
734 #define BROADCOM_T4 0x03e0
735 #define SEEQ_T4 0x0016
736 #define CYPRESS_T4 0x0014
737
738
739
740
741 #define SET_10Mb {\
742 if (lp->phy[lp->active].id) {\
743 omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FD);\
744 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
745 mii_wr(MII_CR_10|(de4x5_full_duplex?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
746 }\
747 omr |= ((de4x5_full_duplex ? OMR_FD : 0) | OMR_TTM);\
748 outl(omr, DE4X5_OMR);\
749 outl(0, DE4X5_GEP);\
750 } else {\
751 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FD));\
752 omr |= (de4x5_full_duplex ? OMR_FD : 0);\
753 outl(omr | OMR_TTM, DE4X5_OMR);\
754 outl((de4x5_full_duplex ? 0 : GEP_FDXD), DE4X5_GEP);\
755 }\
756 }
757
758 #define SET_100Mb {\
759 if (lp->phy[lp->active].id) {\
760 int fdx=0;\
761 if (lp->phy[lp->active].id == NATIONAL_TX) {\
762 mii_wr(mii_rd(0x18, lp->phy[lp->active].addr, DE4X5_MII) & ~0x2000,\
763 0x18, lp->phy[lp->active].addr, DE4X5_MII);\
764 }\
765 omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FD);\
766 sr = mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);\
767 if (!(sr & MII_ANA_T4AM) && de4x5_full_duplex) fdx=1;\
768 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
769 mii_wr(MII_CR_100|(fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
770 }\
771 if (fdx) omr |= OMR_FD;\
772 outl(omr, DE4X5_OMR);\
773 } else {\
774 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FD));\
775 omr |= (de4x5_full_duplex ? OMR_FD : 0);\
776 outl(omr | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);\
777 outl((de4x5_full_duplex ? 0 : GEP_FDXD) | GEP_MODE, DE4X5_GEP);\
778 }\
779 }
780
781
782 #define SET_100Mb_PDET {\
783 if (lp->phy[lp->active].id) {\
784 mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
785 omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FD));\
786 outl(omr, DE4X5_OMR);\
787 } else {\
788 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FD));\
789 outl(omr | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);\
790 outl(GEP_FDXD | GEP_MODE, DE4X5_GEP);\
791 }\
792 }
793
794
795
796
797 #include <linux/sockios.h>
798
799 #define DE4X5IOCTL SIOCDEVPRIVATE
800
801 struct de4x5_ioctl {
802 unsigned short cmd;
803 unsigned short len;
804 unsigned char *data;
805 };
806
807
808
809
810 #define DE4X5_GET_HWADDR 0x01
811 #define DE4X5_SET_HWADDR 0x02
812 #define DE4X5_SET_PROM 0x03
813 #define DE4X5_CLR_PROM 0x04
814 #define DE4X5_SAY_BOO 0x05
815 #define DE4X5_GET_MCA 0x06
816 #define DE4X5_SET_MCA 0x07
817 #define DE4X5_CLR_MCA 0x08
818 #define DE4X5_MCA_EN 0x09
819 #define DE4X5_GET_STATS 0x0a
820 #define DE4X5_CLR_STATS 0x0b
821 #define DE4X5_GET_OMR 0x0c
822 #define DE4X5_SET_OMR 0x0d
823 #define DE4X5_GET_REG 0x0e