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1 /********************************************************
2 * Header file for eata_dma.c and eata_pio.c *
3 * Linux EATA SCSI drivers *
4 * (c) 1993,94,95 Michael Neuffer *
5 *********************************************************
6 * last change: 95/11/07 *
7 ********************************************************/
8
9
10 #ifndef _EATA_GENERIC_H
11 #define _EATA_GENERIC_H
12
13
14
15 /*********************************************
16 * Misc. definitions *
17 *********************************************/
18
19 #ifndef TRUE
20 #define TRUE 1
21 #endif
22 #ifndef FALSE
23 #define FALSE 0
24 #endif
25
26 #define min(a,b) ((a<b)?(a):(b))
27
28 #define R_LIMIT 0x20000
29
30 #define MAXISA 4
31 #define MAXEISA 16
32 #define MAXPCI 16
33 #define MAXIRQ 16
34 #define MAXTARGET 16
35 #define MAXCHANNEL 3
36
37 #define IS_ISA 'I'
38 #define IS_EISA 'E'
39 #define IS_PCI 'P'
40
41 #define BROKEN_INQUIRY 1
42
43 #define BUSMASTER 0xff
44 #define PIO 0xfe
45
46 #define EATA_SIGNATURE 0x45415441 /* BIG ENDIAN coded "EATA" sig. */
47
48 #define DPT_ID1 0x12
49 #define DPT_ID2 0x14
50
51 #define ATT_ID1 0x06
52 #define ATT_ID2 0x94
53 #define ATT_ID3 0x0
54
55 #define NEC_ID1 0x38
56 #define NEC_ID2 0xa3
57 #define NEC_ID3 0x82
58
59
60 #define EATA_CP_SIZE 44
61
62 #define MAX_PCI_DEVICES 32 /* Maximum # Of Devices Per Bus */
63 #define MAX_METHOD_2 16 /* Max Devices For Method 2 */
64 #define MAX_PCI_BUS 16 /* Maximum # Of Busses Allowed */
65
66 #define SG_SIZE 64
67 #define SG_SIZE_BIG 252 /* max. 8096 elements, 64k */
68
69 #define TYPE_DISK_QUEUE 16
70 #define TYPE_TAPE_QUEUE 4
71 #define TYPE_ROM_QUEUE 4
72 #define TYPE_OTHER_QUEUE 2
73
74 #define FREE 0
75 #define OK 0
76 #define NO_TIMEOUT 0
77 #define USED 1
78 #define TIMEOUT 2
79 #define RESET 4
80 #define LOCKED 8
81
82 #define HD(cmd) ((hostdata *)&(cmd->host->hostdata))
83 #define CD(cmd) ((struct eata_ccb *)(cmd->host_scribble))
84 #define SD(host) ((hostdata *)&(host->hostdata))
85
86 #define DELAY(x) { __u32 i; i = jiffies + (x * HZ); while (jiffies < i) barrier(); }
87 #define DEL2(x) { __u32 i; for (i = 0; i < 0xffff * x; i++); }
88
89 /***********************************************
90 * EATA Command & Register definitions *
91 ***********************************************/
92 #define PCI_REG_DPTconfig 0x40
93 #define PCI_REG_PumpModeAddress 0x44
94 #define PCI_REG_PumpModeData 0x48
95 #define PCI_REG_ConfigParam1 0x50
96 #define PCI_REG_ConfigParam2 0x54
97
98
99 #define EATA_CMD_PIO_SETUPTEST 0xc6
100 #define EATA_CMD_PIO_READ_CONFIG 0xf0
101 #define EATA_CMD_PIO_SET_CONFIG 0xf1
102 #define EATA_CMD_PIO_SEND_CP 0xf2
103 #define EATA_CMD_PIO_RECEIVE_SP 0xf3
104 #define EATA_CMD_PIO_TRUNC 0xf4
105
106 #define EATA_CMD_RESET 0xf9
107 #define EATA_CMD_IMMEDIATE 0xfa
108
109 #define EATA_CMD_DMA_READ_CONFIG 0xfd
110 #define EATA_CMD_DMA_SET_CONFIG 0xfe
111 #define EATA_CMD_DMA_SEND_CP 0xff
112
113 #define ECS_EMULATE_SENSE 0xd4
114
115 #define EATA_GENERIC_ABORT 0x00
116 #define EATA_SPECIFIC_RESET 0x01
117 #define EATA_BUS_RESET 0x02
118 #define EATA_SPECIFIC_ABORT 0x03
119 #define EATA_QUIET_INTR 0x04
120 #define EATA_COLD_BOOT_HBA 0x06 /* Only as a last resort */
121 #define EATA_FORCE_IO 0x07
122
123
124 #define HA_WCOMMAND 0x07 /* command register offset */
125 #define HA_WCOMMAND2 0x06 /* immediate command offset */
126 #define HA_WSUBCODE 0x05
127 #define HA_WSUBLUN 0x04
128 #define HA_WDMAADDR 0x02 /* DMA address LSB offset */
129 #define HA_RAUXSTAT 0x08 /* aux status register offset*/
130 #define HA_RSTATUS 0x07 /* status register offset */
131 #define HA_RDATA 0x00 /* data register (16bit) */
132
133 #define HA_ABUSY 0x01 /* aux busy bit */
134 #define HA_AIRQ 0x02 /* aux IRQ pending bit */
135 #define HA_SERROR 0x01 /* pr. command ended in error*/
136 #define HA_SMORE 0x02 /* more data soon to come */
137 #define HA_SCORR 0x04 /* data corrected */
138 #define HA_SDRQ 0x08 /* data request active */
139 #define HA_SSC 0x10 /* seek complete */
140 #define HA_SFAULT 0x20 /* write fault */
141 #define HA_SREADY 0x40 /* drive ready */
142 #define HA_SBUSY 0x80 /* drive busy */
143 #define HA_SDRDY HA_SSC+HA_SREADY+HA_SDRQ
144
145 /**********************************************
146 * Message definitions *
147 **********************************************/
148
149 #define HA_NO_ERROR 0x00 /* No Error */
150 #define HA_ERR_SEL_TO 0x01 /* Selection Timeout */
151 #define HA_ERR_CMD_TO 0x02 /* Command Timeout */
152 #define HA_ERR_RESET 0x03 /* SCSI Bus Reset Received */
153 #define HA_INIT_POWERUP 0x04 /* Initial Controller Power-up */
154 #define HA_UNX_BUSPHASE 0x05 /* Unexpected Bus Phase */
155 #define HA_UNX_BUS_FREE 0x06 /* Unexpected Bus Free */
156 #define HA_BUS_PARITY 0x07 /* Bus Parity Error */
157 #define HA_SCSI_HUNG 0x08 /* SCSI Hung */
158 #define HA_UNX_MSGRJCT 0x09 /* Unexpected Message Rejected */
159 #define HA_RESET_STUCK 0x0a /* SCSI Bus Reset Stuck */
160 #define HA_RSENSE_FAIL 0x0b /* Auto Request-Sense Failed */
161 #define HA_PARITY_ERR 0x0c /* Controller Ram Parity Error */
162 #define HA_CP_ABORT_NA 0x0d /* Abort Message sent to non-active cmd */
163 #define HA_CP_ABORTED 0x0e /* Abort Message sent to active cmd */
164 #define HA_CP_RESET_NA 0x0f /* Reset Message sent to non-active cmd */
165 #define HA_CP_RESET 0x10 /* Reset Message sent to active cmd */
166 #define HA_ECC_ERR 0x11 /* Controller Ram ECC Error */
167 #define HA_PCI_PARITY 0x12 /* PCI Parity Error */
168 #define HA_PCI_MABORT 0x13 /* PCI Master Abort */
169 #define HA_PCI_TABORT 0x14 /* PCI Target Abort */
170 #define HA_PCI_STABORT 0x15 /* PCI Signaled Target Abort */
171
172 /**********************************************
173 * Other definitions *
174 **********************************************/
175
176 struct reg_bit { /* reading this one will clear the interrupt */
177 __u8 error:1; /* previous command ended in an error */
178 __u8 more:1; /* more DATA coming soon, poll BSY & DRQ (PIO) */
179 __u8 corr:1; /* data read was successfully corrected with ECC*/
180 __u8 drq:1; /* data request active */
181 __u8 sc:1; /* seek complete */
182 __u8 fault:1; /* write fault */
183 __u8 ready:1; /* drive ready */
184 __u8 busy:1; /* controller busy */
185 };
186
187 struct reg_abit { /* reading this won't clear the interrupt */
188 __u8 abusy:1; /* auxiliary busy */
189 __u8 irq:1; /* set when drive interrupt is asserted */
190 __u8 dummy:6;
191 };
192
193 struct eata_register { /* EATA register set */
194 __u8 data_reg[2]; /* R, couldn't figure this one out */
195 __u8 cp_addr[4]; /* W, CP address register */
196 union {
197 __u8 command; /* W, command code: [read|set] conf, send CP*/
198 struct reg_bit status; /* R, see register_bit1 */
199 __u8 statusbyte;
200 } ovr;
201 struct reg_abit aux_stat; /* R, see register_bit2 */
202 };
203
204 struct get_conf { /* Read Configuration Array */
205 __u32 len; /* Should return 0x22, 0x24, etc */
206 __u32 signature; /* Signature MUST be "EATA" */
207 __u8 version2:4,
208 version:4; /* EATA Version level */
209 __u8 OCS_enabled:1, /* Overlap Command Support enabled */
210 TAR_support:1, /* SCSI Target Mode supported */
211 TRNXFR:1, /* Truncate Transfer Cmd not necessary *
212 * Only used in PIO Mode */
213 MORE_support:1, /* MORE supported (only PIO Mode) */
214 DMA_support:1, /* DMA supported Driver uses only *
215 * this mode */
216 DMA_valid:1, /* DRQ value in Byte 30 is valid */
217 ATA:1, /* ATA device connected (not supported) */
218 HAA_valid:1; /* Hostadapter Address is valid */
219
220 __u16 cppadlen; /* Number of pad bytes send after CD data *
221 * set to zero for DMA commands */
222 __u8 scsi_id[4]; /* SCSI ID of controller 2-0 Byte 0 res. *
223 * if not, zero is returned */
224 __u32 cplen; /* CP length: number of valid cp bytes */
225 __u32 splen; /* Number of bytes returned after *
226 * Receive SP command */
227 __u16 queuesiz; /* max number of queueable CPs */
228 __u16 dummy;
229 __u16 SGsiz; /* max number of SG table entries */
230 __u8 IRQ:4, /* IRQ used this HA */
231 IRQ_TR:1, /* IRQ Trigger: 0=edge, 1=level */
232 SECOND:1, /* This is a secondary controller */
233 DMA_channel:2; /* DRQ index, DRQ is 2comp of DRQX */
234 __u8 sync; /* device at ID 7 tru 0 is running in *
235 * synchronous mode, this will disappear */
236 __u8 DSBLE:1, /* ISA i/o addressing is disabled */
237 FORCADR:1, /* i/o address has been forced */
238 SG_64K:1,
239 SG_UAE:1,
240 :4;
241 __u8 MAX_ID:5, /* Max number of SCSI target IDs */
242 MAX_CHAN:3; /* Number of SCSI busses on HBA */
243 __u8 MAX_LUN; /* Max number of LUNs */
244 __u8 :3,
245 AUTOTRM:1,
246 M1_inst:1,
247 ID_qest:1, /* Raidnum ID is questionable */
248 is_PCI:1, /* HBA is PCI */
249 is_EISA:1; /* HBA is EISA */
250 __u8 unused[478];
251 };
252
253 struct eata_sg_list
254 {
255 __u32 data;
256 __u32 len;
257 };
258
259 struct eata_ccb { /* Send Command Packet structure */
260
261 __u8 SCSI_Reset:1, /* Cause a SCSI Bus reset on the cmd */
262 HBA_Init:1, /* Cause Controller to reinitialize */
263 Auto_Req_Sen:1, /* Do Auto Request Sense on errors */
264 scatter:1, /* Data Ptr points to a SG Packet */
265 Resrvd:1, /* RFU */
266 Interpret:1, /* Interpret the SCSI cdb of own use */
267 DataOut:1, /* Data Out phase with command */
268 DataIn:1; /* Data In phase with command */
269 __u8 reqlen; /* Request Sense Length *
270 * Valid if Auto_Req_Sen=1 */
271 __u8 unused[3];
272 __u8 FWNEST:1, /* send cmd to phys RAID component */
273 unused2:7;
274 __u8 Phsunit:1, /* physical unit on mirrored pair */
275 I_AT:1, /* inhibit address translation */
276 I_HBA_C:1, /* HBA inhibit caching */
277 unused3:5;
278
279 __u8 cp_id:5, /* SCSI Device ID of target */
280 cp_channel:3; /* SCSI Channel # of HBA */
281 __u8 cp_lun:3,
282 :2,
283 cp_luntar:1, /* CP is for target ROUTINE */
284 cp_dispri:1, /* Grant disconnect privilege */
285 cp_identify:1; /* Always TRUE */
286 __u8 cp_msg1; /* Message bytes 0-3 */
287 __u8 cp_msg2;
288 __u8 cp_msg3;
289 __u8 cp_cdb[12]; /* Command Descriptor Block */
290 __u32 cp_datalen; /* Data Transfer Length *
291 * If scatter=1 len of sg package */
292 void *cp_viraddr; /* address of this ccb */
293 __u32 cp_dataDMA; /* Data Address, if scatter=1 *
294 * address of scatter packet */
295 __u32 cp_statDMA; /* address for Status Packet */
296 __u32 cp_reqDMA; /* Request Sense Address, used if *
297 * CP command ends with error */
298 /* Additional CP info begins here */
299 __u32 timestamp; /* Needed to measure command latency */
300 __u32 timeout;
301 __u8 sizeindex;
302 __u8 rw_latency;
303 __u8 retries;
304 __u8 status; /* status of this queueslot */
305 Scsi_Cmnd *cmd; /* address of cmd */
306 struct eata_sg_list *sg_list;
307 };
308
309
310 struct eata_sp {
311 __u8 hba_stat:7, /* HBA status */
312 EOC:1; /* True if command finished */
313 __u8 scsi_stat; /* Target SCSI status */
314 __u8 reserved[2];
315 __u32 residue_len; /* Number of bytes not transferred */
316 struct eata_ccb *ccb; /* Address set in COMMAND PACKET */
317 __u8 msg[12];
318 };
319
320 typedef struct hstd {
321 __u8 vendor[9];
322 __u8 name[18];
323 __u8 revision[6];
324 __u8 EATA_revision;
325 __u8 bustype; /* bustype of HBA */
326 __u8 channel; /* # of avail. scsi channels */
327 __u8 state; /* state of HBA */
328 __u8 primary; /* true if primary */
329 __u8 broken_INQUIRY:1; /* This is an EISA HBA with *
330 * broken INQUIRY */
331 __u8 do_latency; /* Latency measurement flag */
332 __u32 reads[13];
333 __u32 writes[13];
334 __u32 reads_lat[12][4];
335 __u32 writes_lat[12][4];
336 /* state of Target (RESET,..) */
337 __u8 t_state[MAXCHANNEL][MAXTARGET];
338 /* timeouts on target */
339 __u32 t_timeout[MAXCHANNEL][MAXTARGET];
340 __u32 last_ccb; /* Last used ccb */
341 __u32 cplen; /* size of CP in words */
342 __u16 cppadlen; /* pad length of cp in words */
343 int queuesize;
344 __u8 hostid; /* SCSI ID of HBA */
345 __u8 devflags; /* bits set for detected devices */
346 __u8 moresupport; /* HBA supports MORE flag */
347 struct Scsi_Host *next;
348 struct Scsi_Host *prev;
349 struct eata_sp sp; /* status packet */
350 struct eata_ccb ccb[0]; /* ccb array begins here */
351 }hostdata;
352
353 /* structure for max. 2 emulated drives */
354 struct drive_geom_emul {
355 __u8 trans; /* translation flag 1=transl */
356 __u8 channel; /* SCSI channel number */
357 __u8 HBA; /* HBA number (prim/sec) */
358 __u8 id; /* drive id */
359 __u8 lun; /* drive lun */
360 __u32 heads; /* number of heads */
361 __u32 sectors; /* number of sectors */
362 __u32 cylinder; /* number of cylinders */
363 };
364
365 struct geom_emul {
366 __u8 bios_drives; /* number of emulated drives */
367 struct drive_geom_emul drv[2]; /* drive structures */
368 };
369
370 #endif /* _EATA_GENERIC_H */
371
372 /*
373 * Overrides for Emacs so that we almost follow Linus's tabbing style.
374 * Emacs will notice this stuff at the end of the file and automatically
375 * adjust the settings for this buffer only. This must remain at the end
376 * of the file.
377 * ---------------------------------------------------------------------------
378 * Local variables:
379 * c-indent-level: 4
380 * c-brace-imaginary-offset: 0
381 * c-brace-offset: -4
382 * c-argdecl-indent: 4
383 * c-label-offset: -4
384 * c-continued-statement-offset: 4
385 * c-continued-brace-offset: 0
386 * tab-width: 8
387 * End:
388 */
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*/