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1 /*
2 * i82596 ethernet controller bits and structures (little endian)
3 *
4 * $Id: i82596.h,v 1.7 1996/03/18 15:31:47 rick Exp $
5 */
6
7 /************************************************************************/
8 /* */
9 /* PORT commands (p. 4-20). The least significant nibble is one */
10 /* of these commands, the rest of the command is a memory address */
11 /* aligned on a 16 byte boundary. Note that port commands must */
12 /* be written to the PORT address and the PORT address+2 with two */
13 /* halfword writes. Write the LSH first to PORT, then the MSH to */
14 /* PORT+2. Blame Intel. */
15 /* */
16 /************************************************************************/
17 #define I596_PORT_RESET 0x0 /* Reset. Wait 5 SysClks & 10 TxClks */
18 #define I596_PORT_SELFTEST 0x1 /* Do a selftest */
19 #define I596_PORT_SCP_ADDR 0x2 /* Set new SCP address */
20 #define I596_PORT_DUMP 0x3 /* Dump internal data structures */
21
22 /*
23 * I596_ST: Selftest results (p. 4-21)
24 */
25 typedef volatile struct
26 {
27 ulong signature; /* ROM checksum */
28 ulong result; /* Selftest results: non-zero is a failure */
29 } I596_ST;
30
31 #define I596_ST_SELFTEST_FAIL 0x1000 /* Selftest Failed */
32 #define I596_ST_DIAGNOSE_FAIL 0x0020 /* Diagnose Failed */
33 #define I596_ST_BUSTIMER_FAIL 0x0010 /* Bus Timer Failed */
34 #define I596_ST_REGISTER_FAIL 0x0008 /* Register Failed */
35 #define I596_ST_ROM_FAIL 0x0004 /* ROM Failed */
36
37 /*
38 * I596_DUMP: Dump results
39 */
40 typedef volatile struct
41 {
42 ulong dump[77];
43 } I596_DUMP;
44
45 /************************************************************************/
46 /* */
47 /* I596_TBD: Transmit Buffer Descriptor (p. 4-59) */
48 /* */
49 /************************************************************************/
50 typedef volatile struct _I596_TBD
51 {
52 ulong count;
53 vol struct _I596_TBD *next;
54 uchar *buf;
55 ushort unused1;
56 ushort unused2;
57 } I596_TBD;
58
59 #define I596_TBD_NOLINK ((I596_TBD *) 0xffffffff)
60 #define I596_TBD_EOF 0x8000
61 #define I596_TBD_COUNT_MASK 0x3fff
62
63 /************************************************************************/
64 /* */
65 /* I596_TFD: Transmit Frame Descriptor (p. 4-56) */
66 /* a.k.a. I596_CB_XMIT */
67 /* */
68 /************************************************************************/
69 typedef volatile struct
70 {
71 ushort status;
72 ushort cmd;
73 union _I596_CB *next;
74 I596_TBD *tbdp;
75 ulong count; /* for speed */
76 uchar addr[6];
77 #if 1 /* We don't use these */
78 ushort len;
79 uchar data[1];
80 #endif
81 } I596_TFD;
82
83 #define I596_TFD_NOCRC 0x0010 /* cmd: No CRC insertion */
84 #define I596_TFD_FLEX 0x0008 /* cmd: Flexible mode */
85
86 /************************************************************************/
87 /* */
88 /* I596_RBD: Receive Buffer Descriptor (p. 4-84) */
89 /* */
90 /************************************************************************/
91 typedef volatile struct _I596_RBD
92 {
93 #if INTEL_RENTENTIVE
94 ushort count; /* Length of data in buf */
95 ushort offset;
96 #else
97 ulong count; /* Length of data in buf */
98 #endif
99 vol struct _I596_RBD *next; /* Next buffer descriptor in list */
100 uchar *buf; /* Data buffer */
101 #if INTEL_RENTENTIVE
102 ushort size; /* Size of buf (constant) */
103 ushort zero;
104 #else
105 ulong size; /* Size of buf (constant) */
106 #endif
107 /* application defined data */
108 uchar chan;
109 uchar refcnt;
110 ushort len;
111 } I596_RBD;
112
113 #define I596_RBD_NOLINK ((I596_RBD *) 0xffffffff)
114 #define I596_RBD_EOF 0x8000 /* This is last buffer in a frame */
115 #define I596_RBD_F 0x4000 /* The actual count is valid */
116
117 #define I596_RBD_EL 0x8000 /* Last buffer in list */
118
119 /************************************************************************/
120 /* */
121 /* I596_RFD: Receive Frame Descriptor (p. 4-79) */
122 /* */
123 /************************************************************************/
124 typedef volatile struct _I596_RFD
125 {
126 ushort status;
127 ushort cmd;
128 vol struct _I596_RFD *next;
129 vol struct _I596_RBD *rbdp;
130 ushort count; /* Len of data in RFD: always 0 */
131 ushort size; /* Size of RFD buffer: always 0 */
132 # if 1 /* We don't use these */
133 uchar addr[6];
134 ushort len;
135 uchar data[1];
136 # endif
137 } I596_RFD;
138
139 #define I596_RFD_C 0x8000 /* status: frame complete */
140 #define I596_RFD_B 0x4000 /* status: frame busy or waiting */
141 #define I596_RFD_OK 0x2000 /* status: frame OK */
142 #define I596_RFD_ERR_LENGTH 0x1000 /* status: length error */
143 #define I596_RFD_ERR_CRC 0x0800 /* status: CRC error */
144 #define I596_RFD_ERR_ALIGN 0x0400 /* status: alignment error */
145 #define I596_RFD_ERR_NOBUFS 0x0200 /* status: resource error */
146 #define I596_RFD_ERR_DMA 0x0100 /* status: DMA error */
147 #define I596_RFD_ERR_SHORT 0x0080 /* status: too short error */
148 #define I596_RFD_NOMATCH 0x0002 /* status: IA was not matched */
149 #define I596_RFD_COLLISION 0x0001 /* status: collision during receive */
150
151 #define I596_RFD_EL 0x8000 /* cmd: end of RFD list */
152 #define I596_RFD_FLEX 0x0008 /* cmd: Flexible mode */
153 #define I596_RFD_EOF 0x8000 /* count: last buffer in the frame */
154 #define I596_RFD_F 0x4000 /* count: The actual count is valid */
155
156 /************************************************************************/
157 /* */
158 /* Commands */
159 /* */
160 /************************************************************************/
161
162 /* values for cmd halfword in all the structs below */
163 #define I596_CB_CMD 0x07 /* CB COMMANDS */
164 #define I596_CB_CMD_NOP 0
165 #define I596_CB_CMD_IA 1
166 #define I596_CB_CMD_CONF 2
167 #define I596_CB_CMD_MCAST 3
168 #define I596_CB_CMD_XMIT 4
169 #define I596_CB_CMD_TDR 5
170 #define I596_CB_CMD_DUMP 6
171 #define I596_CB_CMD_DIAG 7
172
173 #define I596_CB_CMD_EL 0x8000 /* CB is last in linked list */
174 #define I596_CB_CMD_S 0x4000 /* Suspend after execution */
175 #define I596_CB_CMD_I 0x2000 /* cause interrupt */
176
177 /* values for the status halfword in all the struct below */
178 #define I596_CB_STATUS 0xF000 /* All four status bits */
179 #define I596_CB_STATUS_C 0x8000 /* Command complete */
180 #define I596_CB_STATUS_B 0x4000 /* Command busy executing */
181 #define I596_CB_STATUS_C_OR_B 0xC000 /* Command complete or busy */
182 #define I596_CB_STATUS_OK 0x2000 /* Command complete, no errors */
183 #define I596_CB_STATUS_A 0x1000 /* Command busy executing */
184
185 #define I596_CB_NOLINK ((I596_CB *) 0xffffffff)
186
187 /*
188 * I596_CB_NOP: NOP Command (p. 4-34)
189 */
190 typedef volatile struct
191 {
192 ushort status;
193 ushort cmd;
194 union _I596_CB *next;
195 } I596_CB_NOP;
196
197 /*
198 * Same as above, but command and status in one ulong for speed
199 */
200 typedef volatile struct
201 {
202 ulong csr;
203 union _I596_CB *next;
204 } I596_CB_FAST;
205 #define FASTs(X) (X)
206 #define FASTc(X) ((X)<<16)
207
208 /*
209 * I596_CB_IA: Individual (MAC) Address Command (p. 4-35)
210 */
211 typedef volatile struct
212 {
213 ushort status;
214 ushort cmd;
215 union _I596_CB *next;
216 uchar addr[6];
217 } I596_CB_IA;
218
219 /*
220 * I596_CB_CONF: Configure Command (p. 4-37)
221 */
222 typedef volatile struct
223 {
224 ushort status;
225 ushort cmd;
226 union _I596_CB *next;
227 uchar conf[14];
228 } I596_CB_CONF;
229
230 #define I596_CONF0_P 0x80 /* Enable RBD Prefetch Bit */
231 #define I596_CONF0_COUNT 14 /* Count of configuration bytes */
232
233 #define I596_CONF1_MON_OFF 0xC0 /* Monitor mode: Monitor off */
234 #define I596_CONF1_MON_ON 0x80 /* Monitor mode: Monitor on */
235 #define I596_CONF1_TxFIFO(W) (W) /* TxFIFO trigger, in words */
236
237 #define I596_CONF2_SAVEBF 0x80 /* Save bad frames */
238
239 #define I596_CONF3_ADDRLEN(B) (B) /* Address length */
240 #define I596_CONF3_NOSRCINSERT 0x08 /* Do not insert source address */
241 #define I596_CONF3_PREAMBLE8 0x20 /* 8 byte preamble */
242 #define I596_CONF3_LOOPOFF 0x00 /* Loopback: Off */
243 #define I596_CONF3_LOOPINT 0x40 /* Loopback: internal */
244 #define I596_CONF3_LOOPEXT 0xC0 /* Loopback: external */
245
246 #define I596_CONF4_LINPRI(ST) (ST) /* Linear priority: slot times */
247 #define I596_CONF4_EXPPRI(ST) (ST) /* Exponential priority: slot times */
248 #define I596_CONF4_IEEE_BOM 0 /* IEEE 802.3 backoff method */
249
250 #define I596_CONF5_IFS(X) (X) /* Interframe spacing in clocks */
251
252 #define I596_CONF6_ST_LOW(X) (X&255) /* Slot time, low byte */
253
254 #define I596_CONF7_ST_HI(X) (X>>8) /* Slot time, high bits */
255 #define I596_CONF7_RETRY(X) (X<<4) /* Max retry number */
256
257 #define I596_CONF8_PROMISC 0x01 /* Rcv all frames */
258 #define I596_CONF8_NOBROAD 0x02
259 #define I596_CONF8_MANCHESTER 0x04
260 #define I596_CONF8_TxNOCRS 0x08
261 #define I596_CONF8_NOCRC 0x10
262 #define I596_CONF8_CRC_CCITT 0x20
263 #define I596_CONF8_BITSTUFFING 0x40
264 #define I596_CONF8_PADDING 0x80
265
266 #define I596_CONF9_CSFILTER(X) (X)
267 #define I596_CONF9_CSINT(X) 0x08
268 #define I596_CONF9_CDFILTER(X) (X<<4)
269 #define I596_CONF9_CDINT(X) 0x80
270
271 #define I596_CONF10_MINLEN(X) (X) /* Minimum frame length */
272
273 #define I596_CONF11_PRECRS_ 0x01 /* Preamble before carrier sense */
274 #define I596_CONF11_LNGFLD_ 0x02 /* Padding in End of Carrier */
275 #define I596_CONF11_CRCINM_ 0x04 /* CRC in memory */
276 #define I596_CONF11_AUTOTX 0x08 /* Auto retransmit */
277 #define I596_CONF11_CSBSAC_ 0x10 /* Collision detect by src addr cmp. */
278 #define I596_CONF11_MCALL_ 0x20 /* Multicast all */
279
280 #define I596_CONF13_RESERVED 0x3f /* Reserved: must be ones */
281 #define I596_CONF13_MULTIA 0x40 /* Enable multiple addr. reception */
282 #define I596_CONF13_DISBOF 0x80 /* Disable backoff algorithm */
283 /*
284 * I596_CB_MCAST: Multicast-Setup Command (p. 4-54)
285 */
286 typedef volatile struct
287 {
288 ushort status;
289 ushort cmd;
290 union _I596_CB *next;
291 ushort count; /* Number of 6-byte addrs that follow */
292 uchar addr[6][1];
293 } I596_CB_MCAST;
294
295 /*
296 * I596_CB_XMIT: Transmit Command (p. 4-56)
297 */
298 typedef I596_TFD I596_CB_XMIT;
299
300 #define I596_CB_XMIT_NOCRC 0x0010 /* cmd: No CRC insertion */
301 #define I596_CB_XMIT_FLEX 0x0008 /* cmd: Flexible memory mode */
302
303 #define I596_CB_XMIT_ERR_LATE 0x0800 /* status: error: late collision */
304 #define I596_CB_XMIT_ERR_NOCRS 0x0400 /* status: error: no carriers sense */
305 #define I596_CB_XMIT_ERR_NOCTS 0x0200 /* status: error: loss of CTS */
306 #define I596_CB_XMIT_ERR_UNDER 0x0100 /* status: error: DMA underrun */
307 #define I596_CB_XMIT_ERR_MAXCOL 0x0020 /* status: error: maximum collisions */
308 #define I596_CB_XMIT_COLLISIONS 0x000f /* status: number of collisions */
309
310 /*
311 * I596_CB_TDR: Time Domain Reflectometry Command (p. 4-63)
312 */
313 typedef volatile struct
314 {
315 ushort status;
316 ushort cmd;
317 union _I596_CB *next;
318 ushort time;
319 } I596_CB_TDR;
320
321 /*
322 * I596_CB_DUMP: Dump Command (p. 4-65)
323 */
324 typedef volatile struct
325 {
326 ushort status;
327 ushort cmd;
328 union _I596_CB *next;
329 uchar *buf;
330 } I596_CB_DUMP;
331
332 /*
333 * I596_CB_DIAG: Diagnose Command (p. 4-77)
334 */
335 typedef volatile struct
336 {
337 ushort status;
338 ushort cmd;
339 union _I596_CB *next;
340 } I596_CB_DIAG;
341
342 /*
343 * I596_CB: Command Block
344 */
345 typedef union _I596_CB
346 {
347 I596_CB_NOP nop;
348 I596_CB_IA ia;
349 I596_CB_CONF conf;
350 I596_CB_MCAST mcast;
351 I596_CB_XMIT xmit;
352 I596_CB_TDR tdr;
353 I596_CB_DUMP dump;
354 I596_CB_DIAG diag;
355
356 /* command and status in one ulong for speed... */
357 I596_CB_FAST fast;
358 } I596_CB;
359
360 /************************************************************************/
361 /* */
362 /* I596_SCB: System Configuration Block (p. 4-26) */
363 /* */
364 /************************************************************************/
365 typedef volatile struct
366 {
367 volatile ushort status; /* Status word */
368 volatile ushort cmd; /* Command word */
369 I596_CB *cbp;
370 I596_RFD *rfdp;
371 ulong crc_errs;
372 ulong align_errs;
373 ulong resource_errs;
374 ulong overrun_errs;
375 ulong rcvcdt_errs;
376 ulong short_errs;
377 ushort toff;
378 ushort ton;
379 } I596_SCB;
380
381 /* cmd halfword values */
382 #define I596_SCB_ACK 0xF000 /* ACKNOWLEDGMENTS */
383 #define I596_SCB_ACK_CX 0x8000 /* Ack command completion */
384 #define I596_SCB_ACK_FR 0x4000 /* Ack received frame */
385 #define I596_SCB_ACK_CNA 0x2000 /* Ack command unit not active */
386 #define I596_SCB_ACK_RNR 0x1000 /* Ack rcv unit not ready */
387 #define I596_SCB_ACK_ALL 0xF000 /* Ack everything */
388
389 #define I596_SCB_CUC 0x0700 /* COMMAND UNIT COMMANDS */
390 #define I596_SCB_CUC_NOP 0x0000 /* No operation */
391 #define I596_SCB_CUC_START 0x0100 /* Start execution of first CB */
392 #define I596_SCB_CUC_RESUME 0x0200 /* Resume execution */
393 #define I596_SCB_CUC_SUSPEND 0x0300 /* Suspend after current CB */
394 #define I596_SCB_CUC_ABORT 0x0400 /* Abort current CB immediately */
395 #define I596_SCB_CUC_LOAD 0x0500 /* Load Bus throttle timers */
396 #define I596_SCB_CUC_LOADIMM 0x0600 /* Load Bus throttle timers, now */
397
398 #define I596_SCB_RUC 0x0070 /* RECEIVE UNIT COMMANDS */
399 #define I596_SCB_RUC_NOP 0x0000 /* No operation */
400 #define I596_SCB_RUC_START 0x0010 /* Start reception */
401 #define I596_SCB_RUC_RESUME 0x0020 /* Resume reception */
402 #define I596_SCB_RUC_SUSPEND 0x0030 /* Suspend reception */
403 #define I596_SCB_RUC_ABORT 0x0040 /* Abort reception */
404
405 #define I596_SCB_RESET 0x0080 /* Hard reset chip */
406
407 /* status halfword values */
408 #define I596_SCB_STAT 0xF000 /* STATUS */
409 #define I596_SCB_CX 0x8000 /* command completion */
410 #define I596_SCB_FR 0x4000 /* received frame */
411 #define I596_SCB_CNA 0x2000 /* command unit not active */
412 #define I596_SCB_RNR 0x1000 /* rcv unit not ready */
413
414 #define I596_SCB_CUS 0x0700 /* COMMAND UNIT STATUS */
415 #define I596_SCB_CUS_IDLE 0x0000 /* Idle */
416 #define I596_SCB_CUS_SUSPENDED 0x0100 /* Suspended */
417 #define I596_SCB_CUS_ACTIVE 0x0200 /* Active */
418
419 #define I596_SCB_RUS 0x00F0 /* RECEIVE UNIT STATUS */
420 #define I596_SCB_RUS_IDLE 0x0000 /* Idle */
421 #define I596_SCB_RUS_SUSPENDED 0x0010 /* Suspended */
422 #define I596_SCB_RUS_NORES 0x0020 /* No Resources */
423 #define I596_SCB_RUS_READY 0x0040 /* Ready */
424 #define I596_SCB_RUS_NORBDS 0x0080 /* No more RBDs modifier */
425
426 #define I596_SCB_LOADED 0x0008 /* Bus timers loaded */
427
428 /************************************************************************/
429 /* */
430 /* I596_ISCP: Intermediate System Configuration Ptr (p 4-26) */
431 /* */
432 /************************************************************************/
433 typedef volatile struct
434 {
435 ulong busy; /* Set to 1; I596 clears it when scbp is read */
436 I596_SCB *scbp;
437 } I596_ISCP;
438
439 /************************************************************************/
440 /* */
441 /* I596_SCP: System Configuration Pointer (p. 4-23) */
442 /* */
443 /************************************************************************/
444 typedef volatile struct
445 {
446 ulong sysbus;
447 ulong dummy;
448 I596_ISCP *iscpp;
449 } I596_SCP;
450
451 /* .sysbus values */
452 #define I596_SCP_RESERVED 0x400000 /* Reserved bits must be set */
453 #define I596_SCP_INTLOW 0x200000 /* Intr. Polarity active low */
454 #define I596_SCP_INTHIGH 0 /* Intr. Polarity active high */
455 #define I596_SCP_LOCKDIS 0x100000 /* Lock Function disabled */
456 #define I596_SCP_LOCKEN 0 /* Lock Function enabled */
457 #define I596_SCP_ETHROTTLE 0x080000 /* External Bus Throttle */
458 #define I596_SCP_ITHROTTLE 0 /* Internal Bus Throttle */
459 #define I596_SCP_LINEAR 0x040000 /* Linear Mode */
460 #define I596_SCP_SEGMENTED 0x020000 /* Segmented Mode */
461 #define I596_SCP_82586 0x000000 /* 82586 Mode */
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