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1 /********************************************************
2 * Header file for eata_dma.c and eata_pio.c *
3 * Linux EATA SCSI drivers *
4 * (c) 1993-96 Michael Neuffer *
5 * mike@i-Connect.Net *
6 * neuffer@mail.uni-mainz.de *
7 *********************************************************
8 * last change: 95/05/05 *
9 ********************************************************/
10
11
12 #ifndef _EATA_GENERIC_H
13 #define _EATA_GENERIC_H
14
15
16
17 /*********************************************
18 * Misc. definitions *
19 *********************************************/
20
21 #ifndef TRUE
22 #define TRUE 1
23 #endif
24 #ifndef FALSE
25 #define FALSE 0
26 #endif
27
28 #define min(a,b) ((a<b)?(a):(b))
29
30 #define R_LIMIT 0x20000
31
32 #define MAXISA 4
33 #define MAXEISA 16
34 #define MAXPCI 16
35 #define MAXIRQ 16
36 #define MAXTARGET 16
37 #define MAXCHANNEL 3
38
39 #define IS_ISA 'I'
40 #define IS_EISA 'E'
41 #define IS_PCI 'P'
42
43 #define BROKEN_INQUIRY 1
44
45 #define BUSMASTER 0xff
46 #define PIO 0xfe
47
48 #define EATA_SIGNATURE 0x45415441 /* BIG ENDIAN coded "EATA" sig. */
49
50 #define DPT_ID1 0x12
51 #define DPT_ID2 0x14
52
53 #define ATT_ID1 0x06
54 #define ATT_ID2 0x94
55 #define ATT_ID3 0x0
56
57 #define NEC_ID1 0x38
58 #define NEC_ID2 0xa3
59 #define NEC_ID3 0x82
60
61
62 #define EATA_CP_SIZE 44
63
64 #define MAX_PCI_DEVICES 32 /* Maximum # Of Devices Per Bus */
65 #define MAX_METHOD_2 16 /* Max Devices For Method 2 */
66 #define MAX_PCI_BUS 16 /* Maximum # Of Busses Allowed */
67
68 #define SG_SIZE 64
69 #define SG_SIZE_BIG 252 /* max. 8096 elements, 64k */
70
71 #define TYPE_DISK_QUEUE 16
72 #define TYPE_TAPE_QUEUE 4
73 #define TYPE_ROM_QUEUE 4
74 #define TYPE_OTHER_QUEUE 2
75
76 #define FREE 0
77 #define OK 0
78 #define NO_TIMEOUT 0
79 #define USED 1
80 #define TIMEOUT 2
81 #define RESET 4
82 #define LOCKED 8
83 #define ABORTED 16
84
85 #define READ 0
86 #define WRITE 1
87 #define OTHER 2
88
89 #define HD(cmd) ((hostdata *)&(cmd->host->hostdata))
90 #define CD(cmd) ((struct eata_ccb *)(cmd->host_scribble))
91 #define SD(host) ((hostdata *)&(host->hostdata))
92
93 #define DELAY(x) { __u32 i; ulong flags; \
94 save_flags(flags); sti(); \
95 i = jiffies + (x * HZ); \
96 while (jiffies < i) barrier(); \
97 restore_flags(flags); }
98
99 /***********************************************
100 * EATA Command & Register definitions *
101 ***********************************************/
102 #define PCI_REG_DPTconfig 0x40
103 #define PCI_REG_PumpModeAddress 0x44
104 #define PCI_REG_PumpModeData 0x48
105 #define PCI_REG_ConfigParam1 0x50
106 #define PCI_REG_ConfigParam2 0x54
107
108
109 #define EATA_CMD_PIO_SETUPTEST 0xc6
110 #define EATA_CMD_PIO_READ_CONFIG 0xf0
111 #define EATA_CMD_PIO_SET_CONFIG 0xf1
112 #define EATA_CMD_PIO_SEND_CP 0xf2
113 #define EATA_CMD_PIO_RECEIVE_SP 0xf3
114 #define EATA_CMD_PIO_TRUNC 0xf4
115
116 #define EATA_CMD_RESET 0xf9
117 #define EATA_CMD_IMMEDIATE 0xfa
118
119 #define EATA_CMD_DMA_READ_CONFIG 0xfd
120 #define EATA_CMD_DMA_SET_CONFIG 0xfe
121 #define EATA_CMD_DMA_SEND_CP 0xff
122
123 #define ECS_EMULATE_SENSE 0xd4
124
125 #define EATA_GENERIC_ABORT 0x00
126 #define EATA_SPECIFIC_RESET 0x01
127 #define EATA_BUS_RESET 0x02
128 #define EATA_SPECIFIC_ABORT 0x03
129 #define EATA_QUIET_INTR 0x04
130 #define EATA_COLD_BOOT_HBA 0x06 /* Only as a last resort */
131 #define EATA_FORCE_IO 0x07
132
133
134 #define HA_WCOMMAND 0x07 /* command register offset */
135 #define HA_WIFC 0x06 /* immediate command offset */
136 #define HA_WCODE 0x05
137 #define HA_WCODE2 0x04
138 #define HA_WDMAADDR 0x02 /* DMA address LSB offset */
139 #define HA_RAUXSTAT 0x08 /* aux status register offset*/
140 #define HA_RSTATUS 0x07 /* status register offset */
141 #define HA_RDATA 0x00 /* data register (16bit) */
142 #define HA_WDATA 0x00 /* data register (16bit) */
143
144 #define HA_ABUSY 0x01 /* aux busy bit */
145 #define HA_AIRQ 0x02 /* aux IRQ pending bit */
146 #define HA_SERROR 0x01 /* pr. command ended in error*/
147 #define HA_SMORE 0x02 /* more data soon to come */
148 #define HA_SCORR 0x04 /* data corrected */
149 #define HA_SDRQ 0x08 /* data request active */
150 #define HA_SSC 0x10 /* seek complete */
151 #define HA_SFAULT 0x20 /* write fault */
152 #define HA_SREADY 0x40 /* drive ready */
153 #define HA_SBUSY 0x80 /* drive busy */
154 #define HA_SDRDY HA_SSC+HA_SREADY+HA_SDRQ
155
156 /**********************************************
157 * Message definitions *
158 **********************************************/
159
160 #define HA_NO_ERROR 0x00 /* No Error */
161 #define HA_ERR_SEL_TO 0x01 /* Selection Timeout */
162 #define HA_ERR_CMD_TO 0x02 /* Command Timeout */
163 #define HA_BUS_RESET 0x03 /* SCSI Bus Reset Received */
164 #define HA_INIT_POWERUP 0x04 /* Initial Controller Power-up */
165 #define HA_UNX_BUSPHASE 0x05 /* Unexpected Bus Phase */
166 #define HA_UNX_BUS_FREE 0x06 /* Unexpected Bus Free */
167 #define HA_BUS_PARITY 0x07 /* Bus Parity Error */
168 #define HA_SCSI_HUNG 0x08 /* SCSI Hung */
169 #define HA_UNX_MSGRJCT 0x09 /* Unexpected Message Rejected */
170 #define HA_RESET_STUCK 0x0a /* SCSI Bus Reset Stuck */
171 #define HA_RSENSE_FAIL 0x0b /* Auto Request-Sense Failed */
172 #define HA_PARITY_ERR 0x0c /* Controller Ram Parity Error */
173 #define HA_CP_ABORT_NA 0x0d /* Abort Message sent to non-active cmd */
174 #define HA_CP_ABORTED 0x0e /* Abort Message sent to active cmd */
175 #define HA_CP_RESET_NA 0x0f /* Reset Message sent to non-active cmd */
176 #define HA_CP_RESET 0x10 /* Reset Message sent to active cmd */
177 #define HA_ECC_ERR 0x11 /* Controller Ram ECC Error */
178 #define HA_PCI_PARITY 0x12 /* PCI Parity Error */
179 #define HA_PCI_MABORT 0x13 /* PCI Master Abort */
180 #define HA_PCI_TABORT 0x14 /* PCI Target Abort */
181 #define HA_PCI_STABORT 0x15 /* PCI Signaled Target Abort */
182
183 /**********************************************
184 * Other definitions *
185 **********************************************/
186
187 struct reg_bit { /* reading this one will clear the interrupt */
188 __u8 error:1; /* previous command ended in an error */
189 __u8 more:1; /* more DATA coming soon, poll BSY & DRQ (PIO) */
190 __u8 corr:1; /* data read was successfully corrected with ECC*/
191 __u8 drq:1; /* data request active */
192 __u8 sc:1; /* seek complete */
193 __u8 fault:1; /* write fault */
194 __u8 ready:1; /* drive ready */
195 __u8 busy:1; /* controller busy */
196 };
197
198 struct reg_abit { /* reading this won't clear the interrupt */
199 __u8 abusy:1; /* auxiliary busy */
200 __u8 irq:1; /* set when drive interrupt is asserted */
201 __u8 dummy:6;
202 };
203
204 struct eata_register { /* EATA register set */
205 __u8 data_reg[2]; /* R, couldn't figure this one out */
206 __u8 cp_addr[4]; /* W, CP address register */
207 union {
208 __u8 command; /* W, command code: [read|set] conf, send CP*/
209 struct reg_bit status; /* R, see register_bit1 */
210 __u8 statusbyte;
211 } ovr;
212 struct reg_abit aux_stat; /* R, see register_bit2 */
213 };
214
215 struct get_conf { /* Read Configuration Array */
216 __u32 len; /* Should return 0x22, 0x24, etc */
217 __u32 signature; /* Signature MUST be "EATA" */
218 __u8 version2:4,
219 version:4; /* EATA Version level */
220 __u8 OCS_enabled:1, /* Overlap Command Support enabled */
221 TAR_support:1, /* SCSI Target Mode supported */
222 TRNXFR:1, /* Truncate Transfer Cmd not necessary *
223 * Only used in PIO Mode */
224 MORE_support:1, /* MORE supported (only PIO Mode) */
225 DMA_support:1, /* DMA supported Driver uses only *
226 * this mode */
227 DMA_valid:1, /* DRQ value in Byte 30 is valid */
228 ATA:1, /* ATA device connected (not supported) */
229 HAA_valid:1; /* Hostadapter Address is valid */
230
231 __u16 cppadlen; /* Number of pad bytes send after CD data *
232 * set to zero for DMA commands */
233 __u8 scsi_id[4]; /* SCSI ID of controller 2-0 Byte 0 res. *
234 * if not, zero is returned */
235 __u32 cplen; /* CP length: number of valid cp bytes */
236 __u32 splen; /* Number of bytes returned after *
237 * Receive SP command */
238 __u16 queuesiz; /* max number of queueable CPs */
239 __u16 dummy;
240 __u16 SGsiz; /* max number of SG table entries */
241 __u8 IRQ:4, /* IRQ used this HA */
242 IRQ_TR:1, /* IRQ Trigger: 0=edge, 1=level */
243 SECOND:1, /* This is a secondary controller */
244 DMA_channel:2; /* DRQ index, DRQ is 2comp of DRQX */
245 __u8 sync; /* device at ID 7 tru 0 is running in *
246 * synchronous mode, this will disappear */
247 __u8 DSBLE:1, /* ISA i/o addressing is disabled */
248 FORCADR:1, /* i/o address has been forced */
249 SG_64K:1,
250 SG_UAE:1,
251 :4;
252 __u8 MAX_ID:5, /* Max number of SCSI target IDs */
253 MAX_CHAN:3; /* Number of SCSI busses on HBA */
254 __u8 MAX_LUN; /* Max number of LUNs */
255 __u8 :3,
256 AUTOTRM:1,
257 M1_inst:1,
258 ID_qest:1, /* Raidnum ID is questionable */
259 is_PCI:1, /* HBA is PCI */
260 is_EISA:1; /* HBA is EISA */
261 __u8 RAIDNUM; /* unique HBA identifier */
262 __u8 unused[474];
263 };
264
265 struct eata_sg_list
266 {
267 __u32 data;
268 __u32 len;
269 };
270
271 struct eata_ccb { /* Send Command Packet structure */
272
273 __u8 SCSI_Reset:1, /* Cause a SCSI Bus reset on the cmd */
274 HBA_Init:1, /* Cause Controller to reinitialize */
275 Auto_Req_Sen:1, /* Do Auto Request Sense on errors */
276 scatter:1, /* Data Ptr points to a SG Packet */
277 Resrvd:1, /* RFU */
278 Interpret:1, /* Interpret the SCSI cdb of own use */
279 DataOut:1, /* Data Out phase with command */
280 DataIn:1; /* Data In phase with command */
281 __u8 reqlen; /* Request Sense Length *
282 * Valid if Auto_Req_Sen=1 */
283 __u8 unused[3];
284 __u8 FWNEST:1, /* send cmd to phys RAID component */
285 unused2:7;
286 __u8 Phsunit:1, /* physical unit on mirrored pair */
287 I_AT:1, /* inhibit address translation */
288 I_HBA_C:1, /* HBA inhibit caching */
289 unused3:5;
290
291 __u8 cp_id:5, /* SCSI Device ID of target */
292 cp_channel:3; /* SCSI Channel # of HBA */
293 __u8 cp_lun:3,
294 :2,
295 cp_luntar:1, /* CP is for target ROUTINE */
296 cp_dispri:1, /* Grant disconnect privilege */
297 cp_identify:1; /* Always TRUE */
298 __u8 cp_msg1; /* Message bytes 0-3 */
299 __u8 cp_msg2;
300 __u8 cp_msg3;
301 __u8 cp_cdb[12]; /* Command Descriptor Block */
302 __u32 cp_datalen; /* Data Transfer Length *
303 * If scatter=1 len of sg package */
304 void *cp_viraddr; /* address of this ccb */
305 __u32 cp_dataDMA; /* Data Address, if scatter=1 *
306 * address of scatter packet */
307 __u32 cp_statDMA; /* address for Status Packet */
308 __u32 cp_reqDMA; /* Request Sense Address, used if *
309 * CP command ends with error */
310 /* Additional CP info begins here */
311 __u32 timestamp; /* Needed to measure command latency */
312 __u32 timeout;
313 __u8 sizeindex;
314 __u8 rw_latency;
315 __u8 retries;
316 __u8 status; /* status of this queueslot */
317 Scsi_Cmnd *cmd; /* address of cmd */
318 struct eata_sg_list *sg_list;
319 };
320
321
322 struct eata_sp {
323 __u8 hba_stat:7, /* HBA status */
324 EOC:1; /* True if command finished */
325 __u8 scsi_stat; /* Target SCSI status */
326 __u8 reserved[2];
327 __u32 residue_len; /* Number of bytes not transferred */
328 struct eata_ccb *ccb; /* Address set in COMMAND PACKET */
329 __u8 msg[12];
330 };
331
332 typedef struct hstd {
333 __u8 vendor[9];
334 __u8 name[18];
335 __u8 revision[6];
336 __u8 EATA_revision;
337 __u32 firmware_revision;
338 __u8 HBA_number;
339 __u8 bustype; /* bustype of HBA */
340 __u8 channel; /* # of avail. scsi channels */
341 __u8 state; /* state of HBA */
342 __u8 primary; /* true if primary */
343 __u8 more_support:1, /* HBA supports MORE flag */
344 immediate_support:1, /* HBA supports IMMEDIATE CMDs*/
345 broken_INQUIRY:1; /* This is an EISA HBA with *
346 * broken INQUIRY */
347 __u8 do_latency; /* Latency measurement flag */
348 __u32 reads[13];
349 __u32 writes[13];
350 __u32 reads_lat[12][4];
351 __u32 writes_lat[12][4];
352 __u32 all_lat[4];
353 /* state of Target (RESET,..) */
354 __u8 t_state[MAXCHANNEL][MAXTARGET];
355 /* timeouts on target */
356 __u32 t_timeout[MAXCHANNEL][MAXTARGET];
357 __u8 resetlevel[MAXCHANNEL];
358 __u32 last_ccb; /* Last used ccb */
359 __u32 cplen; /* size of CP in words */
360 __u16 cppadlen; /* pad length of cp in words */
361 __u16 queuesize;
362 __u16 sgsize; /* # of entries in the SG list*/
363 __u16 devflags; /* bits set for detected devices */
364 __u8 hostid; /* SCSI ID of HBA */
365 __u8 moresupport; /* HBA supports MORE flag */
366 struct Scsi_Host *next;
367 struct Scsi_Host *prev;
368 struct eata_sp sp; /* status packet */
369 struct eata_ccb ccb[0]; /* ccb array begins here */
370 }hostdata;
371
372 /* structure for max. 2 emulated drives */
373 struct drive_geom_emul {
374 __u8 trans; /* translation flag 1=transl */
375 __u8 channel; /* SCSI channel number */
376 __u8 HBA; /* HBA number (prim/sec) */
377 __u8 id; /* drive id */
378 __u8 lun; /* drive lun */
379 __u32 heads; /* number of heads */
380 __u32 sectors; /* number of sectors */
381 __u32 cylinder; /* number of cylinders */
382 };
383
384 struct geom_emul {
385 __u8 bios_drives; /* number of emulated drives */
386 struct drive_geom_emul drv[2]; /* drive structures */
387 };
388
389 #endif /* _EATA_GENERIC_H */
390
391 /*
392 * Overrides for Emacs so that we almost follow Linus's tabbing style.
393 * Emacs will notice this stuff at the end of the file and automatically
394 * adjust the settings for this buffer only. This must remain at the end
395 * of the file.
396 * ---------------------------------------------------------------------------
397 * Local variables:
398 * c-indent-level: 4
399 * c-brace-imaginary-offset: 0
400 * c-brace-offset: -4
401 * c-argdecl-indent: 4
402 * c-label-offset: -4
403 * c-continued-statement-offset: 4
404 * c-continued-brace-offset: 0
405 * tab-width: 8
406 * End:
407 */
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