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1 /* AM53/79C974 (PCscsi) driver release 0.5
2 *
3 * The architecture and much of the code of this device
4 * driver was originally developed by Drew Eckhardt for
5 * the NCR5380. The following copyrights apply:
6 * For the architecture and all parts similar to the NCR5380:
7 * Copyright 1993, Drew Eckhardt
8 * Visionary Computing
9 * (Unix and Linux consulting and custom programming)
10 * drew@colorado.edu
11 * +1 (303) 666-5836
12 *
13 * The AM53C974_nobios_detect code was originally developed by
14 * Robin Cutshaw (robin@xfree86.org) and is used here in a
15 * modified form.
16 *
17 * For the other parts:
18 * Copyright 1994, D. Frieauff
19 * EMail: fri@rsx42sun0.dofn.de
20 * Phone: x49-7545-8-2256 , x49-7541-42305
21 */
22
23 /*
24 * $Log: AM53C974.h,v $
25 */
26
27 #ifndef AM53C974_H
28 #define AM53C974_H
29
30 #include <scsi/scsicam.h>
31
32 /***************************************************************************************
33 * Default setting of the controller's SCSI id. Edit and uncomment this only if your *
34 * BIOS does not correctly initialize the controller's SCSI id. *
35 * If you don't get a warning during boot, it is correctly initialized. *
36 ****************************************************************************************/
37 /* #define AM53C974_SCSI_ID 7 */
38
39 /***************************************************************************************
40 * Default settings for sync. negotiation enable, transfer rate and sync. offset. *
41 * These settings can be replaced by LILO overrides (append) with the following syntax: *
42 * AM53C974=host-scsi-id, target-scsi-id, max-rate, max-offset *
43 * Sync. negotiation is disabled by default and will be enabled for those targets which *
44 * are specified in the LILO override *
45 ****************************************************************************************/
46 #define DEFAULT_SYNC_NEGOTIATION_ENABLED 0 /* 0 or 1 */
47 #define DEFAULT_RATE 5 /* MHz, min: 3; max: 10 */
48 #define DEFAULT_SYNC_OFFSET 0 /* bytes, min: 0; max: 15; use 0 for async. mode */
49
50
51 /* --------------------- don't edit below here --------------------- */
52
53 #define AM53C974_DRIVER_REVISION_MAJOR 0
54 #define AM53C974_DRIVER_REVISION_MINOR 5
55 #define SEPARATOR_LINE \
56 "--------------------------------------------------------------------------\n"
57
58 /* debug control */
59 /* #define AM53C974_DEBUG */
60 /* #define AM53C974_DEBUG_MSG */
61 /* #define AM53C974_DEBUG_KEYWAIT */
62 /* #define AM53C974_DEBUG_INIT */
63 /* #define AM53C974_DEBUG_QUEUE */
64 /* #define AM53C974_DEBUG_INFO */
65 /* #define AM53C974_DEBUG_LINKED */
66 /* #define VERBOSE_AM53C974_DEBUG */
67 /* #define AM53C974_DEBUG_INTR */
68 /* #define AM53C974_DEB_RESEL */
69 #define AM53C974_DEBUG_ABORT
70 /* #define AM53C974_OPTION_DEBUG_PROBE_ONLY */
71
72 /* special options/constants */
73 #define DEF_CLK 40 /* chip clock freq. in MHz */
74 #define MIN_PERIOD 4 /* for negotiation: min. number of clocks per cycle */
75 #define MAX_PERIOD 13 /* for negotiation: max. number of clocks per cycle */
76 #define MAX_OFFSET 15 /* for negotiation: max. offset (0=async) */
77
78 #define DEF_SCSI_TIMEOUT 245 /* STIMREG value, 40 Mhz */
79 #define DEF_STP 8 /* STPREG value assuming 5.0 MB/sec, FASTCLK, FASTSCSI */
80 #define DEF_SOF_RAD 0 /* REQ/ACK deassertion delay */
81 #define DEF_SOF_RAA 0 /* REQ/ACK assertion delay */
82 #define DEF_ETM 0 /* CNTLREG1, ext. timing mode */
83 #define DEF_PERE 1 /* CNTLREG1, parity error reporting */
84 #define DEF_CLKF 0 /* CLKFREG, 0=40 Mhz */
85 #define DEF_ENF 1 /* CNTLREG2, enable features */
86 #define DEF_ADIDCHK 0 /* CNTLREG3, additional ID check */
87 #define DEF_FASTSCSI 1 /* CNTLREG3, fast SCSI */
88 #define DEF_FASTCLK 1 /* CNTLREG3, fast clocking, 5 MB/sec at 40MHz chip clk */
89 #define DEF_GLITCH 1 /* CNTLREG4, glitch eater, 0=12ns, 1=35ns, 2=25ns, 3=off */
90 #define DEF_PWD 0 /* CNTLREG4, reduced power feature */
91 #define DEF_RAE 0 /* CNTLREG4, RAE active negation on REQ, ACK only */
92 #define DEF_RADE 1 /* 1CNTLREG4, active negation on REQ, ACK and data */
93
94 /*** PCI block ***/
95 /* standard registers are defined in <linux/pci.h> */
96 #ifndef PCI_VENDOR_ID_AMD
97 #define PCI_VENDOR_ID_AMD 0x1022
98 #define PCI_DEVICE_ID_AMD_SCSI 0x2020
99 #endif
100 #define PCI_BASE_MASK 0xFFFFFFE0
101 #define PCI_COMMAND_PERREN 0x40
102 #define PCI_SCRATCH_REG_0 0x40 /* 16 bits */
103 #define PCI_SCRATCH_REG_1 0x42 /* 16 bits */
104 #define PCI_SCRATCH_REG_2 0x44 /* 16 bits */
105 #define PCI_SCRATCH_REG_3 0x46 /* 16 bits */
106 #define PCI_SCRATCH_REG_4 0x48 /* 16 bits */
107 #define PCI_SCRATCH_REG_5 0x4A /* 16 bits */
108 #define PCI_SCRATCH_REG_6 0x4C /* 16 bits */
109 #define PCI_SCRATCH_REG_7 0x4E /* 16 bits */
110
111 /*** SCSI block ***/
112 #define CTCLREG 0x00 /* r current transf. count, low byte */
113 #define CTCMREG 0x04 /* r current transf. count, middle byte */
114 #define CTCHREG 0x38 /* r current transf. count, high byte */
115 #define STCLREG 0x00 /* w start transf. count, low byte */
116 #define STCMREG 0x04 /* w start transf. count, middle byte */
117 #define STCHREG 0x38 /* w start transf. count, high byte */
118 #define FFREG 0x08 /* rw SCSI FIFO reg. */
119 #define STIMREG 0x14 /* w SCSI timeout reg. */
120
121 #define SDIDREG 0x10 /* w SCSI destination ID reg. */
122 #define SDIREG_MASK 0x07 /* mask */
123
124 #define STPREG 0x18 /* w synchronous transf. period reg. */
125 #define STPREG_STP 0x1F /* synchr. transfer period */
126
127 #define CLKFREG 0x24 /* w clock factor reg. */
128 #define CLKFREG_MASK 0x07 /* mask */
129
130 #define CMDREG 0x0C /* rw SCSI command reg. */
131 #define CMDREG_DMA 0x80 /* set DMA mode (set together with opcodes below) */
132 #define CMDREG_IT 0x10 /* information transfer */
133 #define CMDREG_ICCS 0x11 /* initiator command complete steps */
134 #define CMDREG_MA 0x12 /* message accepted */
135 #define CMDREG_TPB 0x98 /* transfer pad bytes, DMA mode only */
136 #define CMDREG_SATN 0x1A /* set ATN */
137 #define CMDREG_RATN 0x1B /* reset ATN */
138 #define CMDREG_SOAS 0x41 /* select without ATN steps */
139 #define CMDREG_SAS 0x42 /* select with ATN steps (1 msg byte) */
140 #define CMDREG_SASS 0x43 /* select with ATN and stop steps */
141 #define CMDREG_ESR 0x44 /* enable selection/reselection */
142 #define CMDREG_DSR 0x45 /* disable selection/reselection */
143 #define CMDREG_SA3S 0x46 /* select with ATN 3 steps (3 msg bytes) */
144 #define CMDREG_NOP 0x00 /* no operation */
145 #define CMDREG_CFIFO 0x01 /* clear FIFO */
146 #define CMDREG_RDEV 0x02 /* reset device */
147 #define CMDREG_RBUS 0x03 /* reset SCSI bus */
148
149 #define STATREG 0x10 /* r SCSI status reg. */
150 #define STATREG_INT 0x80 /* SCSI interrupt condition detected */
151 #define STATREG_IOE 0x40 /* SCSI illegal operation error detected */
152 #define STATREG_PE 0x20 /* SCSI parity error detected */
153 #define STATREG_CTZ 0x10 /* CTC reg decremented to zero */
154 #define STATREG_MSG 0x04 /* SCSI MSG phase (latched?) */
155 #define STATREG_CD 0x02 /* SCSI C/D phase (latched?) */
156 #define STATREG_IO 0x01 /* SCSI I/O phase (latched?) */
157 #define STATREG_PHASE 0x07 /* SCSI phase mask */
158
159 #define INSTREG 0x14 /* r interrupt status reg. */
160 #define INSTREG_SRST 0x80 /* SCSI reset detected */
161 #define INSTREG_ICMD 0x40 /* SCSI invalid command detected */
162 #define INSTREG_DIS 0x20 /* target disconnected or sel/resel timeout*/
163 #define INSTREG_SR 0x10 /* device on bus has service request */
164 #define INSTREG_SO 0x08 /* successful operation */
165 #define INSTREG_RESEL 0x04 /* device reselected as initiator */
166
167 #define ISREG 0x18 /* r internal state reg. */
168 #define ISREG_SOF 0x08 /* synchronous offset flag (act. low) */
169 #define ISREG_IS 0x07 /* status of intermediate op. */
170 #define ISREG_OK_NO_STOP 0x04 /* selection successful */
171 #define ISREG_OK_STOP 0x01 /* selection successful */
172
173 #define CFIREG 0x1C /* r current FIFO/internal state reg. */
174 #define CFIREG_IS 0xE0 /* status of intermediate op. */
175 #define CFIREG_CF 0x1F /* number of bytes in SCSI FIFO */
176
177 #define SOFREG 0x1C /* w synchr. offset reg. */
178 #define SOFREG_RAD 0xC0 /* REQ/ACK deassertion delay (sync.) */
179 #define SOFREG_RAA 0x30 /* REQ/ACK assertion delay (sync.) */
180 #define SOFREG_SO 0x0F /* synch. offset (sync.) */
181
182 #define CNTLREG1 0x20 /* rw control register one */
183 #define CNTLREG1_ETM 0x80 /* set extended timing mode */
184 #define CNTLREG1_DISR 0x40 /* disable interrupt on SCSI reset */
185 #define CNTLREG1_PERE 0x10 /* enable parity error reporting */
186 #define CNTLREG1_SID 0x07 /* host adapter SCSI ID */
187
188 #define CNTLREG2 0x2C /* rw control register two */
189 #define CNTLREG2_ENF 0x40 /* enable features */
190
191 #define CNTLREG3 0x30 /* rw control register three */
192 #define CNTLREG3_ADIDCHK 0x80 /* additional ID check */
193 #define CNTLREG3_FASTSCSI 0x10 /* fast SCSI */
194 #define CNTLREG3_FASTCLK 0x08 /* fast SCSI clocking */
195
196 #define CNTLREG4 0x34 /* rw control register four */
197 #define CNTLREG4_GLITCH 0xC0 /* glitch eater */
198 #define CNTLREG4_PWD 0x20 /* reduced power feature */
199 #define CNTLREG4_RAE 0x08 /* write only, active negot. ctrl. */
200 #define CNTLREG4_RADE 0x04 /* active negot. ctrl. */
201 #define CNTLREG4_RES 0x10 /* reserved bit, must be 1 */
202
203 /*** DMA block ***/
204 #define DMACMD 0x40 /* rw command */
205 #define DMACMD_DIR 0x80 /* transfer direction (1=read from device) */
206 #define DMACMD_INTE_D 0x40 /* DMA transfer interrupt enable */
207 #define DMACMD_INTE_P 0x20 /* page transfer interrupt enable */
208 #define DMACMD_MDL 0x10 /* map to memory descriptor list */
209 #define DMACMD_DIAG 0x04 /* diagnostics, set to 0 */
210 #define DMACMD_IDLE 0x00 /* idle cmd */
211 #define DMACMD_BLAST 0x01 /* flush FIFO to memory */
212 #define DMACMD_ABORT 0x02 /* terminate DMA */
213 #define DMACMD_START 0x03 /* start DMA */
214
215 #define DMASTATUS 0x54 /* r status register */
216 #define DMASTATUS_BCMPLT 0x20 /* BLAST complete */
217 #define DMASTATUS_SCSIINT 0x10 /* SCSI interrupt pending */
218 #define DMASTATUS_DONE 0x08 /* DMA transfer terminated */
219 #define DMASTATUS_ABORT 0x04 /* DMA transfer aborted */
220 #define DMASTATUS_ERROR 0x02 /* DMA transfer error */
221 #define DMASTATUS_PWDN 0x02 /* power down indicator */
222
223 #define DMASTC 0x44 /* rw starting transfer count */
224 #define DMASPA 0x48 /* rw starting physical address */
225 #define DMAWBC 0x4C /* r working byte counter */
226 #define DMAWAC 0x50 /* r working address counter */
227 #define DMASMDLA 0x58 /* rw starting MDL address */
228 #define DMAWMAC 0x5C /* r working MDL counter */
229
230 /*** SCSI phases ***/
231 #define PHASE_MSGIN 0x07
232 #define PHASE_MSGOUT 0x06
233 #define PHASE_RES_1 0x05
234 #define PHASE_RES_0 0x04
235 #define PHASE_STATIN 0x03
236 #define PHASE_CMDOUT 0x02
237 #define PHASE_DATAIN 0x01
238 #define PHASE_DATAOUT 0x00
239
240 struct AM53C974_hostdata {
241 volatile unsigned in_reset:1; /* flag, says bus reset pending */
242 volatile unsigned aborted:1; /* flag, says aborted */
243 volatile unsigned selecting:1; /* selection started, but not yet finished */
244 volatile unsigned disconnecting: 1; /* disconnection started, but not yet finished */
245 volatile unsigned dma_busy:1; /* dma busy when service request for info transfer received */
246 volatile unsigned char msgout[10]; /* message to output in MSGOUT_PHASE */
247 volatile unsigned char last_message[10]; /* last message OUT */
248 volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
249 volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
250 volatile Scsi_Cmnd *sel_cmd; /* command for selection */
251 volatile Scsi_Cmnd *connected; /* currently connected command */
252 volatile unsigned char busy[8]; /* index = target, bit = lun */
253 unsigned char sync_per[8]; /* synchronous transfer period (in effect) */
254 unsigned char sync_off[8]; /* synchronous offset (in effect) */
255 unsigned char sync_neg[8]; /* sync. negotiation performed (in effect) */
256 unsigned char sync_en[8]; /* sync. negotiation performed (in effect) */
257 unsigned char max_rate[8]; /* max. transfer rate (setup) */
258 unsigned char max_offset[8]; /* max. sync. offset (setup), only valid if corresponding sync_en is nonzero */
259 };
260
261 #define AM53C974 { \
262 NULL, /* pointer to next in list */ \
263 NULL, /* long * usage_count */ \
264 NULL, /* struct proc_dir_entry *proc_dir */ \
265 NULL, /* int (*proc_info)(char *, char **, off_t, int, int, int); */ \
266 "AM53C974", /* name */ \
267 AM53C974_detect, /* int (* detect)(struct SHT *) */ \
268 NULL, /* int (*release)(struct Scsi_Host *) */ \
269 AM53C974_info, /* const char *(* info)(struct Scsi_Host *) */ \
270 AM53C974_command, /* int (* command)(Scsi_Cmnd *) */ \
271 AM53C974_queue_command, /* int (* queuecommand)(Scsi_Cmnd *, \
272 void (*done)(Scsi_Cmnd *)) */ \
273 AM53C974_abort, /* int (* abort)(Scsi_Cmnd *) */ \
274 AM53C974_reset, /* int (* reset)(Scsi_Cmnd *) */ \
275 NULL, /* int (* slave_attach)(int, int) */ \
276 scsicam_bios_param, /* int (* bios_param)(Disk *, int, int[]) */ \
277 12, /* can_queue */ \
278 -1, /* this_id */ \
279 SG_ALL, /* sg_tablesize */ \
280 1, /* cmd_per_lun */ \
281 0, /* present, i.e. how many adapters of this kind */ \
282 0, /* unchecked_isa_dma */ \
283 DISABLE_CLUSTERING /* use_clustering */ \
284 }
285
286 void AM53C974_setup(char *str, int *ints);
287 int AM53C974_detect(Scsi_Host_Template *tpnt);
288 int AM53C974_biosparm(Disk *disk, int dev, int *info_array);
289 const char *AM53C974_info(struct Scsi_Host *);
290 int AM53C974_command(Scsi_Cmnd *SCpnt);
291 int AM53C974_queue_command(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
292 int AM53C974_abort(Scsi_Cmnd *cmd);
293 int AM53C974_reset (Scsi_Cmnd *cmd);
294
295 #define AM53C974_local_declare() unsigned long io_port
296 #define AM53C974_setio(instance) io_port = instance->io_port
297 #define AM53C974_read_8(addr) inb(io_port + (addr))
298 #define AM53C974_write_8(addr,x) outb((x), io_port + (addr))
299 #define AM53C974_read_16(addr) inw(io_port + (addr))
300 #define AM53C974_write_16(addr,x) outw((x), io_port + (addr))
301 #define AM53C974_read_32(addr) inl(io_port + (addr))
302 #define AM53C974_write_32(addr,x) outl((x), io_port + (addr))
303
304 #define AM53C974_poll_int() { do { statreg = AM53C974_read_8(STATREG); } \
305 while (!(statreg & STATREG_INT)) ; \
306 AM53C974_read_8(INSTREG) ; } /* clear int */
307 #define AM53C974_cfifo() (AM53C974_read_8(CFIREG) & CFIREG_CF)
308
309 /* These are "special" values for the tag parameter passed to AM53C974_select. */
310 #define TAG_NEXT -1 /* Use next free tag */
311 #define TAG_NONE -2 /* Establish I_T_L nexus instead of I_T_L_Q
312 * even on SCSI-II devices */
313
314 /************ LILO overrides *************/
315 typedef struct _override_t {
316 int host_scsi_id; /* SCSI id of the bus controller */
317 int target_scsi_id; /* SCSI id of target */
318 int max_rate; /* max. transfer rate */
319 int max_offset; /* max. sync. offset, 0 = asynchronous */
320 } override_t;
321
322 /************ PCI stuff *************/
323 #define AM53C974_PCIREG_OPEN() outb(0xF1, 0xCF8); outb(0, 0xCFA)
324 #define AM53C974_PCIREG_CLOSE() outb(0, 0xCF8)
325 #define AM53C974_PCIREG_READ_BYTE(instance,a) ( inb((a) + (instance)->io_port) )
326 #define AM53C974_PCIREG_READ_WORD(instance,a) ( inw((a) + (instance)->io_port) )
327 #define AM53C974_PCIREG_READ_DWORD(instance,a) ( inl((a) + (instance)->io_port) )
328 #define AM53C974_PCIREG_WRITE_BYTE(instance,x,a) ( outb((x), (a) + (instance)->io_port) )
329 #define AM53C974_PCIREG_WRITE_WORD(instance,x,a) ( outw((x), (a) + (instance)->io_port) )
330 #define AM53C974_PCIREG_WRITE_DWORD(instance,x,a) ( outl((x), (a) + (instance)->io_port) )
331
332 typedef struct _pci_config_t {
333 /* start of official PCI config space header */
334 union {
335 unsigned int device_vendor;
336 struct {
337 unsigned short vendor;
338 unsigned short device;
339 } dv;
340 } dv_id;
341 #define _device_vendor dv_id.device_vendor
342 #define _vendor dv_id.dv.vendor
343 #define _device dv_id.dv.device
344 union {
345 unsigned int status_command;
346 struct {
347 unsigned short command;
348 unsigned short status;
349 } sc;
350 } stat_cmd;
351 #define _status_command stat_cmd.status_command
352 #define _command stat_cmd.sc.command
353 #define _status stat_cmd.sc.status
354 union {
355 unsigned int class_revision;
356 struct {
357 unsigned char rev_id;
358 unsigned char prog_if;
359 unsigned char sub_class;
360 unsigned char base_class;
361 } cr;
362 } class_rev;
363 #define _class_revision class_rev.class_revision
364 #define _rev_id class_rev.cr.rev_id
365 #define _prog_if class_rev.cr.prog_if
366 #define _sub_class class_rev.cr.sub_class
367 #define _base_class class_rev.cr.base_class
368 union {
369 unsigned int bist_header_latency_cache;
370 struct {
371 unsigned char cache_line_size;
372 unsigned char latency_timer;
373 unsigned char header_type;
374 unsigned char bist;
375 } bhlc;
376 } bhlc;
377 #define _bist_header_latency_cache bhlc.bist_header_latency_cache
378 #define _cache_line_size bhlc.bhlc.cache_line_size
379 #define _latency_timer bhlc.bhlc.latency_timer
380 #define _header_type bhlc.bhlc.header_type
381 #define _bist bhlc.bhlc.bist
382 unsigned int _base0;
383 unsigned int _base1;
384 unsigned int _base2;
385 unsigned int _base3;
386 unsigned int _base4;
387 unsigned int _base5;
388 unsigned int rsvd1;
389 unsigned int rsvd2;
390 unsigned int _baserom;
391 unsigned int rsvd3;
392 unsigned int rsvd4;
393 union {
394 unsigned int max_min_ipin_iline;
395 struct {
396 unsigned char int_line;
397 unsigned char int_pin;
398 unsigned char min_gnt;
399 unsigned char max_lat;
400 } mmii;
401 } mmii;
402 #define _max_min_ipin_iline mmii.max_min_ipin_iline
403 #define _int_line mmii.mmii.int_line
404 #define _int_pin mmii.mmii.int_pin
405 #define _min_gnt mmii.mmii.min_gnt
406 #define _max_lat mmii.mmii.max_lat
407 /* end of official PCI config space header */
408 unsigned short _ioaddr; /* config type 1 - private I/O addr */
409 unsigned int _pcibus; /* config type 2 - private bus id */
410 unsigned int _cardnum; /* config type 2 - private card number */
411 } pci_config_t;
412
413 #endif /* AM53C974_H */
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