This source file includes following definitions.
- readisac_0
- readisac_3
- writeisac_0
- writeisac_3
- readisac_s
- writeisac_s
- readhscx_0
- readhscx_3
- writehscx_0
- writehscx_3
- readhscx_s
- writehscx_s
- waitforCEC_0
- waitforCEC_3
- waitforXFW_0
- waitforXFW_3
- writehscxCMDR_0
- writehscxCMDR_3
- teles_hscxreport
- teles_report
- hscx_sched_event
- hscx_empty_fifo
- hscx_fill_fifo
- hscx_interrupt
- isac_sched_event
- empty_fifo
- fill_fifo
- act_wanted
- ph_command
- isac_new_ph
- teles_interrupt
- act_ivated
- process_new_ph
- process_xmt
- process_rcv
- isac_bh
- hscx_process_xmt
- hscx_process_rcv
- hscx_bh
- restart_ph
- initisac
- checkcard
- modehscx
- teles_addlist
- teles_rmlist
- teles_l2l1
- check_ph_act
- teles_manl1
- teles_l2l1discardq
- setstack_teles
- init_hscxstate
- initcard
- get_irq
- release_irq
- close_hscxstate
- closecard
- teles_shiftcards
- teles_inithardware
- teles_closehardware
- hscx_l2l1
- hscx_l2l1discardq
- open_hscxstate
- hscx_manl1
- setstack_hscx
- teles_reportcard
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16 #define __NO_VERSION__
17 #include "teles.h"
18
19 #define INCLUDE_INLINE_FUNCS
20 #include <linux/tqueue.h>
21 #include <linux/interrupt.h>
22
23 #undef DCHAN_VERBOSE
24
25 extern void tei_handler(struct PStack *st, byte pr,
26 struct BufHeader *ibh);
27 extern struct IsdnCard cards[];
28 extern int nrcards;
29
30 #define byteout(addr,val) outb_p(val,addr)
31 #define bytein(addr) inb_p(addr)
32
33 static inline byte
34 readisac_0(byte * cardm, byte offset)
35 {
36 return *(byte *) (cardm + 0x100 + ((offset & 1) ? 0x1ff : 0) + offset);
37 }
38
39 static inline byte
40 readisac_3(int iobase, byte offset)
41 {
42 return (bytein(iobase - 0x420 + offset));
43 }
44
45 #define READISAC(mbase,ibase,ofs) \
46 ((mbase)?readisac_0(mbase,ofs):readisac_3(ibase,ofs))
47
48 static inline void
49 writeisac_0(byte * cardm, byte offset, byte value)
50 {
51 *(byte *) (cardm + 0x100 + ((offset & 1) ? 0x1ff : 0) + offset) = value;
52 }
53
54 static inline void
55 writeisac_3(int iobase, byte offset, byte value)
56 {
57 byteout(iobase - 0x420 + offset, value);
58 }
59
60 #define WRITEISAC(mbase,ibase,ofs,val) \
61 ((mbase)?writeisac_0(mbase,ofs,val):writeisac_3(ibase,ofs,val))
62
63 static inline void
64 readisac_s(int iobase, byte offset, byte * dest, int count)
65 {
66 insb(iobase - 0x420 + offset, dest, count);
67 }
68
69 static inline void
70 writeisac_s(int iobase, byte offset, byte * src, int count)
71 {
72 outsb(iobase - 0x420 + offset, src, count);
73 }
74
75 static inline byte
76 readhscx_0(byte * base, byte hscx, byte offset)
77 {
78 return *(byte *) (base + 0x180 + ((offset & 1) ? 0x1FF : 0) +
79 ((hscx & 1) ? 0x40 : 0) + offset);
80 }
81
82 static inline byte
83 readhscx_3(int iobase, byte hscx, byte offset)
84 {
85 return (bytein(iobase - (hscx ? 0x820 : 0xc20) + offset));
86 }
87
88 #define READHSCX(mbase,ibase,hscx,ofs) \
89 ((mbase)?readhscx_0(mbase,hscx,ofs):readhscx_3(ibase,hscx,ofs))
90
91 static inline void
92 writehscx_0(byte * base, byte hscx, byte offset, byte data)
93 {
94 *(byte *) (base + 0x180 + ((offset & 1) ? 0x1FF : 0) +
95 ((hscx & 1) ? 0x40 : 0) + offset) = data;
96 }
97
98 static inline void
99 writehscx_3(int iobase, byte hscx, byte offset, byte data)
100 {
101 byteout(iobase - (hscx ? 0x820 : 0xc20) + offset, data);
102 }
103
104 static inline void
105 readhscx_s(int iobase, byte hscx, byte offset, byte * dest, int count)
106 {
107 insb(iobase - (hscx ? 0x820 : 0xc20) + offset, dest, count);
108 }
109
110 static inline void
111 writehscx_s(int iobase, byte hscx, byte offset, byte * src, int count)
112 {
113 outsb(iobase - (hscx ? 0x820 : 0xc20) + offset, src, count);
114 }
115
116 #define ISAC_MASK 0x20
117 #define ISAC_ISTA 0x20
118 #define ISAC_STAR 0x21
119 #define ISAC_CMDR 0x21
120 #define ISAC_EXIR 0x24
121
122 #define ISAC_RBCH 0x2a
123
124 #define ISAC_ADF2 0x39
125 #define ISAC_SPCR 0x30
126 #define ISAC_ADF1 0x38
127 #define ISAC_CIX0 0x31
128 #define ISAC_STCR 0x37
129 #define ISAC_MODE 0x22
130 #define ISAC_RSTA 0x27
131 #define ISAC_RBCL 0x25
132 #define ISAC_TIMR 0x23
133 #define ISAC_SQXR 0x3b
134
135 #define HSCX_ISTA 0x20
136 #define HSCX_CCR1 0x2f
137 #define HSCX_CCR2 0x2c
138 #define HSCX_TSAR 0x31
139 #define HSCX_TSAX 0x30
140 #define HSCX_XCCR 0x32
141 #define HSCX_RCCR 0x33
142 #define HSCX_MODE 0x22
143 #define HSCX_CMDR 0x21
144 #define HSCX_EXIR 0x24
145 #define HSCX_XAD1 0x24
146 #define HSCX_XAD2 0x25
147 #define HSCX_RAH2 0x27
148 #define HSCX_RSTA 0x27
149 #define HSCX_TIMR 0x23
150 #define HSCX_STAR 0x21
151 #define HSCX_RBCL 0x25
152 #define HSCX_XBCH 0x2d
153 #define HSCX_VSTR 0x2e
154 #define HSCX_RLCR 0x2e
155 #define HSCX_MASK 0x20
156
157 static inline void
158 waitforCEC_0(byte * base, byte hscx)
159 {
160 long to = 10;
161
162 while ((readhscx_0(base, hscx, HSCX_STAR) & 0x04) && to) {
163 udelay(5);
164 to--;
165 }
166 if (!to)
167 printk(KERN_WARNING "waitforCEC timeout\n");
168 }
169
170 static inline void
171 waitforCEC_3(int iobase, byte hscx)
172 {
173 long to = 10;
174
175 while ((readhscx_3(iobase, hscx, HSCX_STAR) & 0x04) && to) {
176 udelay(5);
177 to--;
178 }
179 if (!to)
180 printk(KERN_WARNING "waitforCEC timeout\n");
181 }
182
183 static inline void
184 waitforXFW_0(byte * base, byte hscx)
185 {
186 long to = 10;
187
188 waitforCEC_0(base, hscx);
189
190 while ((!(readhscx_0(base, hscx, HSCX_STAR) & 0x40)) && to) {
191 udelay(5);
192 to--;
193 }
194 if (!to)
195 printk(KERN_WARNING "waitforXFW timeout\n");
196 }
197
198 static inline void
199 waitforXFW_3(int iobase, byte hscx)
200 {
201 long to = 10;
202
203 waitforCEC_3(iobase, hscx);
204
205 while ((!(readhscx_3(iobase, hscx, HSCX_STAR) & 0x40)) && to) {
206 udelay(5);
207 to--;
208 }
209 if (!to)
210 printk(KERN_WARNING "waitforXFW timeout\n");
211 }
212
213 static inline void
214 writehscxCMDR_0(byte * base, byte hscx, byte data)
215 {
216 long flags;
217
218 save_flags(flags);
219 cli();
220 waitforCEC_0(base, hscx);
221 writehscx_0(base, hscx, HSCX_CMDR, data);
222 restore_flags(flags);
223 }
224
225 static inline void
226 writehscxCMDR_3(int iobase, byte hscx, byte data)
227 {
228 long flags;
229
230 save_flags(flags);
231 cli();
232 waitforCEC_3(iobase, hscx);
233 writehscx_3(iobase, hscx, HSCX_CMDR, data);
234 restore_flags(flags);
235 }
236
237 #define WRITEHSCX_CMDR(mbase,ibase,hscx,data) \
238 ((mbase)?writehscxCMDR_0(mbase,hscx,data):writehscxCMDR_3(ibase,hscx,data))
239
240
241
242
243
244 #define ISAC_RCVBUFREADY 0
245 #define ISAC_XMTBUFREADY 1
246 #define ISAC_PHCHANGE 2
247
248 #define HSCX_RCVBUFREADY 0
249 #define HSCX_XMTBUFREADY 1
250
251 void
252 teles_hscxreport(struct IsdnCardState *sp, int hscx)
253 {
254 printk(KERN_DEBUG "HSCX %d\n", hscx);
255 if (sp->membase) {
256 printk(KERN_DEBUG " ISTA %x\n", readhscx_0(sp->membase,
257 hscx, HSCX_ISTA));
258 printk(KERN_DEBUG " STAR %x\n", readhscx_0(sp->membase,
259 hscx, HSCX_STAR));
260 printk(KERN_DEBUG " EXIR %x\n", readhscx_0(sp->membase,
261 hscx, HSCX_EXIR));
262 } else {
263 printk(KERN_DEBUG " ISTA %x\n", readhscx_3(sp->iobase,
264 hscx, HSCX_ISTA));
265 printk(KERN_DEBUG " STAR %x\n", readhscx_3(sp->iobase,
266 hscx, HSCX_STAR));
267 printk(KERN_DEBUG " EXIR %x\n", readhscx_3(sp->iobase,
268 hscx, HSCX_EXIR));
269 }
270 }
271
272 void
273 teles_report(struct IsdnCardState *sp)
274 {
275 printk(KERN_DEBUG "ISAC\n");
276 if (sp->membase) {
277 printk(KERN_DEBUG " ISTA %x\n", readisac_0(sp->membase,
278 ISAC_ISTA));
279 printk(KERN_DEBUG " STAR %x\n", readisac_0(sp->membase,
280 ISAC_STAR));
281 printk(KERN_DEBUG " EXIR %x\n", readisac_0(sp->membase,
282 ISAC_EXIR));
283 } else {
284 printk(KERN_DEBUG " ISTA %x\n", readisac_3(sp->iobase,
285 ISAC_ISTA));
286 printk(KERN_DEBUG " STAR %x\n", readisac_3(sp->iobase,
287 ISAC_STAR));
288 printk(KERN_DEBUG " EXIR %x\n", readisac_3(sp->iobase,
289 ISAC_EXIR));
290 }
291 teles_hscxreport(sp, 0);
292 teles_hscxreport(sp, 1);
293 }
294
295
296
297
298
299 static void
300 hscx_sched_event(struct HscxState *hsp, int event)
301 {
302 hsp->event |= 1 << event;
303 queue_task_irq_off(&hsp->tqueue, &tq_immediate);
304 mark_bh(IMMEDIATE_BH);
305 }
306
307 static void
308 hscx_empty_fifo(struct HscxState *hsp, int count)
309 {
310 byte *ptr;
311 struct BufHeader *ibh = hsp->rcvibh;
312
313 if (hsp->sp->debug)
314 printk(KERN_DEBUG "hscx_empty_fifo\n");
315
316 if (hsp->rcvptr + count > BUFFER_SIZE(HSCX_RBUF_ORDER,
317 HSCX_RBUF_BPPS)) {
318 printk(KERN_WARNING
319 "hscx_empty_fifo: incoming packet too large\n");
320 WRITEHSCX_CMDR(hsp->membase, hsp->iobase, hsp->hscx, 0x80);
321 return;
322 }
323 ptr = DATAPTR(ibh);
324 ptr += hsp->rcvptr;
325
326 hsp->rcvptr += count;
327 if (hsp->membase) {
328 while (count--)
329 *ptr++ = readhscx_0(hsp->membase, hsp->hscx, 0x0);
330 writehscxCMDR_0(hsp->membase, hsp->hscx, 0x80);
331 } else {
332 readhscx_s(hsp->iobase, hsp->hscx, 0x3e, ptr, count);
333 writehscxCMDR_3(hsp->iobase, hsp->hscx, 0x80);
334 }
335 #ifdef BCHAN_VERBOSE
336 {
337 int i;
338 printk(KERN_DEBUG "hscx_empty_fifo");
339 for (i = 0; i < count; i++)
340 printk(" %2x", ptr[i]);
341 printk("\n");
342 }
343 #endif
344 }
345
346 static void
347 hscx_fill_fifo(struct HscxState *hsp)
348 {
349 struct BufHeader *ibh;
350 int more, count;
351 byte *ptr;
352
353 if (hsp->sp->debug)
354 printk(KERN_DEBUG "hscx_fill_fifo\n");
355
356 ibh = hsp->xmtibh;
357 if (!ibh)
358 return;
359
360 count = ibh->datasize - hsp->sendptr;
361 if (count <= 0)
362 return;
363
364 #if 0
365 if (!hsp->sendptr) {
366 ptr = DATAPTR(ibh);
367 printk(KERN_DEBUG "snd bytes %2x %2x %2x %2x %2x\n", ptr[0], ptr[1], ptr[2],
368 ptr[3], ptr[4]);
369 }
370 #endif
371
372 more = 0;
373 if (count > 32) {
374 more = !0;
375 count = 32;
376 }
377 ptr = DATAPTR(ibh);
378 ptr += hsp->sendptr;
379 hsp->sendptr += count;
380
381 #ifdef BCHAN_VERBOSE
382 {
383 int i;
384 printk(KERN_DEBUG "hscx_fill_fifo ");
385 for (i = 0; i < count; i++)
386 printk(" %2x", ptr[i]);
387 printk("\n");
388 }
389 #endif
390 if (hsp->membase) {
391 waitforXFW_0(hsp->membase, hsp->hscx);
392 while (count--)
393 writehscx_0(hsp->membase, hsp->hscx, 0x0, *ptr++);
394 writehscxCMDR_0(hsp->membase, hsp->hscx, more ? 0x8 : 0xa);
395 } else {
396 waitforXFW_3(hsp->iobase, hsp->hscx);
397 writehscx_s(hsp->iobase, hsp->hscx, 0x3e, ptr, count);
398 writehscxCMDR_3(hsp->iobase, hsp->hscx, more ? 0x8 : 0xa);
399 }
400 }
401
402 static inline void
403 hscx_interrupt(struct IsdnCardState *sp, byte val, byte hscx)
404 {
405 byte r;
406 struct HscxState *hsp = sp->hs + hscx;
407 int count;
408
409 if (!hsp->init)
410 return;
411
412 if (val & 0x80) {
413
414 r = READHSCX(hsp->membase, sp->iobase, hsp->hscx, HSCX_RSTA);
415 if ((r & 0xf0) != 0xa0) {
416 if (!r & 0x80)
417 printk(KERN_WARNING
418 "Teles: HSCX invalid frame\n");
419 if (r & 0x40)
420 printk(KERN_WARNING "Teles: HSCX RDO\n");
421 if (!r & 0x20)
422 printk(KERN_WARNING "Teles: HSCX CRC error\n");
423 if (hsp->rcvibh)
424 BufPoolRelease(hsp->rcvibh);
425 hsp->rcvibh = NULL;
426 WRITEHSCX_CMDR(hsp->membase, hsp->iobase, hsp->hscx,
427 0x80);
428 goto afterRME;
429 }
430 if (!hsp->rcvibh)
431 if (BufPoolGet(&hsp->rcvibh, &hsp->rbufpool,
432 GFP_ATOMIC, (void *) 1, 1)) {
433 printk(KERN_WARNING
434 "HSCX RME out of buffers at %ld\n",
435 jiffies);
436 WRITEHSCX_CMDR(hsp->membase, hsp->iobase,
437 hsp->hscx, 0x80);
438 goto afterRME;
439 } else
440 hsp->rcvptr = 0;
441
442 count = READHSCX(hsp->membase, sp->iobase, hsp->hscx,
443 HSCX_RBCL) & 0x1f;
444 if (count == 0)
445 count = 32;
446 hscx_empty_fifo(hsp, count);
447 hsp->rcvibh->datasize = hsp->rcvptr - 1;
448 BufQueueLink(&hsp->rq, hsp->rcvibh);
449 hsp->rcvibh = NULL;
450 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
451 }
452 afterRME:
453 if (val & 0x40) {
454 if (!hsp->rcvibh)
455 if (BufPoolGet(&hsp->rcvibh, &hsp->rbufpool,
456 GFP_ATOMIC, (void *) 1, 2)) {
457 printk(KERN_WARNING
458 "HSCX RME out of buffers at %ld\n",
459 jiffies);
460 WRITEHSCX_CMDR(hsp->membase, hsp->iobase,
461 hsp->hscx, 0x80);
462 goto afterRPF;
463 } else
464 hsp->rcvptr = 0;
465
466 hscx_empty_fifo(hsp, 32);
467 #ifdef VOICE
468 hsp->rcvibh->datasize = hsp->rcvptr - 1;
469 BufQueueLink(&hsp->rq, hsp->rcvibh);
470 hsp->rcvibh = NULL;
471 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
472 #endif
473 }
474 afterRPF:
475 if (val & 0x10) {
476 if (hsp->xmtibh)
477 if (hsp->xmtibh->datasize > hsp->sendptr) {
478 hscx_fill_fifo(hsp);
479 goto afterXPR;
480 } else {
481 if (hsp->releasebuf)
482 BufPoolRelease(hsp->xmtibh);
483 hsp->xmtibh = NULL;
484 hsp->sendptr = 0;
485 if (hsp->st->l4.l1writewakeup)
486 hsp->st->l4.l1writewakeup(hsp->st);
487 }
488 if (!BufQueueUnlink(&hsp->xmtibh, &hsp->sq)) {
489 hsp->releasebuf = !0;
490 hscx_fill_fifo(hsp);
491 } else
492 hscx_sched_event(hsp, HSCX_XMTBUFREADY);
493 }
494 afterXPR:
495 }
496
497
498
499
500
501 static void
502 isac_sched_event(struct IsdnCardState *sp, int event)
503 {
504 sp->event |= 1 << event;
505 queue_task_irq_off(&sp->tqueue, &tq_immediate);
506 mark_bh(IMMEDIATE_BH);
507 }
508
509 static void
510 empty_fifo(struct IsdnCardState *sp, int count)
511 {
512 byte *ptr;
513 struct BufHeader *ibh = sp->rcvibh;
514
515 if (sp->debug)
516 printk(KERN_DEBUG "empty_fifo\n");
517
518 if (sp->rcvptr >= 3072) {
519 printk(KERN_WARNING "empty_fifo rcvptr %d\n", sp->rcvptr);
520 return;
521 }
522 ptr = DATAPTR(ibh);
523 ptr += sp->rcvptr;
524 sp->rcvptr += count;
525
526 if (sp->membase) {
527 #ifdef DCHAN_VERBOSE
528 printk(KERN_DEBUG "empty_fifo ");
529 while (count--) {
530 *ptr = readisac_0(sp->membase, 0x0);
531 printk("%2x ", *ptr);
532 ptr++;
533 }
534 printk("\n");
535 #else
536 while (count--)
537 *ptr++ = readisac_0(sp->membase, 0x0);
538 #endif
539 writeisac_0(sp->membase, ISAC_CMDR, 0x80);
540 } else {
541 #ifdef DCHAN_VERBOSE
542 int i;
543 printk(KERN_DEBUG "empty_fifo ");
544 readisac_s(sp->iobase, 0x3e, ptr, count);
545 for (i = 0; i < count; i++)
546 printk("%2x ", ptr[i]);
547 printk("\n");
548 #else
549 readisac_s(sp->iobase, 0x3e, ptr, count);
550 #endif
551 writeisac_3(sp->iobase, ISAC_CMDR, 0x80);
552 }
553 }
554
555 static void
556 fill_fifo(struct IsdnCardState *sp)
557 {
558 struct BufHeader *ibh;
559 int count, more;
560 byte *ptr;
561
562 if (sp->debug)
563 printk(KERN_DEBUG "fill_fifo\n");
564
565 ibh = sp->xmtibh;
566 if (!ibh)
567 return;
568
569 count = ibh->datasize - sp->sendptr;
570 if (count <= 0)
571 return;
572 if (count >= 3072)
573 return;
574
575 more = 0;
576 if (count > 32) {
577 more = !0;
578 count = 32;
579 }
580 ptr = DATAPTR(ibh);
581 ptr += sp->sendptr;
582 sp->sendptr += count;
583
584 if (sp->membase) {
585 #ifdef DCHAN_VERBOSE
586 printk(KERN_DEBUG "fill_fifo ");
587 while (count--) {
588 writeisac_0(sp->membase, 0x0, *ptr);
589 printk("%2x ", *ptr);
590 ptr++;
591 }
592 printk("\n");
593 #else
594 while (count--)
595 writeisac_0(sp->membase, 0x0, *ptr++);
596 #endif
597 writeisac_0(sp->membase, ISAC_CMDR, more ? 0x8 : 0xa);
598 } else {
599 #ifdef DCHAN_VERBOSE
600 int i;
601 writeisac_s(sp->iobase, 0x3e, ptr, count);
602 printk(KERN_DEBUG "fill_fifo ");
603 for (i = 0; i < count; i++)
604 printk("%2x ", ptr[i]);
605 printk("\n");
606 #else
607 writeisac_s(sp->iobase, 0x3e, ptr, count);
608 #endif
609 writeisac_3(sp->iobase, ISAC_CMDR, more ? 0x8 : 0xa);
610 }
611 }
612
613 static int
614 act_wanted(struct IsdnCardState *sp)
615 {
616 struct PStack *st;
617
618 st = sp->stlist;
619 while (st)
620 if (st->l1.act_state)
621 return (!0);
622 else
623 st = st->next;
624 return (0);
625 }
626
627 static void
628 ph_command(struct IsdnCardState *sp, unsigned int command)
629 {
630 printk(KERN_DEBUG "ph_command %d\n", command);
631 WRITEISAC(sp->membase, sp->iobase, ISAC_CIX0, (command << 2) | 3);
632 }
633
634 static void
635 isac_new_ph(struct IsdnCardState *sp)
636 {
637 int enq;
638
639 enq = act_wanted(sp);
640
641 switch (sp->ph_state) {
642 case (0):
643 case (6):
644 if (enq)
645 ph_command(sp, 0);
646 else
647 ph_command(sp, 15);
648 break;
649 case (7):
650 if (enq)
651 ph_command(sp, 9);
652 break;
653 case (12):
654 case (13):
655 ph_command(sp, 8);
656 sp->ph_active = 5;
657 isac_sched_event(sp, ISAC_PHCHANGE);
658 if (!sp->xmtibh)
659 if (!BufQueueUnlink(&sp->xmtibh, &sp->sq))
660 sp->sendptr = 0;
661 if (sp->xmtibh)
662 fill_fifo(sp);
663 break;
664 case (4):
665 case (8):
666 break;
667 default:
668 sp->ph_active = 0;
669 break;
670 }
671 }
672
673 static void
674 teles_interrupt(int intno, void *dev_id, struct pt_regs *regs)
675 {
676 byte val, val2, r;
677 struct IsdnCardState *sp;
678 unsigned int count;
679 struct HscxState *hsp;
680
681 sp = (struct IsdnCardState *) irq2dev_map[intno];
682
683 if (!sp) {
684 printk(KERN_WARNING "Teles: Spurious interrupt!\n");
685 return;
686 }
687 val = READHSCX(sp->membase, sp->iobase, 1, HSCX_ISTA);
688
689 if (val & 0x01) {
690 hsp = sp->hs + 1;
691 printk(KERN_WARNING "HSCX B EXIR %x xmitbh %lx rcvibh %lx\n",
692 READHSCX(sp->membase, sp->iobase, 1, HSCX_EXIR),
693 (long) hsp->xmtibh,
694 (long) hsp->rcvibh);
695 }
696 if (val & 0xf8) {
697 if (sp->debug)
698 printk(KERN_DEBUG "HSCX B interrupt %x\n", val);
699 hscx_interrupt(sp, val, 1);
700 }
701 if (val & 0x02) {
702 printk(KERN_WARNING "HSCX A EXIR %x\n",
703 READHSCX(sp->membase, sp->iobase, 0, HSCX_EXIR));
704 }
705
706
707 if (sp->membase) {
708 if (val & 0x04) {
709 val = readhscx_0(sp->membase, 0, HSCX_ISTA);
710 if (sp->debug)
711 printk(KERN_DEBUG "HSCX A interrupt %x\n",
712 val);
713 hscx_interrupt(sp, val, 0);
714 }
715 } else {
716 val2 = readhscx_3(sp->iobase, 0, HSCX_ISTA);
717 if (sp->debug)
718 printk(KERN_DEBUG "HSCX A ISTA %x\n", val2);
719 if (val & 0x04) {
720 if (sp->debug)
721 printk(KERN_DEBUG "HSCX A interrupt %x\n",
722 val2);
723 hscx_interrupt(sp, val2, 0);
724 }
725 }
726
727
728 val = READISAC(sp->membase, sp->iobase, ISAC_ISTA);
729
730 if (sp->debug)
731 printk(KERN_DEBUG "ISAC interrupt %x\n", val);
732
733 if (val & 0x80) {
734
735 r = READISAC(sp->membase, sp->iobase, ISAC_RSTA);
736 if ((r & 0x70) != 0x20) {
737 if (r & 0x40)
738 printk(KERN_WARNING "Teles: ISAC RDO\n");
739 if (!r & 0x20)
740 printk(KERN_WARNING "Teles: ISAC CRC error\n");
741 if (sp->rcvibh)
742 BufPoolRelease(sp->rcvibh);
743 sp->rcvibh = NULL;
744 WRITEISAC(sp->membase, sp->iobase, ISAC_CMDR, 0x80);
745 goto afterRME;
746 }
747 if (!sp->rcvibh)
748 if (BufPoolGet(&(sp->rcvibh), &(sp->rbufpool),
749 GFP_ATOMIC,
750 (void *) 1, 3)) {
751 printk(KERN_WARNING
752 "ISAC RME out of buffers!\n");
753 WRITEISAC(sp->membase, sp->iobase,
754 ISAC_CMDR, 0x80);
755 goto afterRME;
756 } else
757 sp->rcvptr = 0;
758
759 count = READISAC(sp->membase, sp->iobase, ISAC_RBCL) & 0x1f;
760 if (count == 0)
761 count = 32;
762 empty_fifo(sp, count);
763 sp->rcvibh->datasize = sp->rcvptr;
764 BufQueueLink(&(sp->rq), sp->rcvibh);
765 sp->rcvibh = NULL;
766 isac_sched_event(sp, ISAC_RCVBUFREADY);
767 }
768 afterRME:
769 if (val & 0x40) {
770 if (!sp->rcvibh)
771 if (BufPoolGet(&(sp->rcvibh), &(sp->rbufpool),
772 GFP_ATOMIC,
773 (void *) 1, 4)) {
774 printk(KERN_WARNING
775 "ISAC RME out of buffers!\n");
776 WRITEISAC(sp->membase, sp->iobase,
777 ISAC_CMDR, 0x80);
778 goto afterRPF;
779 } else
780 sp->rcvptr = 0;
781 empty_fifo(sp, 32);
782 }
783 afterRPF:
784 if (val & 0x20) {
785 }
786 if (val & 0x10) {
787 if (sp->xmtibh)
788 if (sp->xmtibh->datasize > sp->sendptr) {
789 fill_fifo(sp);
790 goto afterXPR;
791 } else {
792 if (sp->releasebuf)
793 BufPoolRelease(sp->xmtibh);
794 sp->xmtibh = NULL;
795 sp->sendptr = 0;
796 }
797 if (!BufQueueUnlink(&sp->xmtibh, &sp->sq)) {
798 sp->releasebuf = !0;
799 fill_fifo(sp);
800 } else
801 isac_sched_event(sp, ISAC_XMTBUFREADY);
802 }
803 afterXPR:
804 if (val & 0x04) {
805 sp->ph_state = (READISAC(sp->membase, sp->iobase, ISAC_CIX0)
806 >> 2) & 0xf;
807 printk(KERN_DEBUG "l1state %d\n", sp->ph_state);
808 isac_new_ph(sp);
809 }
810 if (sp->membase) {
811 writeisac_0(sp->membase, ISAC_MASK, 0xFF);
812 writehscx_0(sp->membase, 0, HSCX_MASK, 0xFF);
813 writehscx_0(sp->membase, 1, HSCX_MASK, 0xFF);
814 writeisac_0(sp->membase, ISAC_MASK, 0x0);
815 writehscx_0(sp->membase, 0, HSCX_MASK, 0x0);
816 writehscx_0(sp->membase, 1, HSCX_MASK, 0x0);
817 } else {
818 writeisac_3(sp->iobase, ISAC_MASK, 0xFF);
819 writehscx_3(sp->iobase, 0, HSCX_MASK, 0xFF);
820 writehscx_3(sp->iobase, 1, HSCX_MASK, 0xFF);
821 writeisac_3(sp->iobase, ISAC_MASK, 0x0);
822 writehscx_3(sp->iobase, 0, HSCX_MASK, 0x0);
823 writehscx_3(sp->iobase, 1, HSCX_MASK, 0x0);
824 }
825 }
826
827
828
829
830
831 static void
832 act_ivated(struct IsdnCardState *sp)
833 {
834 struct PStack *st;
835
836 st = sp->stlist;
837 while (st) {
838 if (st->l1.act_state == 1) {
839 st->l1.act_state = 2;
840 st->l1.l1man(st, PH_ACTIVATE, NULL);
841 }
842 st = st->next;
843 }
844 }
845
846 static void
847 process_new_ph(struct IsdnCardState *sp)
848 {
849 if (sp->ph_active == 5)
850 act_ivated(sp);
851 }
852
853 static void
854 process_xmt(struct IsdnCardState *sp)
855 {
856 struct PStack *stptr;
857
858 if (sp->xmtibh)
859 return;
860
861 stptr = sp->stlist;
862 while (stptr != NULL)
863 if (stptr->l1.requestpull) {
864 stptr->l1.requestpull = 0;
865 stptr->l1.l1l2(stptr, PH_PULL_ACK, NULL);
866 break;
867 } else
868 stptr = stptr->next;
869 }
870
871 static void
872 process_rcv(struct IsdnCardState *sp)
873 {
874 struct BufHeader *ibh, *cibh;
875 struct PStack *stptr;
876 byte *ptr;
877 int found, broadc;
878 char tmp[64];
879
880 while (!BufQueueUnlink(&ibh, &sp->rq)) {
881 stptr = sp->stlist;
882 ptr = DATAPTR(ibh);
883 broadc = (ptr[1] >> 1) == 127;
884
885 if (broadc && sp->dlogflag && (!(ptr[0] >> 2)))
886 dlogframe(sp, ptr + 3, ibh->datasize - 3,
887 "Q.931 frame network->user broadcast");
888
889 if (broadc) {
890 while (stptr != NULL) {
891 if ((ptr[0] >> 2) == stptr->l2.sap)
892 if (!BufPoolGet(&cibh, &sp->rbufpool, GFP_ATOMIC,
893 (void *) 1, 5)) {
894 memcpy(DATAPTR(cibh), DATAPTR(ibh), ibh->datasize);
895 cibh->datasize = ibh->datasize;
896 stptr->l1.l1l2(stptr, PH_DATA, cibh);
897 } else
898 printk(KERN_WARNING "isdn broadcast buffer shortage\n");
899 stptr = stptr->next;
900 }
901 BufPoolRelease(ibh);
902 } else {
903 found = 0;
904 while (stptr != NULL)
905 if (((ptr[0] >> 2) == stptr->l2.sap) &&
906 ((ptr[1] >> 1) == stptr->l2.tei)) {
907 stptr->l1.l1l2(stptr, PH_DATA, ibh);
908 found = !0;
909 break;
910 } else
911 stptr = stptr->next;
912 if (!found) {
913
914
915
916
917
918 if ((!(ptr[0] >> 2)) && (!(ptr[2] & 0x01))) {
919 sprintf(tmp, "Q.931 frame network->user with tei %d (not for us)", ptr[1] >> 1);
920 dlogframe(sp, ptr + 4, ibh->datasize - 4, tmp);
921 }
922 BufPoolRelease(ibh);
923 }
924 }
925
926 }
927
928 }
929
930 static void
931 isac_bh(struct IsdnCardState *sp)
932 {
933 if (!sp)
934 return;
935
936 if (clear_bit(ISAC_PHCHANGE, &sp->event))
937 process_new_ph(sp);
938 if (clear_bit(ISAC_RCVBUFREADY, &sp->event))
939 process_rcv(sp);
940 if (clear_bit(ISAC_XMTBUFREADY, &sp->event))
941 process_xmt(sp);
942 }
943
944
945 static void
946 hscx_process_xmt(struct HscxState *hsp)
947 {
948 struct PStack *st = hsp->st;
949
950 if (hsp->xmtibh)
951 return;
952
953 if (st->l1.requestpull) {
954 st->l1.requestpull = 0;
955 st->l1.l1l2(st, PH_PULL_ACK, NULL);
956 }
957 if (!hsp->active)
958 if ((!hsp->xmtibh) && (!hsp->sq.head))
959 modehscx(hsp, 0, 0);
960 }
961
962 static void
963 hscx_process_rcv(struct HscxState *hsp)
964 {
965 struct BufHeader *ibh;
966
967 #ifdef DEBUG_MAGIC
968 if (hsp->magic != 301270) {
969 printk(KERN_DEBUG "hscx_process_rcv magic not 301270\n");
970 return;
971 }
972 #endif
973 while (!BufQueueUnlink(&ibh, &hsp->rq)) {
974 hsp->st->l1.l1l2(hsp->st, PH_DATA, ibh);
975 }
976 }
977
978 static void
979 hscx_bh(struct HscxState *hsp)
980 {
981
982 if (!hsp)
983 return;
984
985 if (clear_bit(HSCX_RCVBUFREADY, &hsp->event))
986 hscx_process_rcv(hsp);
987 if (clear_bit(HSCX_XMTBUFREADY, &hsp->event))
988 hscx_process_xmt(hsp);
989
990 }
991
992
993
994
995
996 static void
997 restart_ph(struct IsdnCardState *sp)
998 {
999 switch (sp->ph_active) {
1000 case (0):
1001 if (sp->ph_state == 6)
1002 ph_command(sp, 0);
1003 else
1004 ph_command(sp, 1);
1005 sp->ph_active = 1;
1006 break;
1007 }
1008 }
1009
1010 static void
1011 initisac(byte * cardmem, int iobase)
1012 {
1013 if (cardmem) {
1014 writeisac_0(cardmem, ISAC_MASK, 0xff);
1015 writeisac_0(cardmem, ISAC_ADF2, 0x0);
1016 writeisac_0(cardmem, ISAC_SPCR, 0xa);
1017 writeisac_0(cardmem, ISAC_ADF1, 0x2);
1018 writeisac_0(cardmem, ISAC_STCR, 0x70);
1019 writeisac_0(cardmem, ISAC_MODE, 0xc9);
1020 writeisac_0(cardmem, ISAC_CMDR, 0x41);
1021 writeisac_0(cardmem, ISAC_CIX0, (1 << 2) | 3);
1022 } else {
1023 writeisac_3(iobase, ISAC_MASK, 0xff);
1024 writeisac_3(iobase, ISAC_ADF2, 0x80);
1025 writeisac_3(iobase, ISAC_SQXR, 0x2f);
1026 writeisac_3(iobase, ISAC_SPCR, 0x00);
1027 writeisac_3(iobase, ISAC_ADF1, 0x02);
1028 writeisac_3(iobase, ISAC_STCR, 0x70);
1029 writeisac_3(iobase, ISAC_MODE, 0xc9);
1030 writeisac_3(iobase, ISAC_TIMR, 0x00);
1031 writeisac_3(iobase, ISAC_ADF1, 0x00);
1032 writeisac_3(iobase, ISAC_CMDR, 0x41);
1033 writeisac_3(iobase, ISAC_CIX0, (1 << 2) | 3);
1034 }
1035 }
1036
1037 static int
1038 checkcard(int cardnr)
1039 {
1040 int timout;
1041 byte cfval, val;
1042 struct IsdnCard *card = cards + cardnr;
1043
1044 if (!card->iobase) {
1045 if (card->membase) {
1046 printk(KERN_NOTICE
1047 "Teles 8 assumed, mem: %lx irq: %d proto: %s\n",
1048 (long) card->membase, card->interrupt,
1049 (card->protocol == ISDN_PTYPE_1TR6) ?
1050 "1TR6" : "EDSS1");
1051 printk(KERN_INFO "HSCX version A: %x B:%x\n",
1052 readhscx_0(card->membase, 0, HSCX_VSTR) & 0xf,
1053 readhscx_0(card->membase, 1, HSCX_VSTR) & 0xf);
1054 }
1055 } else {
1056 switch (card->iobase) {
1057 case 0x180:
1058 case 0x280:
1059 case 0x380:
1060 printk(KERN_INFO "teles: port 0x%x specified, assuming 0x%x\n",
1061 card->iobase, (card->iobase | 0xc00));
1062 card->iobase |= 0xc00;
1063 break;
1064 }
1065 if (check_region(card->iobase, 8)) {
1066 printk(KERN_WARNING
1067 "teles: ports %x-%x already in use\n",
1068 card->iobase,
1069 card->iobase + 8 );
1070 return -1;
1071 }
1072 switch (card->interrupt) {
1073 case 2:
1074 cfval = 0x00;
1075 break;
1076 case 3:
1077 cfval = 0x02;
1078 break;
1079 case 4:
1080 cfval = 0x04;
1081 break;
1082 case 5:
1083 cfval = 0x06;
1084 break;
1085 case 10:
1086 cfval = 0x08;
1087 break;
1088 case 11:
1089 cfval = 0x0A;
1090 break;
1091 case 12:
1092 cfval = 0x0C;
1093 break;
1094 case 15:
1095 cfval = 0x0E;
1096 break;
1097 default:
1098 cfval = 0x00;
1099 break;
1100 }
1101 if (card->membase) {
1102 cfval |= (((unsigned int) card->membase >> 9) & 0xF0);
1103
1104 if (bytein(card->iobase + 0) != 0x51) {
1105 printk(KERN_INFO "XXX Byte at %x is %x\n",
1106 card->iobase + 0,
1107 bytein(card->iobase + 0));
1108 return -2;
1109 }
1110 if (bytein(card->iobase + 1) != 0x93) {
1111 printk(KERN_INFO "XXX Byte at %x is %x\n",
1112 card->iobase + 1,
1113 bytein(card->iobase + 1));
1114 return -2;
1115 }
1116 val = bytein(card->iobase + 2);
1117
1118
1119 if (val != 0x1e && val != 0x1f) {
1120 printk(KERN_INFO "XXX Byte at %x is %x\n",
1121 card->iobase + 2,
1122 bytein(card->iobase + 2));
1123 return -2;
1124 }
1125 }
1126 request_region(card->iobase, 8, "teles");
1127 cli();
1128 timout = jiffies + (HZ / 10) + 1;
1129 byteout(card->iobase + 4, cfval);
1130 sti();
1131 while (jiffies <= timout);
1132
1133 cli();
1134 timout = jiffies + (HZ / 10) + 1;
1135 byteout(card->iobase + 4, cfval | 1);
1136 sti();
1137 while (jiffies <= timout);
1138
1139 if (card->membase)
1140 printk(KERN_NOTICE
1141 "Teles 16.0 found, io: %x mem: %lx irq: %d proto: %s\n",
1142 card->iobase, (long) card->membase,
1143 card->interrupt,
1144 (card->protocol == ISDN_PTYPE_1TR6) ?
1145 "1TR6" : "EDSS1");
1146 else
1147 printk(KERN_NOTICE
1148 "Teles 16.3 found, io: %x irq: %d proto: %s\n",
1149 card->iobase, card->interrupt,
1150 (card->protocol == ISDN_PTYPE_1TR6) ?
1151 "1TR6" : "EDSS1");
1152 printk(KERN_INFO "HSCX version A:%x B:%x\n",
1153 READHSCX(card->membase, card->iobase, 0,
1154 HSCX_VSTR) & 0xf,
1155 READHSCX(card->membase, card->iobase, 1,
1156 HSCX_VSTR) & 0xf);
1157
1158 }
1159 if (card->membase) {
1160 cli();
1161 timout = jiffies + (HZ / 5) + 1;
1162 *(byte *) (card->membase + 0x80) = 0;
1163 sti();
1164 while (jiffies <= timout);
1165
1166 cli();
1167 *(byte *) (card->membase + 0x80) = 1;
1168 timout = jiffies + (HZ / 5) + 1;
1169 sti();
1170 while (jiffies <= timout);
1171 }
1172 return (0);
1173 }
1174
1175 void
1176 modehscx(struct HscxState *hs, int mode,
1177 int ichan)
1178 {
1179 struct IsdnCardState *sp = hs->sp;
1180 int hscx = hs->hscx;
1181
1182 printk(KERN_DEBUG "modehscx hscx %d mode %d ichan %d\n",
1183 hscx, mode, ichan);
1184
1185 if (hscx == 0)
1186 ichan = 1 - ichan;
1187
1188 if (sp->membase) {
1189 writehscx_0(sp->membase, hscx, HSCX_CCR1, 0x85);
1190 writehscx_0(sp->membase, hscx, HSCX_XAD1, 0xFF);
1191 writehscx_0(sp->membase, hscx, HSCX_XAD2, 0xFF);
1192 writehscx_0(sp->membase, hscx, HSCX_RAH2, 0xFF);
1193 writehscx_0(sp->membase, hscx, HSCX_XBCH, 0x0);
1194
1195 switch (mode) {
1196 case (0):
1197 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1198 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0xff);
1199 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0xff);
1200 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1201 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1202 writehscx_0(sp->membase, hscx, HSCX_MODE, 0x84);
1203 break;
1204 case (1):
1205 if (ichan == 0) {
1206 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1207 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x7);
1208 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x7);
1209 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1210 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1211 } else {
1212 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1213 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x3);
1214 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x3);
1215 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1216 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1217 }
1218 writehscx_0(sp->membase, hscx, HSCX_MODE, 0xe4);
1219 writehscx_0(sp->membase, hscx, HSCX_CMDR, 0x41);
1220 break;
1221 case (2):
1222 if (ichan == 0) {
1223 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1224 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x7);
1225 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x7);
1226 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1227 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1228 } else {
1229 writehscx_0(sp->membase, hscx, HSCX_CCR2, 0x30);
1230 writehscx_0(sp->membase, hscx, HSCX_TSAX, 0x3);
1231 writehscx_0(sp->membase, hscx, HSCX_TSAR, 0x3);
1232 writehscx_0(sp->membase, hscx, HSCX_XCCR, 7);
1233 writehscx_0(sp->membase, hscx, HSCX_RCCR, 7);
1234 }
1235 writehscx_0(sp->membase, hscx, HSCX_MODE, 0x8c);
1236 writehscx_0(sp->membase, hscx, HSCX_CMDR, 0x41);
1237 break;
1238 }
1239 writehscx_0(sp->membase, hscx, HSCX_ISTA, 0x00);
1240 } else {
1241 writehscx_3(sp->iobase, hscx, HSCX_CCR1, 0x85);
1242 writehscx_3(sp->iobase, hscx, HSCX_XAD1, 0xFF);
1243 writehscx_3(sp->iobase, hscx, HSCX_XAD2, 0xFF);
1244 writehscx_3(sp->iobase, hscx, HSCX_RAH2, 0xFF);
1245 writehscx_3(sp->iobase, hscx, HSCX_XBCH, 0x00);
1246 writehscx_3(sp->iobase, hscx, HSCX_RLCR, 0x00);
1247
1248 switch (mode) {
1249 case (0):
1250 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1251 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0xff);
1252 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0xff);
1253 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1254 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1255 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0x84);
1256 break;
1257 case (1):
1258 if (ichan == 0) {
1259 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1260 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x2f);
1261 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x2f);
1262 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1263 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1264 } else {
1265 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1266 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x3);
1267 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x3);
1268 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1269 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1270 }
1271 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0xe4);
1272 writehscx_3(sp->iobase, hscx, HSCX_CMDR, 0x41);
1273 break;
1274 case (2):
1275 if (ichan == 0) {
1276 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1277 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x2f);
1278 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x2f);
1279 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1280 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1281 } else {
1282 writehscx_3(sp->iobase, hscx, HSCX_CCR2, 0x30);
1283 writehscx_3(sp->iobase, hscx, HSCX_TSAX, 0x3);
1284 writehscx_3(sp->iobase, hscx, HSCX_TSAR, 0x3);
1285 writehscx_3(sp->iobase, hscx, HSCX_XCCR, 7);
1286 writehscx_3(sp->iobase, hscx, HSCX_RCCR, 7);
1287 }
1288 writehscx_3(sp->iobase, hscx, HSCX_MODE, 0x8c);
1289 writehscx_3(sp->iobase, hscx, HSCX_CMDR, 0x41);
1290 break;
1291 }
1292 writehscx_3(sp->iobase, hscx, HSCX_ISTA, 0x00);
1293 }
1294 }
1295
1296 void
1297 teles_addlist(struct IsdnCardState *sp,
1298 struct PStack *st)
1299 {
1300 st->next = sp->stlist;
1301 sp->stlist = st;
1302 }
1303
1304 void
1305 teles_rmlist(struct IsdnCardState *sp,
1306 struct PStack *st)
1307 {
1308 struct PStack *p;
1309
1310 if (sp->stlist == st)
1311 sp->stlist = st->next;
1312 else {
1313 p = sp->stlist;
1314 while (p)
1315 if (p->next == st) {
1316 p->next = st->next;
1317 return;
1318 } else
1319 p = p->next;
1320 }
1321 }
1322
1323
1324 static void
1325 teles_l2l1(struct PStack *st, int pr,
1326 struct BufHeader *ibh)
1327 {
1328 struct IsdnCardState *sp = (struct IsdnCardState *)
1329 st->l1.hardware;
1330
1331
1332 switch (pr) {
1333 case (PH_DATA):
1334 if (sp->xmtibh)
1335 BufQueueLink(&sp->sq, ibh);
1336 else {
1337 sp->xmtibh = ibh;
1338 sp->sendptr = 0;
1339 sp->releasebuf = !0;
1340 fill_fifo(sp);
1341 }
1342 break;
1343 case (PH_DATA_PULLED):
1344 if (sp->xmtibh) {
1345 printk(KERN_DEBUG "teles_l2l1: this shouldn't happen\n");
1346 break;
1347 }
1348 sp->xmtibh = ibh;
1349 sp->sendptr = 0;
1350 sp->releasebuf = 0;
1351 fill_fifo(sp);
1352 break;
1353 case (PH_REQUEST_PULL):
1354 if (!sp->xmtibh) {
1355 st->l1.requestpull = 0;
1356 st->l1.l1l2(st, PH_PULL_ACK, NULL);
1357 } else
1358 st->l1.requestpull = !0;
1359 break;
1360 }
1361 }
1362
1363 static void
1364 check_ph_act(struct IsdnCardState *sp)
1365 {
1366 struct PStack *st = sp->stlist;
1367
1368 while (st) {
1369 if (st->l1.act_state)
1370 return;
1371 st = st->next;
1372 }
1373 sp->ph_active = 0;
1374 }
1375
1376 static void
1377 teles_manl1(struct PStack *st, int pr,
1378 void *arg)
1379 {
1380 struct IsdnCardState *sp = (struct IsdnCardState *)
1381 st->l1.hardware;
1382 long flags;
1383
1384 switch (pr) {
1385 case (PH_ACTIVATE):
1386 save_flags(flags);
1387 cli();
1388 if (sp->ph_active == 5) {
1389 st->l1.act_state = 2;
1390 restore_flags(flags);
1391 st->l1.l1man(st, PH_ACTIVATE, NULL);
1392 } else {
1393 st->l1.act_state = 1;
1394 if (sp->ph_active == 0)
1395 restart_ph(sp);
1396 restore_flags(flags);
1397 }
1398 break;
1399 case (PH_DEACTIVATE):
1400 st->l1.act_state = 0;
1401 check_ph_act(sp);
1402 break;
1403 }
1404 }
1405
1406 static void
1407 teles_l2l1discardq(struct PStack *st, int pr,
1408 void *heldby, int releasetoo)
1409 {
1410 struct IsdnCardState *sp = (struct IsdnCardState *) st->l1.hardware;
1411
1412 #ifdef DEBUG_MAGIC
1413 if (sp->magic != 301271) {
1414 printk(KERN_DEBUG "isac_discardq magic not 301271\n");
1415 return;
1416 }
1417 #endif
1418
1419 BufQueueDiscard(&sp->sq, pr, heldby, releasetoo);
1420 }
1421
1422 void
1423 setstack_teles(struct PStack *st, struct IsdnCardState *sp)
1424 {
1425 st->l1.hardware = sp;
1426 st->l1.sbufpool = &(sp->sbufpool);
1427 st->l1.rbufpool = &(sp->rbufpool);
1428 st->l1.smallpool = &(sp->smallpool);
1429 st->protocol = sp->teistack->protocol;
1430
1431 setstack_tei(st);
1432
1433 st->l1.stlistp = &(sp->stlist);
1434 st->l1.act_state = 0;
1435 st->l2.l2l1 = teles_l2l1;
1436 st->l2.l2l1discardq = teles_l2l1discardq;
1437 st->ma.manl1 = teles_manl1;
1438 st->l1.requestpull = 0;
1439 }
1440
1441 void
1442 init_hscxstate(struct IsdnCardState *sp,
1443 int hscx)
1444 {
1445 struct HscxState *hsp = sp->hs + hscx;
1446
1447 hsp->sp = sp;
1448 hsp->hscx = hscx;
1449 hsp->membase = sp->membase;
1450 hsp->iobase = sp->iobase;
1451
1452 hsp->tqueue.next = 0;
1453 hsp->tqueue.sync = 0;
1454 hsp->tqueue.routine = (void *) (void *) hscx_bh;
1455 hsp->tqueue.data = hsp;
1456
1457 hsp->inuse = 0;
1458 hsp->init = 0;
1459 hsp->active = 0;
1460
1461 #ifdef DEBUG_MAGIC
1462 hsp->magic = 301270;
1463 #endif
1464 }
1465
1466 void
1467 initcard(int cardnr)
1468 {
1469 struct IsdnCardState *sp;
1470 struct IsdnCard *card = cards + cardnr;
1471
1472 sp = (struct IsdnCardState *)
1473 Smalloc(sizeof(struct IsdnCardState), GFP_KERNEL,
1474 "struct IsdnCardState");
1475
1476 sp->membase = card->membase;
1477 sp->iobase = card->iobase;
1478 sp->cardnr = cardnr;
1479
1480 BufPoolInit(&sp->sbufpool, ISAC_SBUF_ORDER, ISAC_SBUF_BPPS,
1481 ISAC_SBUF_MAXPAGES);
1482 BufPoolInit(&sp->rbufpool, ISAC_RBUF_ORDER, ISAC_RBUF_BPPS,
1483 ISAC_RBUF_MAXPAGES);
1484 BufPoolInit(&sp->smallpool, ISAC_SMALLBUF_ORDER, ISAC_SMALLBUF_BPPS,
1485 ISAC_SMALLBUF_MAXPAGES);
1486
1487 sp->dlogspace = Smalloc(4096, GFP_KERNEL, "dlogspace");
1488
1489 initisac(card->membase, card->iobase);
1490
1491 sp->rcvibh = NULL;
1492 sp->rcvptr = 0;
1493 sp->xmtibh = NULL;
1494 sp->sendptr = 0;
1495 sp->event = 0;
1496 sp->tqueue.next = 0;
1497 sp->tqueue.sync = 0;
1498 sp->tqueue.routine = (void *) (void *) isac_bh;
1499 sp->tqueue.data = sp;
1500
1501 BufQueueInit(&sp->rq);
1502 BufQueueInit(&sp->sq);
1503
1504 sp->stlist = NULL;
1505
1506 sp->ph_active = 0;
1507
1508 sp->dlogflag = 0;
1509 sp->debug = 0;
1510
1511 sp->releasebuf = 0;
1512 #ifdef DEBUG_MAGIC
1513 sp->magic = 301271;
1514 #endif
1515
1516 cards[sp->cardnr].sp = sp;
1517
1518 init_hscxstate(sp, 0);
1519 init_hscxstate(sp, 1);
1520
1521 modehscx(sp->hs, 0, 0);
1522 modehscx(sp->hs + 1, 0, 0);
1523
1524 WRITEISAC(sp->membase, sp->iobase, ISAC_MASK, 0x0);
1525 }
1526
1527 static int
1528 get_irq(int cardnr)
1529 {
1530 struct IsdnCard *card = cards + cardnr;
1531 long flags;
1532
1533 save_flags(flags);
1534 cli();
1535 if (request_irq(card->interrupt, &teles_interrupt,
1536 SA_INTERRUPT, "teles", NULL)) {
1537 printk(KERN_WARNING "Teles couldn't get interrupt %d\n",
1538 card->interrupt);
1539 restore_flags(flags);
1540 return (!0);
1541 }
1542 irq2dev_map[card->interrupt] = (void *) card->sp;
1543 restore_flags(flags);
1544 return (0);
1545 }
1546
1547 static void
1548 release_irq(int cardnr)
1549 {
1550 struct IsdnCard *card = cards + cardnr;
1551
1552 irq2dev_map[card->interrupt] = NULL;
1553 free_irq(card->interrupt, NULL);
1554 }
1555
1556 void
1557 close_hscxstate(struct HscxState *hs)
1558 {
1559 modehscx(hs, 0, 0);
1560 hs->inuse = 0;
1561
1562 if (hs->init) {
1563 BufPoolFree(&hs->smallpool);
1564 BufPoolFree(&hs->rbufpool);
1565 BufPoolFree(&hs->sbufpool);
1566 }
1567 hs->init = 0;
1568 }
1569
1570 void
1571 closecard(int cardnr)
1572 {
1573 struct IsdnCardState *sp = cards[cardnr].sp;
1574
1575 cards[cardnr].sp = NULL;
1576
1577 Sfree(sp->dlogspace);
1578
1579 BufPoolFree(&sp->smallpool);
1580 BufPoolFree(&sp->rbufpool);
1581 BufPoolFree(&sp->sbufpool);
1582
1583 close_hscxstate(sp->hs + 1);
1584 close_hscxstate(sp->hs);
1585
1586 if (cards[cardnr].iobase)
1587 release_region(cards[cardnr].iobase, 8);
1588
1589 Sfree((void *) sp);
1590 }
1591
1592 void
1593 teles_shiftcards(int idx)
1594 {
1595 int i;
1596
1597 for (i = idx; i < 15; i++)
1598 memcpy(&cards[i],&cards[i+1],sizeof(cards[i]));
1599 }
1600
1601 int
1602 teles_inithardware(void)
1603 {
1604 int foundcards = 0;
1605 int i = 0;
1606
1607 while (i < nrcards) {
1608 if (!cards[i].protocol)
1609 break;
1610 switch (checkcard(i)) {
1611 case (0):
1612 initcard(i);
1613 if (get_irq(i)) {
1614 closecard(i);
1615 teles_shiftcards(i);
1616 } else {
1617 foundcards++;
1618 i++;
1619 }
1620 break;
1621 case (-1):
1622 teles_shiftcards(i);
1623 break;
1624 case (-2):
1625 release_region(cards[i].iobase, 8);
1626 teles_shiftcards(i);
1627 printk(KERN_WARNING "NO Teles card found at 0x%x!\n", cards[i].iobase);
1628 break;
1629 }
1630 }
1631 return foundcards;
1632 }
1633
1634 void
1635 teles_closehardware(void)
1636 {
1637 int i;
1638
1639 for (i = 0; i < nrcards; i++)
1640 if (cards[i].sp) {
1641 release_irq(i);
1642 closecard(i);
1643 }
1644 }
1645
1646 static void
1647 hscx_l2l1(struct PStack *st, int pr,
1648 struct BufHeader *ibh)
1649 {
1650 struct IsdnCardState *sp = (struct IsdnCardState *)
1651 st->l1.hardware;
1652 struct HscxState *hsp = sp->hs + st->l1.hscx;
1653
1654 switch (pr) {
1655 case (PH_DATA):
1656 if (hsp->xmtibh)
1657 BufQueueLink(&hsp->sq, ibh);
1658 else {
1659 hsp->xmtibh = ibh;
1660 hsp->sendptr = 0;
1661 hsp->releasebuf = !0;
1662 hscx_fill_fifo(hsp);
1663 }
1664 break;
1665 case (PH_DATA_PULLED):
1666 if (hsp->xmtibh) {
1667 printk(KERN_DEBUG "hscx_l2l1: this shouldn't happen\n");
1668 break;
1669 }
1670 hsp->xmtibh = ibh;
1671 hsp->sendptr = 0;
1672 hsp->releasebuf = 0;
1673 hscx_fill_fifo(hsp);
1674 break;
1675 case (PH_REQUEST_PULL):
1676 if (!hsp->xmtibh) {
1677 st->l1.requestpull = 0;
1678 st->l1.l1l2(st, PH_PULL_ACK, NULL);
1679 } else
1680 st->l1.requestpull = !0;
1681 break;
1682 }
1683
1684 }
1685
1686 extern struct IsdnBuffers *tracebuf;
1687
1688 static void
1689 hscx_l2l1discardq(struct PStack *st, int pr, void *heldby,
1690 int releasetoo)
1691 {
1692 struct IsdnCardState *sp = (struct IsdnCardState *)
1693 st->l1.hardware;
1694 struct HscxState *hsp = sp->hs + st->l1.hscx;
1695
1696 #ifdef DEBUG_MAGIC
1697 if (hsp->magic != 301270) {
1698 printk(KERN_DEBUG "hscx_discardq magic not 301270\n");
1699 return;
1700 }
1701 #endif
1702
1703 BufQueueDiscard(&hsp->sq, pr, heldby, releasetoo);
1704 }
1705
1706 static int
1707 open_hscxstate(struct IsdnCardState *sp,
1708 int hscx)
1709 {
1710 struct HscxState *hsp = sp->hs + hscx;
1711
1712 if (!hsp->init) {
1713 BufPoolInit(&hsp->sbufpool, HSCX_SBUF_ORDER, HSCX_SBUF_BPPS,
1714 HSCX_SBUF_MAXPAGES);
1715 BufPoolInit(&hsp->rbufpool, HSCX_RBUF_ORDER, HSCX_RBUF_BPPS,
1716 HSCX_RBUF_MAXPAGES);
1717 BufPoolInit(&hsp->smallpool, HSCX_SMALLBUF_ORDER, HSCX_SMALLBUF_BPPS,
1718 HSCX_SMALLBUF_MAXPAGES);
1719 }
1720 hsp->init = !0;
1721
1722 BufQueueInit(&hsp->rq);
1723 BufQueueInit(&hsp->sq);
1724
1725 hsp->releasebuf = 0;
1726 hsp->rcvibh = NULL;
1727 hsp->xmtibh = NULL;
1728 hsp->rcvptr = 0;
1729 hsp->sendptr = 0;
1730 hsp->event = 0;
1731 return (0);
1732 }
1733
1734 static void
1735 hscx_manl1(struct PStack *st, int pr,
1736 void *arg)
1737 {
1738 struct IsdnCardState *sp = (struct IsdnCardState *)
1739 st->l1.hardware;
1740 struct HscxState *hsp = sp->hs + st->l1.hscx;
1741
1742 switch (pr) {
1743 case (PH_ACTIVATE):
1744 hsp->active = !0;
1745 modehscx(hsp, st->l1.hscxmode, st->l1.hscxchannel);
1746 st->l1.l1man(st, PH_ACTIVATE, NULL);
1747 break;
1748 case (PH_DEACTIVATE):
1749 if (!hsp->xmtibh)
1750 modehscx(hsp, 0, 0);
1751
1752 hsp->active = 0;
1753 break;
1754 }
1755 }
1756
1757 int
1758 setstack_hscx(struct PStack *st, struct HscxState *hs)
1759 {
1760 if (open_hscxstate(st->l1.hardware, hs->hscx))
1761 return (-1);
1762
1763 st->l1.hscx = hs->hscx;
1764 st->l2.l2l1 = hscx_l2l1;
1765 st->ma.manl1 = hscx_manl1;
1766 st->l2.l2l1discardq = hscx_l2l1discardq;
1767
1768 st->l1.sbufpool = &hs->sbufpool;
1769 st->l1.rbufpool = &hs->rbufpool;
1770 st->l1.smallpool = &hs->smallpool;
1771 st->l1.act_state = 0;
1772 st->l1.requestpull = 0;
1773
1774 hs->st = st;
1775 return (0);
1776 }
1777
1778 void
1779 teles_reportcard(int cardnr)
1780 {
1781
1782 printk(KERN_DEBUG "teles_reportcard\n");
1783
1784 }
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