include/linux/serial

/* */
   1 /*
   2  * include/linux/serial.h
   3  *
   4  * Copyright (C) 1992, 1994 by Theodore Ts'o.
   5  * 
   6  * Redistribution of this file is permitted under the terms of the GNU 
   7  * Public License (GPL)
   8  * 
   9  * These are the UART port assignments, expressed as offsets from the base
  10  * register.  These assignments should hold for any serial port based on
  11  * a 8250, 16450, or 16550(A).
  12  */
  13 
  14 #ifndef _LINUX_SERIAL_REG_H
  15 #define _LINUX_SERIAL_REG_H
  16 
  17 #define UART_RX         0       /* In:  Receive buffer (DLAB=0) */
  18 #define UART_TX         0       /* Out: Transmit buffer (DLAB=0) */
  19 #define UART_DLL        0       /* Out: Divisor Latch Low (DLAB=1) */
  20 #define UART_DLM        1       /* Out: Divisor Latch High (DLAB=1) */
  21 #define UART_IER        1       /* Out: Interrupt Enable Register */
  22 #define UART_IIR        2       /* In:  Interrupt ID Register */
  23 #define UART_FCR        2       /* Out: FIFO Control Register */
  24 #define UART_EFR        2       /* I/O: Extended Features Register */
  25                                 /* (DLAB=1, 16C660 only) */
  26 #define UART_LCR        3       /* Out: Line Control Register */
  27 #define UART_MCR        4       /* Out: Modem Control Register */
  28 #define UART_LSR        5       /* In:  Line Status Register */
  29 #define UART_MSR        6       /* In:  Modem Status Register */
  30 #define UART_SCR        7       /* I/O: Scratch Register */
  31 
  32 /*
  33  * These are the definitions for the FIFO Control Register
  34  * (16650 only)
  35  */
  36 #define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
  37 #define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
  38 #define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
  39 #define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
  40 #define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
  41 #define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
  42 #define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
  43 #define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
  44 #define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
  45 /* 16650 redefinitions */
  46 #define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */
  47 #define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */
  48 #define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
  49 #define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */
  50 #define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */
  51 #define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */
  52 #define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
  53 #define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */
  54 
  55 /*
  56  * These are the definitions for the Line Control Register
  57  * 
  58  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
  59  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  60  */
  61 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  62 #define UART_LCR_SBC    0x40    /* Set break control */
  63 #define UART_LCR_SPAR   0x20    /* Stick parity (?) */
  64 #define UART_LCR_EPAR   0x10    /* Even parity select */
  65 #define UART_LCR_PARITY 0x08    /* Parity Enable */
  66 #define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
  67 #define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
  68 #define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
  69 #define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
  70 #define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
  71 
  72 /*
  73  * These are the definitions for the Line Status Register
  74  */
  75 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  76 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  77 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  78 #define UART_LSR_FE     0x08    /* Frame error indicator */
  79 #define UART_LSR_PE     0x04    /* Parity error indicator */
  80 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  81 #define UART_LSR_DR     0x01    /* Receiver data ready */
  82 
  83 /*
  84  * These are the definitions for the Interrupt Identification Register
  85  */
  86 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  87 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  88 
  89 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  90 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  91 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  92 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  93 
  94 /*
  95  * These are the definitions for the Interrupt Enable Register
  96  */
  97 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  98 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  99 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
 100 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
 101 
 102 /*
 103  * These are the definitions for the Modem Control Register
 104  */
 105 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
 106 #define UART_MCR_OUT2   0x08    /* Out2 complement */
 107 #define UART_MCR_OUT1   0x04    /* Out1 complement */
 108 #define UART_MCR_RTS    0x02    /* RTS complement */
 109 #define UART_MCR_DTR    0x01    /* DTR complement */
 110 
 111 /*
 112  * These are the definitions for the Modem Status Register
 113  */
 114 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
 115 #define UART_MSR_RI     0x40    /* Ring Indicator */
 116 #define UART_MSR_DSR    0x20    /* Data Set Ready */
 117 #define UART_MSR_CTS    0x10    /* Clear to Send */
 118 #define UART_MSR_DDCD   0x08    /* Delta DCD */
 119 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
 120 #define UART_MSR_DDSR   0x02    /* Delta DSR */
 121 #define UART_MSR_DCTS   0x01    /* Delta CTS */
 122 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 123 
 124 /*
 125  * These are the definitions for the Extended Features Register
 126  * (StarTech 16C660 only, when DLAB=1)
 127  */
 128 #define UART_EFR_CTS    0x80    /* CTS flow control */
 129 #define UART_EFR_RTS    0x40    /* RTS flow control */
 130 #define UART_EFR_SCD    0x20    /* Special character detect */
 131 #define UART_EFR_ENI    0x10    /* Enhanced Interrupt */
 132 /*
 133  * the low four bits control software flow control
 134  */
 135 
 136 #endif /* _LINUX_SERIAL_REG_H */
 137
/* */
root/include/linux/serial_reg.h

INCLUDED FROM
